diff options
Diffstat (limited to 'sim/resolver')
| -rw-r--r-- | sim/resolver/makefile | 68 | ||||
| -rw-r--r-- | sim/resolver/makefile.sources | 21 |
2 files changed, 89 insertions, 0 deletions
diff --git a/sim/resolver/makefile b/sim/resolver/makefile new file mode 100644 index 0000000..ac0a168 --- /dev/null +++ b/sim/resolver/makefile @@ -0,0 +1,68 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with ModelSim, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# assign variable PROJECT with the top level project name +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of testbench t_$(PROJECT).vhd +################################################################### + +PROJECT = resolver + +include ./makefile.sources + +# Add here the testbench file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/cntupdn_rtl.vhd \ +../../src/t_$(PROJECT).vhd + +include ../makefile + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## DigitaltechnikPraktikum +## | +## +---src +## | and2gate_equation.vhd +## | invgate_equation.vhd +## | mux2to1_structure.vhd +## | or2gate_equation.vhd +## | t_mux2to1.vhd +## | de1_mux2to1_structure.vhd +## | +## +---sim +## | | makefile +## | | +## | \---mux2to1 +## | makefile +## | makefile.sources +## | +## +---pnr +## | | makefile +## | | +## | \---de1_mux2to1 +## | de1_mux2to1_pins.tcl +## | makefile +## | +## \---scripts +## de1_pin_assignments_minimumio.csv +## de1_pin_assignments_minimumio.tcl +## modelsim.ini +## quartus_project_settings.tcl +## ---------------------------------------------------------------------------- + diff --git a/sim/resolver/makefile.sources b/sim/resolver/makefile.sources new file mode 100644 index 0000000..272943f --- /dev/null +++ b/sim/resolver/makefile.sources @@ -0,0 +1,21 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/rising_edge_detector_qfsm.vhd \ +../../src/falling_edge_detector_qfsm.vhd \ +../../src/resolver_master_qfsm.vhd \ +../../src/synchroniser_rtl.vhd \ +../../src/resolver_structure.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- |