diff options
Diffstat (limited to 'sim')
31 files changed, 1053 insertions, 0 deletions
diff --git a/sim/and2gate/makefile b/sim/and2gate/makefile new file mode 100644 index 0000000..e523dc3 --- /dev/null +++ b/sim/and2gate/makefile @@ -0,0 +1,67 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with ModelSim, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# assign variable PROJECT with the top level project name +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of testbench t_$(PROJECT).vhd +################################################################### + +PROJECT = and2gate + +include ./makefile.sources + +# Add here the testbench file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/t_$(PROJECT).vhd + +include ../makefile + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## DigitaltechnikPraktikum +## | +## +---src +## | and2gate_equation.vhd +## | invgate_equation.vhd +## | mux2to1_structure.vhd +## | or2gate_equation.vhd +## | t_mux2to1.vhd +## | de1_mux2to1_structure.vhd +## | +## +---sim +## | | makefile +## | | +## | \---mux2to1 +## | makefile +## | makefile.sources +## | +## +---pnr +## | | makefile +## | | +## | \---de1_mux2to1 +## | de1_mux2to1_pins.tcl +## | makefile +## | +## \---scripts +## de1_pin_assignments_minimumio.csv +## de1_pin_assignments_minimumio.tcl +## modelsim.ini +## quartus_project_settings.tcl +## ---------------------------------------------------------------------------- + diff --git a/sim/and2gate/makefile.sources b/sim/and2gate/makefile.sources new file mode 100644 index 0000000..cac390c --- /dev/null +++ b/sim/and2gate/makefile.sources @@ -0,0 +1,17 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/and2gate_equation.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/cntdn/makefile b/sim/cntdn/makefile new file mode 100644 index 0000000..1be2176 --- /dev/null +++ b/sim/cntdn/makefile @@ -0,0 +1,67 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with ModelSim, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# assign variable PROJECT with the top level project name +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of testbench t_$(PROJECT).vhd +################################################################### + +PROJECT = cntdn + +include ./makefile.sources + +# Add here the testbench file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/t_$(PROJECT).vhd + +include ../makefile + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## DigitaltechnikPraktikum +## | +## +---src +## | and2gate_equation.vhd +## | invgate_equation.vhd +## | mux2to1_structure.vhd +## | or2gate_equation.vhd +## | t_mux2to1.vhd +## | de1_mux2to1_structure.vhd +## | +## +---sim +## | | makefile +## | | +## | \---mux2to1 +## | makefile +## | makefile.sources +## | +## +---pnr +## | | makefile +## | | +## | \---de1_mux2to1 +## | de1_mux2to1_pins.tcl +## | makefile +## | +## \---scripts +## de1_pin_assignments_minimumio.csv +## de1_pin_assignments_minimumio.tcl +## modelsim.ini +## quartus_project_settings.tcl +## ---------------------------------------------------------------------------- + diff --git a/sim/cntdn/makefile.sources b/sim/cntdn/makefile.sources new file mode 100644 index 0000000..af4874d --- /dev/null +++ b/sim/cntdn/makefile.sources @@ -0,0 +1,17 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/cntdn_rtl.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/cntdnmodm/makefile b/sim/cntdnmodm/makefile new file mode 100644 index 0000000..060a0ad --- /dev/null +++ b/sim/cntdnmodm/makefile @@ -0,0 +1,67 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with ModelSim, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# assign variable PROJECT with the top level project name +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of testbench t_$(PROJECT).vhd +################################################################### + +PROJECT = cntdnmodm + +include ./makefile.sources + +# Add here the testbench file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/t_$(PROJECT).vhd + +include ../makefile + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## DigitaltechnikPraktikum +## | +## +---src +## | and2gate_equation.vhd +## | invgate_equation.vhd +## | mux2to1_structure.vhd +## | or2gate_equation.vhd +## | t_mux2to1.vhd +## | de1_mux2to1_structure.vhd +## | +## +---sim +## | | makefile +## | | +## | \---mux2to1 +## | makefile +## | makefile.sources +## | +## +---pnr +## | | makefile +## | | +## | \---de1_mux2to1 +## | de1_mux2to1_pins.tcl +## | makefile +## | +## \---scripts +## de1_pin_assignments_minimumio.csv +## de1_pin_assignments_minimumio.tcl +## modelsim.ini +## quartus_project_settings.tcl +## ---------------------------------------------------------------------------- + diff --git a/sim/cntdnmodm/makefile.sources b/sim/cntdnmodm/makefile.sources new file mode 100644 index 0000000..4752d19 --- /dev/null +++ b/sim/cntdnmodm/makefile.sources @@ -0,0 +1,17 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/cntdnmodm_rtl.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/de1_audio/makefile b/sim/de1_audio/makefile new file mode 100644 index 0000000..99b022e --- /dev/null +++ b/sim/de1_audio/makefile @@ -0,0 +1,10 @@ +PROJECT = de1_audio + +include ./makefile.sources + +# Add here the testbench file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/t_$(PROJECT).vhd + +include ../makefile + diff --git a/sim/de1_audio/makefile.sources b/sim/de1_audio/makefile.sources new file mode 100644 index 0000000..ee901cc --- /dev/null +++ b/sim/de1_audio/makefile.sources @@ -0,0 +1,14 @@ +SYN_SOURCE_FILES = \ +../../src/adcintf.vhd \ +../../src/bclk.vhd \ +../../src/dacintf.vhd \ +../../src/fsgen.vhd \ +../../src/i2c_sub.vhd \ +../../src/i2c.vhd \ +../../src/i2c_write.vhd \ +../../src/mclk.vhd \ +../../src/memory.vhd \ +../../src/ringbuf.vhd \ +../../src/audio.vhd \ +../../src/de1_audio.vhd + diff --git a/sim/de1_tone/makefile b/sim/de1_tone/makefile new file mode 100644 index 0000000..7eb97d3 --- /dev/null +++ b/sim/de1_tone/makefile @@ -0,0 +1,9 @@ +PROJECT = de1_tone + +include ./makefile.sources + +# Add here the testbench file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/t_$(PROJECT).vhd + +include ../makefile diff --git a/sim/de1_tone/makefile.sources b/sim/de1_tone/makefile.sources new file mode 100644 index 0000000..46993a5 --- /dev/null +++ b/sim/de1_tone/makefile.sources @@ -0,0 +1,13 @@ +SYN_SOURCE_FILES = \ +../../src/adcintf.vhd \ +../../src/bclk.vhd \ +../../src/dacintf.vhd \ +../../src/fsgen.vhd \ +../../src/i2c_sub.vhd \ +../../src/i2c.vhd \ +../../src/i2c_write.vhd \ +../../src/mclk.vhd \ +../../src/audio.vhd \ +../../src/tone_rtl.vhd \ +../../src/de1_tone.vhd + diff --git a/sim/falling_edge_detector/makefile b/sim/falling_edge_detector/makefile new file mode 100644 index 0000000..48792e4 --- /dev/null +++ b/sim/falling_edge_detector/makefile @@ -0,0 +1,67 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with ModelSim, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# assign variable PROJECT with the top level project name +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of testbench t_$(PROJECT).vhd +################################################################### + +PROJECT = falling_edge_detector + +include ./makefile.sources + +# Add here the testbench file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/t_$(PROJECT).vhd + +include ../makefile + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## DigitaltechnikPraktikum +## | +## +---src +## | and2gate_equation.vhd +## | invgate_equation.vhd +## | mux2to1_structure.vhd +## | or2gate_equation.vhd +## | t_mux2to1.vhd +## | de1_mux2to1_structure.vhd +## | +## +---sim +## | | makefile +## | | +## | \---mux2to1 +## | makefile +## | makefile.sources +## | +## +---pnr +## | | makefile +## | | +## | \---de1_mux2to1 +## | de1_mux2to1_pins.tcl +## | makefile +## | +## \---scripts +## de1_pin_assignments_minimumio.csv +## de1_pin_assignments_minimumio.tcl +## modelsim.ini +## quartus_project_settings.tcl +## ---------------------------------------------------------------------------- + diff --git a/sim/falling_edge_detector/makefile.sources b/sim/falling_edge_detector/makefile.sources new file mode 100644 index 0000000..03b2cd7 --- /dev/null +++ b/sim/falling_edge_detector/makefile.sources @@ -0,0 +1,18 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/e_falling_edge_detector.vhd \ +../../src/a_falling_edge_detector_rtl.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/falling_edge_detector/makefile_qfsm.sources b/sim/falling_edge_detector/makefile_qfsm.sources new file mode 100644 index 0000000..5b3eeec --- /dev/null +++ b/sim/falling_edge_detector/makefile_qfsm.sources @@ -0,0 +1,17 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/falling_edge_detector_qfsm.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/falling_edge_detector/makefile_rtl.sources b/sim/falling_edge_detector/makefile_rtl.sources new file mode 100644 index 0000000..03b2cd7 --- /dev/null +++ b/sim/falling_edge_detector/makefile_rtl.sources @@ -0,0 +1,18 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/e_falling_edge_detector.vhd \ +../../src/a_falling_edge_detector_rtl.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/falling_edge_detector/makefile_structure.sources b/sim/falling_edge_detector/makefile_structure.sources new file mode 100644 index 0000000..f644c26 --- /dev/null +++ b/sim/falling_edge_detector/makefile_structure.sources @@ -0,0 +1,19 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/d_ff_rtl.vhd \ +../../src/e_falling_edge_detector.vhd \ +../../src/a_falling_edge_detector_structure.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/incrementer/makefile b/sim/incrementer/makefile new file mode 100644 index 0000000..54e7a63 --- /dev/null +++ b/sim/incrementer/makefile @@ -0,0 +1,67 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with ModelSim, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# assign variable PROJECT with the top level project name +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of testbench t_$(PROJECT).vhd +################################################################### + +PROJECT = incrementer + +include ./makefile.sources + +# Add here the testbench file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/t_$(PROJECT).vhd + +include ../makefile + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## DigitaltechnikPraktikum +## | +## +---src +## | and2gate_equation.vhd +## | invgate_equation.vhd +## | mux2to1_structure.vhd +## | or2gate_equation.vhd +## | t_mux2to1.vhd +## | de1_mux2to1_structure.vhd +## | +## +---sim +## | | makefile +## | | +## | \---mux2to1 +## | makefile +## | makefile.sources +## | +## +---pnr +## | | makefile +## | | +## | \---de1_mux2to1 +## | de1_mux2to1_pins.tcl +## | makefile +## | +## \---scripts +## de1_pin_assignments_minimumio.csv +## de1_pin_assignments_minimumio.tcl +## modelsim.ini +## quartus_project_settings.tcl +## ---------------------------------------------------------------------------- + diff --git a/sim/incrementer/makefile.sources b/sim/incrementer/makefile.sources new file mode 100644 index 0000000..8766f99 --- /dev/null +++ b/sim/incrementer/makefile.sources @@ -0,0 +1,23 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/rising_edge_detector_qfsm.vhd \ +../../src/falling_edge_detector_qfsm.vhd \ +../../src/resolver_master_qfsm.vhd \ +../../src/resolver_structure.vhd \ +../../src/synchroniser_rtl.vhd \ +../../src/cntupdn_rtl.vhd \ +../../src/incrementer_structure.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/makefile b/sim/makefile new file mode 100644 index 0000000..6e7bd40 --- /dev/null +++ b/sim/makefile @@ -0,0 +1,87 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author(s) : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with ModelSim, +## it is based on a design directory structure shown at +## the end of this file. +## ---------------------------------------------------------------------------- + +################################################################### +# Main Targets +# +################################################################### + +help: + @echo '"make" does intentionally nothing. Type:' + @echo ' "make mproject" to create a new modelsim project only' + @echo ' "make compile" to compile all VHDL sources in batch mode' + @echo ' "make modelsim" to start modelsim with graphical user interface' + @echo ' "make sim" to start modelsim gui with the top testbench of the project' + @echo ' "make clean" to remove all generated files' + +mproject : mproject_created + +mproject_created : $(SOURCE_FILES) + # create modelsim project + rm -rf ./modelsim_sources.tcl + for source_file in $(SOURCE_FILES); do \ + echo project addfile $$source_file >> modelsim_sources.tcl; \ + done + vsim -modelsimini ../../scripts/modelsim.ini -c -do "project new [pwd] $(PROJECT); source ./modelsim_sources.tcl; quit -f" + touch mproject_created + +compile: ./work/_vmake + +./work/_vmake: mproject_created + vsim -c -do "project open $(PROJECT); project calculateorder; quit -f" + grep Error transcript; if [ $$? -eq 0 ] ; then rm -rf work/_vmake; exit 1; fi + + +modelsim: mproject_created + vsim -i -do "project open $(PROJECT)" & + +sim: ./work/_vmake + vsim -i -do "project open $(PROJECT); vsim work.t_$(PROJECT)(tbench); add wave *; run -a;" & + +clean: + rm -rf *.mpf *.mti *.ini *.wlf wlf* transcript work modelsim_sources.tcl mproject_created + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## DigitaltechnikPraktikum +## | +## +---src +## | and2gate_equation.vhd +## | invgate_equation.vhd +## | mux2to1_structure.vhd +## | or2gate_equation.vhd +## | t_mux2to1.vhd +## | de1_mux2to1_structure.vhd +## | +## +---sim +## | | makefile +## | | +## | \---mux2to1 +## | makefile +## | makefile.sources +## | +## +---pnr +## | | makefile +## | | +## | \---de1_mux2to1 +## | de1_mux2to1_pins.tcl +## | makefile +## | +## \---scripts +## de1_pin_assignments_minimumio.csv +## de1_pin_assignments_minimumio.tcl +## modelsim.ini +## quartus_project_settings.tcl +## ---------------------------------------------------------------------------- + diff --git a/sim/mux2to1/makefile b/sim/mux2to1/makefile new file mode 100644 index 0000000..c655d61 --- /dev/null +++ b/sim/mux2to1/makefile @@ -0,0 +1,67 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with ModelSim, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# assign variable PROJECT with the top level project name +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of testbench t_$(PROJECT).vhd +################################################################### + +PROJECT = mux2to1 + +include ./makefile.sources + +# Add here the testbench file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/t_$(PROJECT).vhd + +include ../makefile + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## DigitaltechnikPraktikum +## | +## +---src +## | and2gate_equation.vhd +## | invgate_equation.vhd +## | mux2to1_structure.vhd +## | or2gate_equation.vhd +## | t_mux2to1.vhd +## | de1_mux2to1_structure.vhd +## | +## +---sim +## | | makefile +## | | +## | \---mux2to1 +## | makefile +## | makefile.sources +## | +## +---pnr +## | | makefile +## | | +## | \---de1_mux2to1 +## | de1_mux2to1_pins.tcl +## | makefile +## | +## \---scripts +## de1_pin_assignments_minimumio.csv +## de1_pin_assignments_minimumio.tcl +## modelsim.ini +## quartus_project_settings.tcl +## ---------------------------------------------------------------------------- + diff --git a/sim/mux2to1/makefile.sources b/sim/mux2to1/makefile.sources new file mode 100644 index 0000000..880fac4 --- /dev/null +++ b/sim/mux2to1/makefile.sources @@ -0,0 +1,17 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/mux2to1_equation.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/mux2to1/makefile_equation.sources b/sim/mux2to1/makefile_equation.sources new file mode 100644 index 0000000..880fac4 --- /dev/null +++ b/sim/mux2to1/makefile_equation.sources @@ -0,0 +1,17 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/mux2to1_equation.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/mux2to1/makefile_rtl.sources b/sim/mux2to1/makefile_rtl.sources new file mode 100644 index 0000000..7dd9c7d --- /dev/null +++ b/sim/mux2to1/makefile_rtl.sources @@ -0,0 +1,17 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/mux2to1_rtl.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/mux2to1/makefile_structure.sources b/sim/mux2to1/makefile_structure.sources new file mode 100644 index 0000000..f797190 --- /dev/null +++ b/sim/mux2to1/makefile_structure.sources @@ -0,0 +1,20 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/and2gate_equation.vhd \ +../../src/or2gate_equation.vhd \ +../../src/invgate_equation.vhd \ +../../src/mux2to1_structure.vhd \ + +# do not delete this line +# -----------------------------------------------------------------------------
\ No newline at end of file diff --git a/sim/mux2to1/makefile_structure_errors.sources b/sim/mux2to1/makefile_structure_errors.sources new file mode 100644 index 0000000..c412baf --- /dev/null +++ b/sim/mux2to1/makefile_structure_errors.sources @@ -0,0 +1,20 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/and2gate_equation.vhd \ +../../src/or2gate_equation.vhd \ +../../src/invgate_equation.vhd \ +../../src/mux2to1_structure_errors.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/mux2to1/makefile_truthtable.sources b/sim/mux2to1/makefile_truthtable.sources new file mode 100644 index 0000000..e815b55 --- /dev/null +++ b/sim/mux2to1/makefile_truthtable.sources @@ -0,0 +1,17 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/mux2to1_truthtable.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/pwm/makefile b/sim/pwm/makefile new file mode 100644 index 0000000..962c45a --- /dev/null +++ b/sim/pwm/makefile @@ -0,0 +1,67 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with ModelSim, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# assign variable PROJECT with the top level project name +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of testbench t_$(PROJECT).vhd +################################################################### + +PROJECT = pwm + +include ./makefile.sources + +# Add here the testbench file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/t_$(PROJECT).vhd + +include ../makefile + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## DigitaltechnikPraktikum +## | +## +---src +## | and2gate_equation.vhd +## | invgate_equation.vhd +## | mux2to1_structure.vhd +## | or2gate_equation.vhd +## | t_mux2to1.vhd +## | de1_mux2to1_structure.vhd +## | +## +---sim +## | | makefile +## | | +## | \---mux2to1 +## | makefile +## | makefile.sources +## | +## +---pnr +## | | makefile +## | | +## | \---de1_mux2to1 +## | de1_mux2to1_pins.tcl +## | makefile +## | +## \---scripts +## de1_pin_assignments_minimumio.csv +## de1_pin_assignments_minimumio.tcl +## modelsim.ini +## quartus_project_settings.tcl +## ---------------------------------------------------------------------------- + diff --git a/sim/pwm/makefile.sources b/sim/pwm/makefile.sources new file mode 100644 index 0000000..5db2028 --- /dev/null +++ b/sim/pwm/makefile.sources @@ -0,0 +1,17 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/pwm_rtl.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/pwm_incrementer/makefile b/sim/pwm_incrementer/makefile new file mode 100644 index 0000000..54e7a63 --- /dev/null +++ b/sim/pwm_incrementer/makefile @@ -0,0 +1,67 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with ModelSim, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# assign variable PROJECT with the top level project name +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of testbench t_$(PROJECT).vhd +################################################################### + +PROJECT = incrementer + +include ./makefile.sources + +# Add here the testbench file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/t_$(PROJECT).vhd + +include ../makefile + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## DigitaltechnikPraktikum +## | +## +---src +## | and2gate_equation.vhd +## | invgate_equation.vhd +## | mux2to1_structure.vhd +## | or2gate_equation.vhd +## | t_mux2to1.vhd +## | de1_mux2to1_structure.vhd +## | +## +---sim +## | | makefile +## | | +## | \---mux2to1 +## | makefile +## | makefile.sources +## | +## +---pnr +## | | makefile +## | | +## | \---de1_mux2to1 +## | de1_mux2to1_pins.tcl +## | makefile +## | +## \---scripts +## de1_pin_assignments_minimumio.csv +## de1_pin_assignments_minimumio.tcl +## modelsim.ini +## quartus_project_settings.tcl +## ---------------------------------------------------------------------------- + diff --git a/sim/pwm_incrementer/makefile.sources b/sim/pwm_incrementer/makefile.sources new file mode 100644 index 0000000..687a731 --- /dev/null +++ b/sim/pwm_incrementer/makefile.sources @@ -0,0 +1,24 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/rising_edge_detector_qfsm.vhd \ +../../src/falling_edge_detector_qfsm.vhd \ +../../src/resolver_master_qfsm.vhd \ +../../src/resolver_structure.vhd \ +../../src/synchroniser_rtl.vhd \ +../../src/cntupdn_rtl.vhd \ +../../src/incrementer_structure.vhd \ +../../src/pwm_rtl.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/resolver/makefile b/sim/resolver/makefile new file mode 100644 index 0000000..ac0a168 --- /dev/null +++ b/sim/resolver/makefile @@ -0,0 +1,68 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with ModelSim, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# assign variable PROJECT with the top level project name +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of testbench t_$(PROJECT).vhd +################################################################### + +PROJECT = resolver + +include ./makefile.sources + +# Add here the testbench file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/cntupdn_rtl.vhd \ +../../src/t_$(PROJECT).vhd + +include ../makefile + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## DigitaltechnikPraktikum +## | +## +---src +## | and2gate_equation.vhd +## | invgate_equation.vhd +## | mux2to1_structure.vhd +## | or2gate_equation.vhd +## | t_mux2to1.vhd +## | de1_mux2to1_structure.vhd +## | +## +---sim +## | | makefile +## | | +## | \---mux2to1 +## | makefile +## | makefile.sources +## | +## +---pnr +## | | makefile +## | | +## | \---de1_mux2to1 +## | de1_mux2to1_pins.tcl +## | makefile +## | +## \---scripts +## de1_pin_assignments_minimumio.csv +## de1_pin_assignments_minimumio.tcl +## modelsim.ini +## quartus_project_settings.tcl +## ---------------------------------------------------------------------------- + diff --git a/sim/resolver/makefile.sources b/sim/resolver/makefile.sources new file mode 100644 index 0000000..272943f --- /dev/null +++ b/sim/resolver/makefile.sources @@ -0,0 +1,21 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/rising_edge_detector_qfsm.vhd \ +../../src/falling_edge_detector_qfsm.vhd \ +../../src/resolver_master_qfsm.vhd \ +../../src/synchroniser_rtl.vhd \ +../../src/resolver_structure.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- |