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-rw-r--r--src/fir_mac_rtl.vhd47
-rw-r--r--src/fir_structure.vhd124
-rw-r--r--src/t_fir_fileio.vhd111
3 files changed, 282 insertions, 0 deletions
diff --git a/src/fir_mac_rtl.vhd b/src/fir_mac_rtl.vhd
new file mode 100644
index 0000000..866fa50
--- /dev/null
+++ b/src/fir_mac_rtl.vhd
@@ -0,0 +1,47 @@
+-------------------------------------------------------------------------------
+-- Module : fir_mac
+-------------------------------------------------------------------------------
+-- Author : Matthias Kamuf
+-- Company : University of Applied Sciences Augsburg
+-------------------------------------------------------------------------------
+-- Description: Module fir_mac used as part of fir
+--
+-------------------------------------------------------------------------------
+-- Revisions : see end of file
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+
+ENTITY fir_mac IS
+ GENERIC (
+ gen_w_in : natural := 14;
+ gen_w_c : natural := 12);
+ PORT (
+ clk_i : IN std_ulogic;
+ rst_ni : IN std_ulogic;
+ hl_i : IN std_ulogic_vector(gen_w_c-1 DOWNTO 0); -- left coefficient
+ hr_i : IN std_ulogic_vector(gen_w_c-1 DOWNTO 0); -- right coefficient
+ d_i : IN std_ulogic_vector(gen_w_in-1 DOWNTO 0); -- data input first register
+ d_o : OUT std_ulogic_vector(gen_w_in-1 DOWNTO 0); -- data output second register
+ sum_o : OUT std_ulogic_vector(gen_w_in+gen_w_c DOWNTO 0)); -- registered output sum_o
+END fir_mac;
+
+ARCHITECTURE rtl OF fir_mac IS
+
+
+BEGIN
+
+ -- shift register at sample rate
+
+ -- products left and right of first register
+
+ -- output sum (registered) at sample rate
+
+END rtl;
+
+-------------------------------------------------------------------------------
+-- Revisions:
+-- ----------
+-- $Id:$
+-------------------------------------------------------------------------------
diff --git a/src/fir_structure.vhd b/src/fir_structure.vhd
new file mode 100644
index 0000000..88364e5
--- /dev/null
+++ b/src/fir_structure.vhd
@@ -0,0 +1,124 @@
+-------------------------------------------------------------------------------
+-- Module : fir
+-------------------------------------------------------------------------------
+-- Author : Matthias Kamuf
+-- Company : University of Applied Sciences Augsburg
+-------------------------------------------------------------------------------
+-- Description: Top-level of module fir
+--
+-------------------------------------------------------------------------------
+-- Revisions : see end of file
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+
+ENTITY fir IS
+ PORT (
+ clk_i : IN std_ulogic;
+ rst_ni : IN std_ulogic;
+ valid_i : IN std_ulogic;
+ sample_i : IN std_ulogic_vector(13 DOWNTO 0);
+ valid_o : OUT std_ulogic;
+ sample_o : OUT std_ulogic_vector(13 DOWNTO 0));
+END fir;
+
+ARCHITECTURE structure OF fir IS
+
+ -- coefficient wordlength
+ CONSTANT W_C : natural := 12;
+
+ -- type definition for coefficients
+ TYPE COEFFS_TYPE IS ARRAY (0 TO 7) OF integer;
+
+ -- HERE SHALL BE THE CONTENT OF hqi.txt --->
+
+ -- <---
+
+ COMPONENT fir_mac IS
+ GENERIC (
+ gen_w_in : natural := 14;
+ gen_w_c : natural := 12);
+ PORT (
+ clk_i : IN std_ulogic;
+ rst_ni : IN std_ulogic;
+ hl_i : IN std_ulogic_vector(gen_w_c-1 DOWNTO 0); -- left coefficient
+ hr_i : IN std_ulogic_vector(gen_w_c-1 DOWNTO 0); -- right coefficient
+ d_i : IN std_ulogic_vector(gen_w_in-1 DOWNTO 0); -- data input first register
+ d_o : OUT std_ulogic_vector(gen_w_in-1 DOWNTO 0); -- data output second register
+ sum_o : OUT std_ulogic_vector(gen_w_in+gen_w_c DOWNTO 0)); -- registered output sum_o
+ END COMPONENT fir_mac;
+
+ -- dynamic range of sum given coefficients above
+ CONSTANT W_DYN : natural := 1;
+
+BEGIN
+
+ -- component instantiation
+ mac0 : fir_mac
+ GENERIC MAP (
+ gen_w_in => sample_i'length,
+ gen_w_c => W_C)
+ PORT MAP (
+ clk_i => clk_i,
+ rst_ni => rst_ni,
+ hl_i => ,
+ hr_i => ,
+ d_i => ,
+ d_o => ,
+ sum_o => );
+
+ mac1 : fir_mac
+ GENERIC MAP (
+ gen_w_in => sample_i'length,
+ gen_w_c => W_C)
+ PORT MAP (
+ clk_i => clk_i,
+ rst_ni => rst_ni,
+ hl_i => ,
+ hr_i => ,
+ d_i => ,
+ d_o => ,
+ sum_o => );
+
+ mac2 : fir_mac
+ GENERIC MAP (
+ gen_w_in => sample_i'length,
+ gen_w_c => W_C)
+ PORT MAP (
+ clk_i => clk_i,
+ rst_ni => rst_ni,
+ hl_i => ,
+ hr_i => ,
+ d_i => ,
+ d_o => ,
+ sum_o => );
+
+ mac3 : fir_mac
+ GENERIC MAP (
+ gen_w_in => sample_i'length,
+ gen_w_c => W_C)
+ PORT MAP (
+ clk_i => clk_i,
+ rst_ni => rst_ni,
+ hl_i => ,
+ hr_i => ,
+ d_i => ,
+ d_o => ,
+ sum_o => );
+
+ -- combining sums of individual fir_mac
+
+ -- final sum
+
+ -- truncated final sum (registered) at sample rate
+
+ -- (registered and delayed due to pipeline stage in fir_mac) valid signal at sample rate
+
+END structure;
+
+-------------------------------------------------------------------------------
+-- Revisions:
+-- ----------
+-- $Id:$
+-------------------------------------------------------------------------------
diff --git a/src/t_fir_fileio.vhd b/src/t_fir_fileio.vhd
new file mode 100644
index 0000000..3fd8363
--- /dev/null
+++ b/src/t_fir_fileio.vhd
@@ -0,0 +1,111 @@
+-------------------------------------------------------------------------------
+-- Module : t_fir_fileio
+-------------------------------------------------------------------------------
+-- Author : Matthias Kamuf
+-- Company : University of Applied Sciences Augsburg
+-------------------------------------------------------------------------------
+-- Description: Testbench for module fir
+--
+------------------------------------------------------------------------------
+-- Revisions : see end of file
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE STD.textio.ALL;
+
+ENTITY t_fir IS
+
+END t_fir;
+
+ARCHITECTURE tbench OF t_fir IS
+
+ COMPONENT fir IS
+ PORT (
+ clk_i : IN std_ulogic;
+ rst_ni : IN std_ulogic;
+ valid_i : IN std_ulogic;
+ sample_i : IN std_ulogic_vector(13 DOWNTO 0);
+ valid_o : OUT std_ulogic;
+ sample_o : OUT std_ulogic_vector(13 DOWNTO 0));
+ END COMPONENT fir;
+
+ -- component ports
+ SIGNAL clk : std_ulogic;
+ SIGNAL rst_n : std_ulogic;
+ SIGNAL valid_in : std_ulogic;
+ SIGNAL sample_in : std_ulogic_vector(13 DOWNTO 0);
+ SIGNAL valid_out : std_ulogic;
+ SIGNAL sample_out : std_ulogic_vector(13 DOWNTO 0);
+
+ -- definition of a clock period
+ CONSTANT period : time := 20 ns;
+ -- switch for clock generator
+ SIGNAL clken_p : boolean := true;
+
+BEGIN
+
+ -- component instantiation
+ DUT : fir
+ PORT MAP (
+ clk_i => clk,
+ rst_ni => rst_n,
+ valid_i => valid_in,
+ sample_i => sample_in,
+ valid_o => valid_out,
+ sample_o => sample_out);
+
+ -- clock generation
+ clock_proc : PROCESS
+ BEGIN
+ WHILE clken_p LOOP
+ clk <= '0'; WAIT FOR period/2;
+ clk <= '1'; WAIT FOR period/2;
+ END LOOP;
+ WAIT;
+ END PROCESS;
+
+ reset : rst_n <= '0', '1' AFTER period;
+
+ stimuli_observer : PROCESS
+ VARIABLE Li : line; -- pointer to file input buffer
+ VARIABLE Vi : integer;
+ FILE stimulifile : text OPEN read_mode IS "stimuli/fir_stimuli.dat";
+
+ VARIABLE Lo : line; -- pointer to file output buffer
+ VARIABLE Vo : integer;
+ FILE resultfile : text OPEN write_mode IS "log/fir_result.dat";
+
+ BEGIN
+
+ valid_in <= '1';
+ sample_in <= (OTHERS => '0');
+
+ WAIT UNTIL rst_n = '1'; -- wait for reset
+
+ WHILE (NOT endfile(stimulifile)) LOOP
+ IF valid_in = '1' THEN
+ readline(stimulifile, Li);
+ read(Li, Vi);
+ sample_in <= std_ulogic_vector(to_signed(Vi, sample_in'length));
+ END IF;
+ IF valid_out = '1' THEN
+ Vo := to_integer(signed(sample_out));
+ write(Lo, Vo);
+ writeline(resultfile, Lo);
+ END IF;
+ WAIT UNTIL clk = '1';
+ END LOOP;
+
+ clken_p <= false; -- switch off clock generator
+
+ WAIT;
+ END PROCESS;
+END tbench;
+
+
+-------------------------------------------------------------------------------
+-- Revisions:
+-- ----------
+-- $Id:$
+-------------------------------------------------------------------------------
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