From 941aeaad5be56c905b4f38f3d07b0a0cbc1bd07f Mon Sep 17 00:00:00 2001 From: Matthias Kamuf Date: Wed, 15 Jun 2022 17:31:01 +0200 Subject: Created stub for DDS test with ADDA-board using Simulink flow --- matlab/dds_adda/makefile | 4 + .../de1_matlab_dds_adda_pins.tcl | 62 ++++++++++++ pnr/de1_matlab_dds_adda/makefile | 18 ++++ src/de1_matlab_dds_adda.vhd | 104 +++++++++++++++++++++ 4 files changed, 188 insertions(+) create mode 100644 matlab/dds_adda/makefile create mode 100755 pnr/de1_matlab_dds_adda/de1_matlab_dds_adda_pins.tcl create mode 100644 pnr/de1_matlab_dds_adda/makefile create mode 100644 src/de1_matlab_dds_adda.vhd diff --git a/matlab/dds_adda/makefile b/matlab/dds_adda/makefile new file mode 100644 index 0000000..8cf1d6d --- /dev/null +++ b/matlab/dds_adda/makefile @@ -0,0 +1,4 @@ +PROJECT=dds_adda_first +TOPLEVEL=$(PROJECT)/ml_dds_adda + +include ../makefile diff --git a/pnr/de1_matlab_dds_adda/de1_matlab_dds_adda_pins.tcl b/pnr/de1_matlab_dds_adda/de1_matlab_dds_adda_pins.tcl new file mode 100755 index 0000000..0bbae36 --- /dev/null +++ b/pnr/de1_matlab_dds_adda/de1_matlab_dds_adda_pins.tcl @@ -0,0 +1,62 @@ +# Pin Configuration +set_location_assignment PIN_L1 -to CLOCK_50 +set_location_assignment PIN_R22 -to KEY0 +# set_location_assignment PIN_L22 -to SW[0] +# set_location_assignment PIN_L21 -to SW[1] +# set_location_assignment PIN_M22 -to SW[2] +# set_location_assignment PIN_V12 -to SW[3] +# set_location_assignment PIN_W12 -to SW[4] +# set_location_assignment PIN_U12 -to SW[5] +# set_location_assignment PIN_U11 -to SW[6] +# set_location_assignment PIN_M2 -to SW[7] +# set_location_assignment PIN_M1 -to SW[8] +# set_location_assignment PIN_L2 -to SW[9] +set_location_assignment PIN_R20 -to LEDR +#set_location_assignment PIN_R19 -to LEDR[1] +#set_location_assignment PIN_U19 -to LEDR[2] +#set_location_assignment PIN_Y19 -to LEDR[3] +#set_location_assignment PIN_T18 -to LEDR[4] +#set_location_assignment PIN_V19 -to LEDR[5] +#set_location_assignment PIN_Y18 -to LEDR[6] +#set_location_assignment PIN_U18 -to LEDR[7] +#set_location_assignment PIN_R18 -to LEDR[8] +#set_location_assignment PIN_R17 -to LEDR[9] +# DAC Pins on GPIO Header +set_location_assignment PIN_C19 -to DAC_CLK_A +set_location_assignment PIN_D19 -to DAC_CLK_B +set_location_assignment PIN_C18 -to DAC_DA[0] +set_location_assignment PIN_F15 -to DAC_DA[10] +set_location_assignment PIN_E14 -to DAC_DA[11] +set_location_assignment PIN_G15 -to DAC_DA[12] +set_location_assignment PIN_H13 -to DAC_DA[13] +set_location_assignment PIN_D16 -to DAC_DA[1] +set_location_assignment PIN_C17 -to DAC_DA[2] +set_location_assignment PIN_D15 -to DAC_DA[3] +set_location_assignment PIN_D14 -to DAC_DA[4] +set_location_assignment PIN_F13 -to DAC_DA[5] +set_location_assignment PIN_C14 -to DAC_DA[6] +set_location_assignment PIN_F12 -to DAC_DA[7] +set_location_assignment PIN_G16 -to DAC_DA[8] +set_location_assignment PIN_E15 -to DAC_DA[9] +set_location_assignment PIN_P15 -to DAC_DB[0] +set_location_assignment PIN_G20 -to DAC_DB[10] +set_location_assignment PIN_E19 -to DAC_DB[11] +set_location_assignment PIN_F20 -to DAC_DB[12] +set_location_assignment PIN_D20 -to DAC_DB[13] +set_location_assignment PIN_N22 -to DAC_DB[1] +set_location_assignment PIN_N15 -to DAC_DB[2] +set_location_assignment PIN_N21 -to DAC_DB[3] +set_location_assignment PIN_J15 -to DAC_DB[4] +set_location_assignment PIN_G17 -to DAC_DB[5] +set_location_assignment PIN_H18 -to DAC_DB[6] +set_location_assignment PIN_H17 -to DAC_DB[7] +set_location_assignment PIN_G18 -to DAC_DB[8] +set_location_assignment PIN_E18 -to DAC_DB[9] +set_location_assignment PIN_P18 -to DAC_MODE +set_location_assignment PIN_C20 -to DAC_WRT_A +set_location_assignment PIN_P17 -to DAC_WRT_B +set_location_assignment PIN_C21 -to ADC_CLK_A +set_location_assignment PIN_D21 -to ADC_CLK_B +set_location_assignment PIN_L18 -to ADC_OEB_A +set_location_assignment PIN_K20 -to ADC_OEB_B +set_location_assignment PIN_J18 -to POWER_ON diff --git a/pnr/de1_matlab_dds_adda/makefile b/pnr/de1_matlab_dds_adda/makefile new file mode 100644 index 0000000..14cbe16 --- /dev/null +++ b/pnr/de1_matlab_dds_adda/makefile @@ -0,0 +1,18 @@ +MATLAB_DIR_NAME = dds_adda +MATLAB_PROJECT_NAME = dds_adda_first +PROJECT = de1_matlab_$(MATLAB_DIR_NAME) + +# Matlab produces a xxx_compile.do file which contains the vhdl files belonging to the project +# Here I produce a list of these source files with full relative path to the matlab project +SIMULINK_PATH=../../matlab/$(MATLAB_DIR_NAME)/hdl_prj/hdlsrc/$(MATLAB_PROJECT_NAME) +MATLAB_SOURCE_FILE_NAMES = $(shell grep vcom $(SIMULINK_PATH)/*_compile.do | sed "s/vcom \(.*\)/\1/g") +MATLAB_SOURCE_FILES = $(foreach file,$(MATLAB_SOURCE_FILE_NAMES),$(SIMULINK_PATH)/$(file)) + +SOURCE_FILES = \ +../../src/de1_matlab_dds_adda.vhd $(MATLAB_SOURCE_FILES) + +FAMILY = "Cyclone II" +DEVICE = EP2C20F484C7 +PROGFILEEXT = sof + +include ../makefile diff --git a/src/de1_matlab_dds_adda.vhd b/src/de1_matlab_dds_adda.vhd new file mode 100644 index 0000000..a6546f6 --- /dev/null +++ b/src/de1_matlab_dds_adda.vhd @@ -0,0 +1,104 @@ +------------------------------------------------------------------------------- +-- Module : de1_matlab_dds_adda +------------------------------------------------------------------------------- +-- Author : Matthias Kamuf +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: Top-level of module de1_matlab_dds_adda +-- +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY de1_matlab_dds_adda IS + PORT ( + CLOCK_50 : IN std_ulogic; + KEY0 : IN std_ulogic; + DAC_MODE : OUT std_ulogic; + DAC_WRT_A : OUT std_ulogic; + DAC_WRT_B : OUT std_ulogic; + DAC_CLK_A : OUT std_ulogic; + DAC_CLK_B : OUT std_ulogic; + DAC_DA : OUT std_ulogic_vector(13 DOWNTO 0); + DAC_DB : OUT std_ulogic_vector(13 DOWNTO 0); + POWER_ON : OUT std_ulogic; + ADC_CLK_A : OUT std_ulogic; + ADC_CLK_B : OUT std_ulogic; + ADC_OEB_A : OUT std_ulogic; + ADC_OEB_B : OUT std_ulogic; + LEDR : OUT std_ulogic); +END de1_matlab_dds_adda; + +ARCHITECTURE structure OF de1_matlab_dds_adda IS + + -- Matlab-generated toplevel + COMPONENT ml_dds_adda IS + PORT ( + clk : IN std_ulogic; + rst_n : IN std_ulogic; + valid_o : OUT std_ulogic; + sample_o : OUT std_ulogic_vector(13 DOWNTO 0)); + END COMPONENT ml_dds_adda; + + -- component ports + SIGNAL clk : std_ulogic; + SIGNAL rst_n : std_ulogic; + SIGNAL valid : std_ulogic; + SIGNAL sample : std_ulogic_vector(13 DOWNTO 0); + +BEGIN + + sinegen : ml_dds_adda + PORT MAP ( + clk_ => clk, + rst_n => rst_n, + valid_o => valid, + sample_o => sample); + + -- clock and reset signal + clk <= CLOCK_50; + rst_n <= KEY0; + + -- valid indicator + LEDR <= valid; + + -- DAC in dual-port mode + DAC_MODE <= '1'; + + DAC_WRT_A <= clk; + DAC_WRT_B <= clk; + DAC_CLK_A <= clk; + DAC_CLK_B <= clk; + + -- DAC on board has 00000000000000 as minimum value + -- and 11111111111111 as maximum value + -- therefore the conversion has to look like this + -- input signed value output DAC value + -- minimum 10000000000000 00000000000000 + -- zero 00000000000000 10000000000000 + -- maximum 01111111111111 11111111111111 + + -- assign to DAC channels + DAC_DA <= "10000000000000" WHEN rst_n = '0' ELSE (NOT(sample(13)) & sample(12 DOWNTO 0)) WHEN falling_edge(clk); + DAC_DB <= "10000000000000" WHEN rst_n = '0' ELSE "10000000000000" WHEN falling_edge(clk); + + -- ADC section all off! + ADC_CLK_A <= '0'; + ADC_CLK_B <= '0'; + ADC_OEB_A <= '0'; + ADC_OEB_B <= '0'; + + -- switch on DAC/ADC + POWER_ON <= '1'; + +END structure; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- + -- cgit v1.2.3