From a04bbf15b0f51696894e37f3e566998108aefd74 Mon Sep 17 00:00:00 2001 From: Johann Faerber Date: Wed, 9 Mar 2022 09:48:43 +0100 Subject: added basic design directory structure --- doc/datasheet.yaml | 26 + doc/images/uasa-logo.pdf | 2737 ++++++++++++++++++++ doc/makefile | 78 + doc/presentation.yaml | 11 + doc/pulse_width_modulator_datasheet.md | 206 ++ doc/pulse_width_modulator_presentation.md | 106 + doc/pulse_width_modulator_report.md | 235 ++ doc/report.yaml | 27 + doc/uasa_meng_vlsi_template.tex | 1038 ++++++++ doc/vec.conf | 243 ++ matlab/audio/audio_first.slx | Bin 0 -> 23427 bytes matlab/audio/audio_tone.slx | Bin 0 -> 26943 bytes matlab/audio/makefile | 4 + matlab/makefile | 15 + pnr/de1_and2gate/de1_and2gate_pins.tcl | 10 + pnr/de1_and2gate/makefile | 53 + pnr/de1_audio/de1_audio_pins.tcl | 23 + pnr/de1_audio/makefile | 16 + pnr/de1_binto7segment/de1_binto7segment_pins.tcl | 20 + pnr/de1_binto7segment/makefile | 53 + pnr/de1_cntdn/de1_cntdn_pins.tcl | 14 + pnr/de1_cntdn/makefile | 53 + pnr/de1_cntdnmodm/de1_cntdnmodm_pins.tcl | 16 + pnr/de1_cntdnmodm/makefile | 53 + pnr/de1_incrementer/de1_incrementer_pins.tcl | 25 + pnr/de1_incrementer/makefile | 55 + pnr/de1_mux2to1/de1_mux2to1_pins.tcl | 9 + pnr/de1_mux2to1/makefile | 87 + pnr/de1_pwm/de1_pwm_pins.tcl | 27 + pnr/de1_pwm/makefile | 87 + .../de1_pwm_incrementer_pins.tcl | 36 + pnr/de1_pwm_incrementer/makefile | 55 + pnr/de1_tone/de1_tone_pins.tcl | 33 + pnr/de1_tone/makefile | 14 + pnr/makefile | 92 + scripts/create_quartus_project_settings.tcl | 84 + scripts/de1_pin_assignments_minimumio.tcl | 282 ++ scripts/modelsim.ini | 351 +++ scripts/quartus_project_flow.tcl | 84 + sim/and2gate/makefile | 67 + sim/and2gate/makefile.sources | 17 + sim/cntdn/makefile | 67 + sim/cntdn/makefile.sources | 17 + sim/cntdnmodm/makefile | 67 + sim/cntdnmodm/makefile.sources | 17 + sim/de1_audio/makefile | 10 + sim/de1_audio/makefile.sources | 14 + sim/de1_tone/makefile | 9 + sim/de1_tone/makefile.sources | 13 + sim/falling_edge_detector/makefile | 67 + sim/falling_edge_detector/makefile.sources | 18 + sim/falling_edge_detector/makefile_qfsm.sources | 17 + sim/falling_edge_detector/makefile_rtl.sources | 18 + .../makefile_structure.sources | 19 + sim/incrementer/makefile | 67 + sim/incrementer/makefile.sources | 23 + sim/makefile | 87 + sim/mux2to1/makefile | 67 + sim/mux2to1/makefile.sources | 17 + sim/mux2to1/makefile_equation.sources | 17 + sim/mux2to1/makefile_rtl.sources | 17 + sim/mux2to1/makefile_structure.sources | 20 + sim/mux2to1/makefile_structure_errors.sources | 20 + sim/mux2to1/makefile_truthtable.sources | 17 + sim/pwm/makefile | 67 + sim/pwm/makefile.sources | 17 + sim/pwm_incrementer/makefile | 67 + sim/pwm_incrementer/makefile.sources | 24 + sim/resolver/makefile | 68 + sim/resolver/makefile.sources | 21 + src/a_falling_edge_detector_rtl.vhd | 42 + src/adcintf.vhd | 98 + src/and2gate_equation.vhd | 35 + src/audio.vhd | 156 ++ src/bclk.vhd | 79 + src/binto7segment_truthtable.vhd | 63 + src/cntdn_rtl.vhd | 47 + src/cntdnmodm_rtl.vhd | 54 + src/cntupdn_rtl.vhd | 47 + src/cntupen_rtl.vhd | 52 + src/d_ff_rtl.vhd | 39 + src/dacintf.vhd | 60 + src/de1_adc_rtl.vhd | 111 + src/de1_add1_structure.vhd | 51 + src/de1_add4_structure.vhd | 103 + src/de1_audio.vhd | 118 + src/de1_binto7segment_structure.vhd | 48 + src/de1_cntdn_structure.vhd | 78 + src/de1_cntdnmodm_structure.vhd | 111 + src/de1_dac_rtl.vhd | 109 + src/de1_matlab_audio.vhd | 126 + src/de1_mux2to1_structure.vhd | 48 + src/de1_sta.vhd | 32 + src/de1_tone.vhd | 119 + src/e_falling_edge_detector.vhd | 34 + src/fsgen.vhd | 56 + src/i2c.vhd | 245 ++ src/i2c_sub.vhd | 79 + src/i2c_write.vhd | 98 + src/invgate_equation.vhd | 34 + src/mclk.vhd | 48 + src/memory.vhd | 54 + src/mux2to1_equation.vhd | 40 + src/mux2to1_rtl.vhd | 42 + src/mux2to1_structure.vhd | 90 + src/mux2to1_structure_errors.vhd | 79 + src/mux2to1_truthtable.vhd | 54 + src/or2gate_equation.vhd | 18 + src/play_rtl.vhd | 101 + src/ringbuf.vhd | 74 + src/t_cntdn.vhd | 123 + src/t_cntdnmodm.vhd | 157 ++ src/t_de1_audio.vhd | 88 + src/t_de1_play.vhd | 100 + src/t_de1_tone.vhd | 108 + src/t_falling_edge_detector.vhd | 116 + src/t_mux2to1.vhd | 81 + src/tone_rtl.vhd | 19 + 118 files changed, 11175 insertions(+) create mode 100644 doc/datasheet.yaml create mode 100644 doc/images/uasa-logo.pdf create mode 100644 doc/makefile create mode 100644 doc/presentation.yaml create mode 100644 doc/pulse_width_modulator_datasheet.md create mode 100644 doc/pulse_width_modulator_presentation.md create mode 100644 doc/pulse_width_modulator_report.md create mode 100644 doc/report.yaml create mode 100644 doc/uasa_meng_vlsi_template.tex create mode 100644 doc/vec.conf create mode 100644 matlab/audio/audio_first.slx create mode 100644 matlab/audio/audio_tone.slx create mode 100644 matlab/audio/makefile create mode 100644 matlab/makefile create mode 100644 pnr/de1_and2gate/de1_and2gate_pins.tcl create mode 100644 pnr/de1_and2gate/makefile create mode 100644 pnr/de1_audio/de1_audio_pins.tcl create mode 100644 pnr/de1_audio/makefile create mode 100644 pnr/de1_binto7segment/de1_binto7segment_pins.tcl create mode 100644 pnr/de1_binto7segment/makefile create mode 100644 pnr/de1_cntdn/de1_cntdn_pins.tcl create mode 100644 pnr/de1_cntdn/makefile create mode 100644 pnr/de1_cntdnmodm/de1_cntdnmodm_pins.tcl create mode 100644 pnr/de1_cntdnmodm/makefile create mode 100644 pnr/de1_incrementer/de1_incrementer_pins.tcl create mode 100644 pnr/de1_incrementer/makefile create mode 100644 pnr/de1_mux2to1/de1_mux2to1_pins.tcl create mode 100644 pnr/de1_mux2to1/makefile create mode 100644 pnr/de1_pwm/de1_pwm_pins.tcl create mode 100644 pnr/de1_pwm/makefile create mode 100644 pnr/de1_pwm_incrementer/de1_pwm_incrementer_pins.tcl create mode 100644 pnr/de1_pwm_incrementer/makefile create mode 100644 pnr/de1_tone/de1_tone_pins.tcl create mode 100644 pnr/de1_tone/makefile create mode 100644 pnr/makefile create mode 100644 scripts/create_quartus_project_settings.tcl create mode 100644 scripts/de1_pin_assignments_minimumio.tcl create mode 100644 scripts/modelsim.ini create mode 100644 scripts/quartus_project_flow.tcl create mode 100644 sim/and2gate/makefile create mode 100644 sim/and2gate/makefile.sources create mode 100644 sim/cntdn/makefile create mode 100644 sim/cntdn/makefile.sources create mode 100644 sim/cntdnmodm/makefile create mode 100644 sim/cntdnmodm/makefile.sources create mode 100644 sim/de1_audio/makefile create mode 100644 sim/de1_audio/makefile.sources create mode 100644 sim/de1_tone/makefile create mode 100644 sim/de1_tone/makefile.sources create mode 100644 sim/falling_edge_detector/makefile create mode 100644 sim/falling_edge_detector/makefile.sources create mode 100644 sim/falling_edge_detector/makefile_qfsm.sources create mode 100644 sim/falling_edge_detector/makefile_rtl.sources create mode 100644 sim/falling_edge_detector/makefile_structure.sources create mode 100644 sim/incrementer/makefile create mode 100644 sim/incrementer/makefile.sources create mode 100644 sim/makefile create mode 100644 sim/mux2to1/makefile create mode 100644 sim/mux2to1/makefile.sources create mode 100644 sim/mux2to1/makefile_equation.sources create mode 100644 sim/mux2to1/makefile_rtl.sources create mode 100644 sim/mux2to1/makefile_structure.sources create mode 100644 sim/mux2to1/makefile_structure_errors.sources create mode 100644 sim/mux2to1/makefile_truthtable.sources create mode 100644 sim/pwm/makefile create mode 100644 sim/pwm/makefile.sources create mode 100644 sim/pwm_incrementer/makefile create mode 100644 sim/pwm_incrementer/makefile.sources create mode 100644 sim/resolver/makefile create mode 100644 sim/resolver/makefile.sources create mode 100644 src/a_falling_edge_detector_rtl.vhd create mode 100644 src/adcintf.vhd create mode 100644 src/and2gate_equation.vhd create mode 100644 src/audio.vhd create mode 100644 src/bclk.vhd create mode 100644 src/binto7segment_truthtable.vhd create mode 100644 src/cntdn_rtl.vhd create mode 100644 src/cntdnmodm_rtl.vhd create mode 100644 src/cntupdn_rtl.vhd create mode 100644 src/cntupen_rtl.vhd create mode 100644 src/d_ff_rtl.vhd create mode 100644 src/dacintf.vhd create mode 100644 src/de1_adc_rtl.vhd create mode 100644 src/de1_add1_structure.vhd create mode 100644 src/de1_add4_structure.vhd create mode 100644 src/de1_audio.vhd create mode 100644 src/de1_binto7segment_structure.vhd create mode 100644 src/de1_cntdn_structure.vhd create mode 100644 src/de1_cntdnmodm_structure.vhd create mode 100644 src/de1_dac_rtl.vhd create mode 100644 src/de1_matlab_audio.vhd create mode 100644 src/de1_mux2to1_structure.vhd create mode 100644 src/de1_sta.vhd create mode 100644 src/de1_tone.vhd create mode 100644 src/e_falling_edge_detector.vhd create mode 100644 src/fsgen.vhd create mode 100644 src/i2c.vhd create mode 100644 src/i2c_sub.vhd create mode 100644 src/i2c_write.vhd create mode 100644 src/invgate_equation.vhd create mode 100644 src/mclk.vhd create mode 100644 src/memory.vhd create mode 100644 src/mux2to1_equation.vhd create mode 100644 src/mux2to1_rtl.vhd create mode 100644 src/mux2to1_structure.vhd create mode 100644 src/mux2to1_structure_errors.vhd create mode 100644 src/mux2to1_truthtable.vhd create mode 100644 src/or2gate_equation.vhd create mode 100644 src/play_rtl.vhd create mode 100644 src/ringbuf.vhd create mode 100644 src/t_cntdn.vhd create mode 100644 src/t_cntdnmodm.vhd create mode 100644 src/t_de1_audio.vhd create mode 100644 src/t_de1_play.vhd create mode 100644 src/t_de1_tone.vhd create mode 100644 src/t_falling_edge_detector.vhd create mode 100644 src/t_mux2to1.vhd create mode 100644 src/tone_rtl.vhd diff --git a/doc/datasheet.yaml b/doc/datasheet.yaml new file mode 100644 index 0000000..a8aae06 --- /dev/null +++ b/doc/datasheet.yaml @@ -0,0 +1,26 @@ +--- +title: Pulse Width Modulator +subtitle: Datasheet +author: J Färber +date: April 2022 +lang: en-UK +geometry: a4paper, left=25mm, right=20mm, top=20mm, bottom=25mm +fontsize: 12pt +code-block-font-size: \scriptsize +titlepage: true +logo: images/uasa-logo.pdf +#toc: true +#lof: true +#lot: true +#toc-own-page: true +colorlinks: true +secnumdepth: 4 +header-includes: +# 4th level header rendering +# see https://stackoverflow.com/questions/21198025/pandoc-generation-of-pdf-from-markdown-4th-header-is-rendered-differently/21204829#21204829 + - | + ``` {=latex} + \let\originAlParaGraph\paragraph + \renewcommand{\paragraph}[1]{\originAlParaGraph{#1} \hfill} + ``` +--- diff --git a/doc/images/uasa-logo.pdf b/doc/images/uasa-logo.pdf new file mode 100644 index 0000000..6ad508e --- /dev/null +++ b/doc/images/uasa-logo.pdf @@ -0,0 +1,2737 @@ +%PDF-1.3 % +1 0 obj <> endobj 2 0 obj <>stream + + + + + application/pdf + + + Druck + + + + + 2015-04-28T13:11:41+02:00 + 2015-04-28T13:11:41+02:00 + 2012-02-03T04:14:54+01:00 + Adobe Illustrator CS5 + + + + JPEG + 155 + 256 + /9j/4gxYSUNDX1BST0ZJTEUAAQEAAAxITGlubwIQAABtbnRyUkdCIFhZWiAHzgACAAkABgAxAABh Y3NwTVNGVAAAAABJRUMgc1JHQgAAAAAAAAAAAAAAAQAA9tYAAQAAAADTLUhQICAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABFjcHJ0AAABUAAAADNkZXNjAAAB hAAAAGx3dHB0AAAB8AAAABRia3B0AAACBAAAABRyWFlaAAACGAAAABRnWFlaAAACLAAAABRiWFla AAACQAAAABRkbW5kAAACVAAAAHBkbWRkAAACxAAAAIh2dWVkAAADTAAAAIZ2aWV3AAAD1AAAACRs dW1pAAAD+AAAABRtZWFzAAAEDAAAACR0ZWNoAAAEMAAAAAxyVFJDAAAEPAAACAxnVFJDAAAEPAAA CAxiVFJDAAAEPAAACAx0ZXh0AAAAAENvcHlyaWdodCAoYykgMTk5OCBIZXdsZXR0LVBhY2thcmQg Q29tcGFueQAAZGVzYwAAAAAAAAASc1JHQiBJRUM2MTk2Ni0yLjEAAAAAAAAAAAAAABJzUkdCIElF QzYxOTY2LTIuMQAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAWFlaIAAAAAAAAPNRAAEAAAABFsxYWVogAAAAAAAAAAAAAAAAAAAAAFhZWiAAAAAAAABvogAA OPUAAAOQWFlaIAAAAAAAAGKZAAC3hQAAGNpYWVogAAAAAAAAJKAAAA+EAAC2z2Rlc2MAAAAAAAAA FklFQyBodHRwOi8vd3d3LmllYy5jaAAAAAAAAAAAAAAAFklFQyBodHRwOi8vd3d3LmllYy5jaAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAABkZXNjAAAAAAAAAC5J RUMgNjE5NjYtMi4xIERlZmF1bHQgUkdCIGNvbG91ciBzcGFjZSAtIHNSR0IAAAAAAAAAAAAAAC5J RUMgNjE5NjYtMi4xIERlZmF1bHQgUkdCIGNvbG91ciBzcGFjZSAtIHNSR0IAAAAAAAAAAAAAAAAA AAAAAAAAAAAAZGVzYwAAAAAAAAAsUmVmZXJlbmNlIFZpZXdpbmcgQ29uZGl0aW9uIGluIElFQzYx OTY2LTIuMQAAAAAAAAAAAAAALFJlZmVyZW5jZSBWaWV3aW5nIENvbmRpdGlvbiBpbiBJRUM2MTk2 Ni0yLjEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAHZpZXcAAAAAABOk/gAUXy4AEM8UAAPtzAAE EwsAA1yeAAAAAVhZWiAAAAAAAEwJVgBQAAAAVx/nbWVhcwAAAAAAAAABAAAAAAAAAAAAAAAAAAAA AAAAAo8AAAACc2lnIAAAAABDUlQgY3VydgAAAAAAAAQAAAAABQAKAA8AFAAZAB4AIwAoAC0AMgA3 ADsAQABFAEoATwBUAFkAXgBjAGgAbQByAHcAfACBAIYAiwCQAJUAmgCfAKQAqQCuALIAtwC8AMEA xgDLANAA1QDbAOAA5QDrAPAA9gD7AQEBBwENARMBGQEfASUBKwEyATgBPgFFAUwBUgFZAWABZwFu AXUBfAGDAYsBkgGaAaEBqQGxAbkBwQHJAdEB2QHhAekB8gH6AgMCDAIUAh0CJgIvAjgCQQJLAlQC XQJnAnECegKEAo4CmAKiAqwCtgLBAssC1QLgAusC9QMAAwsDFgMhAy0DOANDA08DWgNmA3IDfgOK A5YDogOuA7oDxwPTA+AD7AP5BAYEEwQgBC0EOwRIBFUEYwRxBH4EjASaBKgEtgTEBNME4QTwBP4F DQUcBSsFOgVJBVgFZwV3BYYFlgWmBbUFxQXVBeUF9gYGBhYGJwY3BkgGWQZqBnsGjAadBq8GwAbR BuMG9QcHBxkHKwc9B08HYQd0B4YHmQesB78H0gflB/gICwgfCDIIRghaCG4IggiWCKoIvgjSCOcI +wkQCSUJOglPCWQJeQmPCaQJugnPCeUJ+woRCicKPQpUCmoKgQqYCq4KxQrcCvMLCwsiCzkLUQtp C4ALmAuwC8gL4Qv5DBIMKgxDDFwMdQyODKcMwAzZDPMNDQ0mDUANWg10DY4NqQ3DDd4N+A4TDi4O SQ5kDn8Omw62DtIO7g8JDyUPQQ9eD3oPlg+zD88P7BAJECYQQxBhEH4QmxC5ENcQ9RETETERTxFt EYwRqhHJEegSBxImEkUSZBKEEqMSwxLjEwMTIxNDE2MTgxOkE8UT5RQGFCcUSRRqFIsUrRTOFPAV EhU0FVYVeBWbFb0V4BYDFiYWSRZsFo8WshbWFvoXHRdBF2UXiReuF9IX9xgbGEAYZRiKGK8Y1Rj6 GSAZRRlrGZEZtxndGgQaKhpRGncanhrFGuwbFBs7G2MbihuyG9ocAhwqHFIcexyjHMwc9R0eHUcd cB2ZHcMd7B4WHkAeah6UHr4e6R8THz4faR+UH78f6iAVIEEgbCCYIMQg8CEcIUghdSGhIc4h+yIn IlUigiKvIt0jCiM4I2YjlCPCI/AkHyRNJHwkqyTaJQklOCVoJZclxyX3JicmVyaHJrcm6CcYJ0kn eierJ9woDSg/KHEooijUKQYpOClrKZ0p0CoCKjUqaCqbKs8rAis2K2krnSvRLAUsOSxuLKIs1y0M LUEtdi2rLeEuFi5MLoIuty7uLyQvWi+RL8cv/jA1MGwwpDDbMRIxSjGCMbox8jIqMmMymzLUMw0z RjN/M7gz8TQrNGU0njTYNRM1TTWHNcI1/TY3NnI2rjbpNyQ3YDecN9c4FDhQOIw4yDkFOUI5fzm8 Ofk6Njp0OrI67zstO2s7qjvoPCc8ZTykPOM9Ij1hPaE94D4gPmA+oD7gPyE/YT+iP+JAI0BkQKZA 50EpQWpBrEHuQjBCckK1QvdDOkN9Q8BEA0RHRIpEzkUSRVVFmkXeRiJGZ0arRvBHNUd7R8BIBUhL SJFI10kdSWNJqUnwSjdKfUrESwxLU0uaS+JMKkxyTLpNAk1KTZNN3E4lTm5Ot08AT0lPk0/dUCdQ cVC7UQZRUFGbUeZSMVJ8UsdTE1NfU6pT9lRCVI9U21UoVXVVwlYPVlxWqVb3V0RXklfgWC9YfVjL WRpZaVm4WgdaVlqmWvVbRVuVW+VcNVyGXNZdJ114XcleGl5sXr1fD19hX7NgBWBXYKpg/GFPYaJh 9WJJYpxi8GNDY5dj62RAZJRk6WU9ZZJl52Y9ZpJm6Gc9Z5Nn6Wg/aJZo7GlDaZpp8WpIap9q92tP a6dr/2xXbK9tCG1gbbluEm5rbsRvHm94b9FwK3CGcOBxOnGVcfByS3KmcwFzXXO4dBR0cHTMdSh1 hXXhdj52m3b4d1Z3s3gReG54zHkqeYl553pGeqV7BHtje8J8IXyBfOF9QX2hfgF+Yn7CfyN/hH/l gEeAqIEKgWuBzYIwgpKC9INXg7qEHYSAhOOFR4Wrhg6GcobXhzuHn4gEiGmIzokziZmJ/opkisqL MIuWi/yMY4zKjTGNmI3/jmaOzo82j56QBpBukNaRP5GokhGSepLjk02TtpQglIqU9JVflcmWNJaf lwqXdZfgmEyYuJkkmZCZ/JpomtWbQpuvnByciZz3nWSd0p5Anq6fHZ+Ln/qgaaDYoUehtqImopaj BqN2o+akVqTHpTilqaYapoum/adup+CoUqjEqTepqaocqo+rAqt1q+msXKzQrUStuK4trqGvFq+L sACwdbDqsWCx1rJLssKzOLOutCW0nLUTtYq2AbZ5tvC3aLfguFm40blKucK6O7q1uy67p7whvJu9 Fb2Pvgq+hL7/v3q/9cBwwOzBZ8Hjwl/C28NYw9TEUcTOxUvFyMZGxsPHQce/yD3IvMk6ybnKOMq3 yzbLtsw1zLXNNc21zjbOts83z7jQOdC60TzRvtI/0sHTRNPG1EnUy9VO1dHWVdbY11zX4Nhk2OjZ bNnx2nba+9uA3AXcit0Q3ZbeHN6i3ynfr+A24L3hROHM4lPi2+Nj4+vkc+T85YTmDeaW5x/nqegy 6LzpRunQ6lvq5etw6/vshu0R7ZzuKO6070DvzPBY8OXxcvH/8ozzGfOn9DT0wvVQ9d72bfb794r4 Gfio+Tj5x/pX+uf7d/wH/Jj9Kf26/kv+3P9t////7QAMQWRvYmVfQ00AAv/uAA5BZG9iZQBkgAAA AAH/2wCEAAwICAgJCAwJCQwRCwoLERUPDAwPFRgTExUTExgRDAwMDAwMEQwMDAwMDAwMDAwMDAwM DAwMDAwMDAwMDAwMDAwBDQsLDQ4NEA4OEBQODg4UFA4ODg4UEQwMDAwMEREMDAwMDAwRDAwMDAwM DAwMDAwMDAwMDAwMDAwMDAwMDAwMDP/AABEIAJsBAAMBIgACEQEDEQH/3QAEABD/xAE/AAABBQEB AQEBAQAAAAAAAAADAAECBAUGBwgJCgsBAAEFAQEBAQEBAAAAAAAAAAEAAgMEBQYHCAkKCxAAAQQB AwIEAgUHBggFAwwzAQACEQMEIRIxBUFRYRMicYEyBhSRobFCIyQVUsFiMzRygtFDByWSU/Dh8WNz NRaisoMmRJNUZEXCo3Q2F9JV4mXys4TD03Xj80YnlKSFtJXE1OT0pbXF1eX1VmZ2hpamtsbW5vY3 R1dnd4eXp7fH1+f3EQACAgECBAQDBAUGBwcGBTUBAAIRAyExEgRBUWFxIhMFMoGRFKGxQiPBUtHw MyRi4XKCkkNTFWNzNPElBhaisoMHJjXC0kSTVKMXZEVVNnRl4vKzhMPTdePzRpSkhbSVxNTk9KW1 xdXl9VZmdoaWprbG1ub2JzdHV2d3h5ent8f/2gAMAwEAAhEDEQA/APVUkkklKSSSSUpJJJJSkkkk lKSSSSUpJJVOodSx+nsa67c4vMMYwAkx9L6Ra32ps5xhEymRGI3JXRjKUhGIsnYNtZX1kZY7pu5p Iax7TYOxafZ7v7bmOV7Dy6cyht9JOx0iDoQRo5rgpZNDcjHtodxa0tnwkcqPNEZsE4xN+5A8JHj8 q/HI4ssTIVwS9QP/ADmj9X8l1/TmteS59DjWSTJj6TP+g5aa5n6tXuqzbMZ+htbqD+/WfcP81z/8 xdMovh+X3OWgT80f1cv8D/0FfzmPgzyraXrH+EpJZ9vXMGrM+yOLtwcGOsA9gcfzXOnd/wBFaCsQ ywmZCEhLgPDKv0ZMMsc4UZRMeIXG+oY2PbXW6x5hrAXOPgAJK5voD8jJ6rZkuc7Vrn266Hef0dZ/ qfmf1Fp/WHI9HprmD6V5FY+B91n/AIG1yF9WcfZhPyCNb3mD/JZ7G/8AT9RUs5OTncOIH04gc06/ 5v8AL+u2sQEOVy5DvkPtx/a7CShddXRU+607a6wXOPkFV6f1fF6g57Kg5j2CSx4AJB/OG0uV2WWE ZxgZATn8sesmqMczEzESYx+aTdVDreU7G6da5jttj4rYRoZdpLf6rNzlfXO/WnJ/SU444Y02uHmf ZX/6MUPPZfa5bJIGiRwx/vT9LLymPjzQHQHiP+C2fqxXYMS17idj7IraeBtEOc3+s5bKr9PxvsuF TR3Y0bv6x91n/TKJkX1Y1L77TtrrEuPKdy0PZ5eEZGuCNyvp+lJbnl7maRjrxSqNdf0YpElS6f1b G6gXtqDmPrgljwAYP5w2uerqlx5IZIiUJCUT1CycJQkYyHCR0Kkkkk5apJJJJT//0PVUkkklKSSS SUpJJJJSkkkklKSSSSUpU+o9Mo6gxjbS5jqySx7YkT9Ie4Ob7lcSTZwjOJhMCUTuCuhOUJCUTUhs UGFh04WO3Hpna2SS7UknVznI6SSMYiIEYioxFABEpGRMibJ1JeV6h/k7rnrjRu9t/wDZf7b/AP0a up5WH9aMcOqpyQPouNb/AIP1b/0mf9NX+i5H2jptLiZewem/4s9n/Sb71Q5X9VzfMYOkv10P8L52 3zH6zl8OXrH9VL6fKjt6DhW5n2txfJcHurBGwuHc6bv+ktJJJXYYscDIwiI8Z4pV+kWtPJOYAlIy 4RUbeZ+s15szK8ZmpqbMD9+ww1v+a3/procWhuNjVUN4qYGz4wOVzWBPUeu+udWb3Xf2We2n/wBF LqlS5D9Zk5jmP358EP7mP+UWzzfohiw/ux4pf3pfykjvpryKX0Wia7AWuHkVV6d0jG6e99lbn2Pe Nu55EhvO0bWtV5JXZYscpxyGIM4fLLrFrDJMRMBIiMvmClyjf8o9fnms2z4jZTx/n7P/AARdD1LJ +y4F94MOa0hn9Z3sr/6blkfVbG912SeGgUsP/Ts/9FKlzv63mOX5fpxe9P8Auw2/7ts8r+rw5s3W vbj5y/lB6FCycerJofRaJZYIMaH4hFSV8gEEEWCKIagJBBGhGoaPTukY/T3PfW51j3iC58aAfmt2 hqvJJJuPHDHEQhERiOgTOcpyMpHiJ6qSSST1qkkkklP/0fVUkkklKSSSSUpJJJJSkkkklKSSSSUp JJJJSklXz/tf2O37HH2iP0cx46xu9u7b9Dcufj6zf8P/ANBVuY5r2ZCPtZMli7xx4os+Hl/ciT7k IUaqZou91LGOVgX0AS5zSWf1m+9n/Tasj6rZPuvxjw4C5g/8Ds/9FIEfWb/h/wDoKXSOn9Sq6lVc +l1bBu9RziIhwP7p/f2qjLPLJzeDLDDljX6ufHHTgn/3vFJtjFGHL5ccsuOV+uPDL9KP/fcL0ypd ZyPs/Tbngw949Nnxf7P+jO9XVkfWHFzMmmluOz1GMeXWNETMbWO90fvPWhzcpRwZDAGUuEiIjrL1 en/mtLlxE5oCRAjdm9vT6kP1XxwK78kj6RFTPg33O/6Tv+gt1cpVT9YaaxVSy6utsw1uyBJ3H/pK cfWb/h/+gqPK837OGGP7vmJiNSIfpH1Sbefl/dySn72PXb1dBs9Qksrog6t+l+37tmnp+pt3Trvj Z+Z9H6S1Vo4cnuQE+GUL/RmOGTSyQ4JmPEJV+lE3FwvrRkBtVOMD9Nxsf8GaN/6T/wDoK/0XH+z9 NpaRDnj1H/F/v/6LfasrrvT+oZGebK6TbUWNawtI0Anc10lv57kKPrN/w/8A0Fme9LHzmbLPDlnp 7ePgjfpG5/wm97UZ8tjxxyQj+nPil+kXqEly8fWb/h/+gt3pn237FX9u/n9ZmJifZv2e3ftV7Bzf vSMfayY6F8WSPDHyaubl/bjxe5CetVA3JtpJJKywKSSSSUpJJJJT/9L1VJJJJSkkkklKSSSSUpJJ JJSkkkklKSSSSUgzcqvDxbMmwEtrEkN5MnaP+kVkf86q/wDuM7/PatXqN5x8G64VevtbrXyCD7Xb vpez99cz+2Kv+4GJ/mf7Fm8/zM8WSMY5hiuN8Jh7nXfibvKYI5IEnEclGr4+H8Hd6Z1qrqFz6RW6 t7W7xJBBE7fzf6y0lidA6gMm62tuLXQA0ONlLdomYDLNPpa+xbas8nkOTDGcpjIST6hH2/8AmsHM wEMpiI8Gg9N8akkklZYXP6n1irp72VurdY+wF0NgAAacuVH/AJ2Y/wDoHf5zf70T6yYdtldWXSJO PO8ASdph2+P+Dcz3IZ+sWD9m3jH/AFiPowNk/ver/o/+mszPzGWOfJCWeOCAAlj4ocfHH9LhP95v 4sOOWKEhiOWRJjOp8PBLpbf6Z1erqLrGtrdW6sAw6CCHTwW/1VfWN9WsO2qizKtBDsgjYCIO0Sd8 f8I562Vb5OeSeCE8vzys7cOl+n/mtbmYwjllHH8o076/pKTeSdYvVeh5OVl/a8e0B8AbXkt27f8A R2M3bU/PknCHFjxnKb+UHh9P7y3FCE5VOftivmri1dpMuaPQutWjZbcCzwfa9w/zdq3Om4RwcNmM X+oWyd0QNTu2tbr7WqPBny5JESwSxRA+aZ/S/d4V+XDjhG45RklfyxHTvxNpJJJWWBSSSSSlJJJJ Kf/T9VSSSSUpJJJJSkkkklKSSSSUpJJJJSkkkklKSSSSUpJJJJSkkkklKVb9nYHqer9mq9SZ3bBM /vcKykmyjGVcQBraxaRKQ2JF9lJJJJyFJJJJKUkkkkpSSSSSlJJJJKUkkkkp/9Tp/qv9YOoZf1l+ seD1DKa7F6fdWzDrcK2bGudeHDcxrH2fzdf8456k/rvUD/jFo6NVkh3TH4BvdS0MINm6xu71dvrf Ra32eoud6J9WOh/WH64fWlvWMb7S3FyWGkepZXtNjr/U/mH1bt3pV/SRsDofTuh/4zqcDo9P2al3 TX2hhc+weo4vZv3XOsf/AINn5ySnquofXn6p9NzjgZvUq68oHa5gD3hp4222VMfVU7/jXrVv6n07 HwD1K/JqZghjbPtJePTLHx6b22Tsf6u9npbf5xecfUfP+qWJ9Weo4X1idTV1EW3DqtOXHr2kE+2t r/097mRs9On9J9q9T/CWLIZTm0/UX6uXdVY53Ra+q+rk1kF36sX+1z2N93pP/XNn+k9ar/SVJKfT +i/W76udessp6VnMyLahLq9r63x++2u9lT7GN/fYua+qn+MXprPq9iXfWfqjP2jkPt0DJeGtftr9 WrCq/QN2/RfayvetOvq31HyvrR05mEKcvqxpsGNk4kWMqra2PTvsod6bHOr9RtO9v6H9J/Mev+m5 v6l9J6ZZ/ixz8mzGrsvvpynWWvaHPJqa9tG17vcz0fTa+rb/ADdv6X+cSU9/1Dr3Rum9Pb1PNzKq sKwNNV+7c1+8b6/Q9Pe6/ez3t9Hf+j96D0X60/V/r24dJza8l9Yl9fuZYAIG/wBG5td3p+7+c2bF wDcLBy/qh9U7n9Xq6R1TGNj+nPyAHVPcHeo71A/2V+m6in07rP0X+A9PffWjYPWOs5PU+tdKtZg5 /WbOlXGrqvShNhcxu2mi272e/wBR7PoMr9O30P5z/BpT19n17+qFfUT01/U6W5QdsI93ph37rsrb 9lb/ANvLJyfrgel/XjqOJ1fPbj9FxsJltdb2t/nnGn+bLGfarrNht/RN9RYnRer/AOL2r/F5Rj9T FNwZDsrBaR9qfeH621s31Xu/kXeps+zfof5v9Er/AE7C6dmf40ckvx2upo6ZTbi1WsLfTP6vXWfQ ta11VtdVmzY9m+pJT1uB9Z+g9R6bd1TDzGW4eM1zsiyHAsDRvcbKntbcz2e7+bRbOu9Jq6QOtWZL W9NLW2DJh23a4hjHbdu/3Pd+4uCox6qMv/GLjYtYrqGK3ZVWIALqMp7trG/vPe9VOpfWPorv8U1P TK8yp/UH000fZQ6bQ6uxllu+r6bK211WPba/9E//AK4kp6zqHXs5v12+r/T8TI/yZ1LHvttrDWkP 21W20v8AUcz1mfRZ9B6v9V+u31W6PmfYeo9QrpydN1Qa+wtn6Pq+gyxtP736Vc1Z/wCLf6l/+m+3 /wBtrVhfVq23GPWsTP65h9HzH5V37QozsWu514P0z9ovup9ep7jd+qM9T/Tf9qUlPrVF9ORSy/Hs bbTa0OrsYQ5rmnVrmPb7XNciLl/8XGPiY/1ZZTg556nhtusNF5pfjwCd1lXpXue522/1f0i6hJSk kkklKSSSSUpJJJJSkkkklKSSSSUpJJJJSkkkklKSSSSU/wD/1fTcfp+Bi33ZGNjVU35J3ZFtbGtf YRJ3XPYA6z6bvppHp+Ac0Z5x6jmtb6bcnY31Qz/Ri6PU2a/RWL9cvrhX9V8bGeMY5uRlvc2vHD/T Oytu+63f6d383NTfof4RbHTM+nqfTsbqFH81l1MuYJkgPaH7HfymfRckpr5v1b+r/UMn7XndOxsn I0m22pjnGBtb6jnN/SbW/vq9bjY91Dsa6plmO9ux9L2hzC3jY6t3scxESSU0endC6N0ovd03CoxH W/zjqa2sc4c7XOaN2z+Qi0dM6dj4bsGjFpqw3hzX4zK2tqIf/ONdS1vp/pPz1ZSSU0beidGuwmdP twcd+FVrXjOqYa2nX3V1bdjHe530FLpvR+ldKY5nTcSnDbZHqeixrC6J2+o5o3P27vz1Qy/rKMb6 14P1cOPuOdQ+8ZO+Nuz1D6fo7Pfu9H/SrbSU5x+rnQDn/tE9Oxvtu71PtHpM3753+tu2/wA9u/wv 84rLen4LMx+ezHqbm2N9OzJDGi1zPb+jfdHqOZ7Ge1WEklIKcHCoyLsmjHqqyMmDkXMY1r7C36Hr WNG6zb/LVFn1U+rFfqbOk4YFwi0ehXDhIftI2fR3sY9aqSSmt+zOnevRk/ZafXxW+njW+m3fWwjZ 6dL43VM2HZtYq+f9Xeg9Svbk5/T8bKvbAFttTXOgfRa5zm+9n8hyfrvVf2P0x+f6Xr7LKa/T3bJ9 a6rF3b9r/oet6n0VoJKY1111Vtqqa2uutoaxjQA1rQNrWta32ta1qkqPQ+p/tfo+H1P0vQ+11Nt9 Ldv27hO3ftZu/wAxXklKSQMHJdl4dOS+mzGda0PNFw22Mn8yxo3bXo6SlJJJJKUkkgMyHOzLcb0b GtqrrsF5H6N5sNrTXW786yn0f0v/AB1SSk6SpdI6pT1bAZnUsdXW99tYa+N002WYz/olzfc+lXUl KSSSSUpJZfSerZfUsjLIxmU4ONfdjV3G3da+yh/oWudjCr06qXWNs9N32r1PZ/NfpFqJKUkkkkpS SSSSn//WsdZ+snQT/jIdZ1vJ9Hp/SMWzGpG19gffc3Zk+yhljv5nJsps/wDC6f6ldXa/6hde6ZTe bHdJqyvst7ZYTRYy63Hvb9Gxj/Wbkfy6vYux6F9VOn9GObYHPzMjqF5yMi/IDC4uMuhvpsrY1m99 r/8Arigz6ndMZ1vP6sH2R1Sg42Zh+0UuaWsqc6GNbY1+2v8A0n59v76SnnMjMyW/4nRl/aLBkHGr /T73b9xuaz+dnf8AyFWzrMnrXVfq19WMrMuxunZPS6srINTyyzIs2P8A0L7fdv8A6Pv93/C/4T0v T0W/4qcH7I/p9vVuoW9PBLsfENjRXW4nd6np7PSss+l/gmfTel9cuhgYnSsV3R7usYOFW2g5WLZs zqdgrZ6lVTNrMj1G17tm30/UZ/gf0aSmt0jCs6R/jFPSMXqF+ViV9NdZVRfa6wUuc8bcd43fmfzt f+E9G9c5azJwar7frXjdbxurtsn9vYtjn1N3H9G1kPpxWU/m+nU//ivS/mWdF9Tvq28fWW7qmP03 K6T0pmI7Gb9seRlX3WOa+3JsG99tLtv5zH/4Ov0f8J6Wjb/i49Wg9Pd13qLukvdufhve1xOu/b9o czd6e/3bNiSnH+sGLT1z68/V7HozrmY+Z04uGZU707rKtt93se1tex2VW39J+j/m/U/Rq30am36t fXa36tYuVfldLzME5bKbn7zRYHPb7X/mtd6b/wBz+dp9T+b9Ra/WP8X/AErqeTh5DcjJwT07HbjY YxnhvpiuTRY2xzX3b6p/0iP9XPqdi9EycjqF2Vf1LqeW0V3ZmUdziwR+iYP3PZV9N9n81Wkpwfq1 mZL/APFLk5dt73ZAxM8i9zyXhwOQKz6hO/c327Fl9St6pk9D+pFGLnXYuRnO9J+S17i6Xipvqv8A c31nM3e3etxv+KvpzGZGJX1TPr6XeS8dOZaBUH/mPeC1zbvSc1jmeoz/AAVXq2WrVP1KwDT0Or7R dt+r7w/GPsl5Gz+f9n/B/wCD2JKeZ61011HWOg/UZvUMmnpN7L78nIdZF+Q9zrr/AEbL2tY13vG3 Zt/w3+Eu9FE6dgHov+MnD6Pi5+RkYAwrLWY11zrBUXep+hiduz2erXv9/vWr/jC6c7Npw/U6O/q+ LW93qvxbDXl0btn6XFaP5/dHvpd7N9VX/G1ZH1Q+rtjfrY3q2J0zK6X0zGx31l/UD+s332fTtsrc +xzPY7839F+h/wCESU9N9eyB9WbidAL8Mk+Qy8VdAgZ2Fi9Qw7sLMrF2NkMNdtZkS1wg6thzf67F iH6s9YsrOHd9YMuzpxb6bqzXSMhzNuz07OoNr9T3fn2+l9o/4ZJTk9Oqy7vqx9UMOjKuwftTmsus odtc6r7HmXvr/wCuen7LPp0v/T0/pq61r4LX9O+tR6VTddbhZGCcr08i6zIcy2u1lG6q7Ksuuay2 u79JXv2fo/6603dIxZ6cKgaaulP3Y1TI2x6N2C2sz+YynITnpdR6yzq+93rMxnYgr02bXvZeX8b9 +6r99JTznT83Oq+r31Y6zbkW2NHoU9Q32mLK8xoxG3X+p/O2UZ1mHb6jv0jKvtH+kUuodV6o3G6z 1bDfYP1mjpXTmbdwaW3MwsvNqx7bK8ezI+3ZWTTX63p12fYcf1P0K2qvq/iM+ro+rznPfijGOL6h j1Nu30/U+js9Vv02ez6adv1f6d+wm9CsabcRtQqcXH3uI9/2lz27f1n1v1n1m/8Aaj9KkpwMarq+ NnYD+m4XWGFtra8/9o5NV9NtDttd99gf1DJ9HJo2/aKX4VNf/cf0vSt9l7AxMjN+svWLcnMyHYuD k0DEw2Wvrra/7NiZFj3ilzHXVvc7+jW/qn89+h33KzX9XsyzIqd1Lq2Rn42La26jHLKqQX1kupdl 2YtdT8r0nbXtZ+ho9Sv9LTYtDE6dVi5eblMc5zs+1l1jTENLKqsQBmn7mO1ySnlcn1MW65/Xbup9 PyX5D3U9Yptc7AZWbf1Jjsau27Dx6PQ9GnI/aWB6f87Zbf8A4dbga7L6/wBUwbbbRj/Y8JzWV2vr LXOs6h6j6n0vrspfZ6NXqPqdv9irP+qVr6T053Vcp3RXk78B2xzywu9R2H+0HN+2fY3fzWzf9o9D 9D9q2LYqwK6+pZHUA5xsyaqaHMMbQ2h2RYxzfztzvtj9ySnkug4GTV9SMjJ6Xbkfb225F1TDdbYH vxMvItrx21WWbGNzfT+z5Xp7PtPq/p/UWyzqJ6v1rpzcG57cCnFHUsgt9os+0h1HTKLfcHem5n23 Jsq2/wA5j4yJgYmH9WMa85fUhX059rnY7Mo1VMpNr7cmytt59N9vqW3P/nrPoMQfqT05mJ0h2U2t 1X7RtflV1WGXV47jt6did9lePgto/Qf4D9IkpL9Ycm92X0vpFVtmO3ql9jL76jteKqabcp9VVo91 Vl7q66/VZ+lZV6vpfpP0iq20DpfXMLpVN+S/B6zTk12VWZNtj67KWsuZk42Rc+zLo31vuqt9PI/n Ps9leyz6ev1bpVfU6amm63FvxrW34uVQQLK7GhzNw3h9VjLKrLKLqbq7KrabbFX6d0O2jN/aXUc2 zqOc2s0Uve1tVVVbiH2jHxqfY2y9zKvXusdbb+ir/m6/Ykpz/qV0+jHpz7q33ucOoZ1O2y+61m1u TYGu9K+yyv1vZ78jb69v+FsXTKn0zptXTqrq6nueL8i7KcXRo6+x2Q9jdob7Gus9iuJKUkkkkpSS SSSn/9f1VJJJJSkkkklKSSSSUpJJJJSkkkklKSSSSUpVxn4ZzndOFrTmMqF7qPzhW5xrbZ/V3tRn vZWx1j3BrGAuc4mAANS5xXD1Odj42N9eLf0duVl+vlboBb0zK9PBxq3+kH7mYtFfT+pP/wCGZk/v pKe6SWN9YOq9Twb+nYvTKKsjI6jc+gC9xY1u2q3I9UuYHeyv0t9jNv6T+brS6d1Hq1fVXdJ6wyl1 tlLsnDy8UOZXYxjmVZNNmPc+6yi/HffR/hrq7qrv8H6b0lOygDMxTmOwRYPtTaxe6ruK3OdWyz+1 ZW9q5jF+sf1ps6DT9ZcjExGYApGTkYTC85BoDfUuyqMhzm47H7f09OFZU/8AQ/8Aaz1voXcexlv1 4vsrIcx/SMdzXDgg5GWWlJTu0X0ZNLL8ext1Ng3V21uDmuB4cx7Ja5qIuVp+s7MX6s9HuooxsbK6 rW1mLQ5woxKv0br7LLHf4PGx62fzdf6S1/p0f4T1GWelfWNz+qt6Tm5OHmW5Fb7cTJwXQ13pen6+ PfjOuyn03N9T1an+vZXfV6n816X6RKd3IvpxqLMi9wrppY6yx54a1o3vcf6rQnpuqvprvpcH1WtD 63jgtcNzXf2mrkepdW691T6t5/VcOrG/ZFuNkeljv9QZNlAZdX9rbf8AzNL7Nvr0Yv2W71K/+1NX qfouk6IAOjYABkDGpg+P6NiSkHVutdEw7GYPUH+rdc31G4jKn5Nha06XOxsavItbV6jP559fp+or PTeq9P6rjfaen3tvqDixxEhzXt+lVdU8Ntptbu91VrGWLIso6r0jruf1LGwf2nidU9F1voPrZk0u orNGz08p1NWTjOa1tlW3IZbXdbkfovenxOs/V5lfVuvV02Y2ZRUx3V6LWGrJApY+zGbdj2lrN7qn vZj3s/R5H8369no/o0p6FDqyKLjY2mxlhpf6doY4OLHgNf6dm36Fmx7H7HLGxsj64EUZWTjYfpXO b63T6y8X0MeWjf8AbrH/AGbLtxmu35FP2bG/7r3Wfo/VA76xU9PxetZZxaw/G6g3FrZWW1evdbXh tpsyb7P0bHb8ljL8h/8ANY1P/BpKekSXL4v1oux83Do6nm9Nyq+oWNx2HAe7dTe8PdXVYyy3I+00 WuZ6LMn9W/TbP1f9J+ilj9X+tHUWZt2BTh01YGVk4wbf6jnZHoWurb6bq3Mbhfomen61n2vfkf8A aeqn+eSnpklz7/rFk5zOm4/Rqqxm9UxW5+7JJNePjH0psurqc2y+57r2000V2V7/ANJ+nr9JPldc 6p0fAyLes0U22ssqqw7qHimrIfe/0qWPZkPuswfRdt+1Pssvq9H9NT6v8wkp30lzGH9Z76c/Exup ZnTsxnUHiit+A4h1V5a+xtV1dl2Q6+i30/Srym+h+m+njfpf0b4vW+vdQtyrun/YHtw8iyl3S3Od 9rLKXux3WXZPqNqxLr9nrUUWYdtfpel+s/pPUSU//9D1VJJJJSkkkklKSSSSUpJJJJSkkkklKSSS SU5P1mws7qPSz03DENzrGUZdocGmvFcf117d4d6j347X47Gf8MoXfU76qXU2Uu6RhMFjSwuZj1Me A4bd1djGB9b/AN17FspJKeKyx1/Fr+q1VtNd/V8S++rbZYQy4U4uVV6vrj1XV2ZmMz1v0jP0d9n6 VbPTqerZ3WB1fqWKOn1Y1D8bExC9ttpNz6rcnIyH0bqK/wCi49dFVdt3+GssTdc/8UH1c/8ADWR/ 7Z5S3UlPC9Ib9Z8/6m4PRGYdLas3Brp/avqj0q8a2rZLsT2Zb8+qh3p+mz9Vsu/TfamM/RLocXpN 2N9ZHZlbA3Bb02jDqM676rb7Nm36X81ZX7k/1P8A/En0f/wlj/8Anti2ElPJM+rOcz6v9C/V6b+p dDYN2HeQarQ6p2Nk43rQ9ldjmu9Si7ZZX6tXv/Rv3rQ6VRm2Z7cg9Jo6Pi1NcC13pPyLXuDdm12G X049Ff6T/D22Xf6On/CbqSSnj3YH1nxOgXfVfEwmZDBRbjYvVH3sawUOFjKPWo2/aPtdNRrp2Mq+ zWP/AEv2mtdN0yh+N03Ex7Btsporre2ZgtY1jhu/O4VpJJTgvf8AWHpefkuqxX9ZwMuz1qtl1bLs d21jH43p5bqKLMTcz1aHVXepX+k9Sr/DKqfq/n9bHVcvq7G4FnU8MdPx8ZjvWdTU022tyMp7HMpu yXX5G/0qf0VVdfp+vb6i6hJJThYud9bLTRi5HTase1jmjMzjc1+O5jS31XYVNbhmusvZu9JmVVj/ AGf/AAll+z9LVyPq3m5WJ1iuKmX39Tr6hgG6X1ONLMP0m5LKzv8ASusxLaLf+Df6i6dJJTzeHR1O /MxtvQsbpDKnh+VkWGm5zgJ/Q4DcT3++zZ+s5P2b06/+03qfzd7onT8nDwc2m9obZfmZl9YBBll9 9t1DtP3q7GLWSSU8ridG6r0qjo3UcbHGVmYXTaum5+F6jWOcwCh2/Fuefs/rY11VnstfXVfVZ/P1 o+f0/rfXunW/a6KMKyq+nJ6bi2k2nfjv9Xb1Kyh7qfTy9vpenjer9mr/AEnqZNn6JdGkkp5zBo6j fl45HQsbo7KXB+Te802udAd+hwRie7+c2frOR9n/AEf/AGm/0dLqXSutdTDsTN6TjO6iH7cf6xUu ZWKmtd6tGXVWXu6pTlUbWfqbH2Y9tv8A2r+zWLsEklP/2Q== + + + + + + uuid:551f298d-e043-484f-abf6-792d02bf587f + xmp.did:CDCC195597EDE411BF6F8D436E9B2F4B + uuid:5D20892493BFDB11914A8590D31508C8 + proof:pdf + + xmp.iid:CDCC195597EDE411BF6F8D436E9B2F4B + xmp.did:CDCC195597EDE411BF6F8D436E9B2F4B + uuid:5D20892493BFDB11914A8590D31508C8 + proof:pdf + + + + + saved + xmp.iid:05801174072068118083DE96E4AF4DB7 + 2011-12-18T23:44:36+01:00 + Adobe Illustrator CS5 + / + + + saved + xmp.iid:FE00D69E062168118083DE96E4AF4DB7 + 2011-12-19T11:12:27+01:00 + Adobe Illustrator CS5 + / + + + converted + from application/postscript to application/vnd.adobe.illustrator + + + saved + xmp.iid:FA7F1174072068118083A72FB8BC9D6D + 2012-02-03T03:52:24+01:00 + Adobe Illustrator CS5 + / + + + saved + xmp.iid:00801174072068118083A72FB8BC9D6D + 2012-02-03T04:14:54+01:00 + Adobe Illustrator CS5 + / + + + converted + from application/postscript to application/vnd.adobe.photoshop + + + saved + xmp.iid:CDCC195597EDE411BF6F8D436E9B2F4B + 2015-04-28T13:11:35+02:00 + Adobe Photoshop CS6 (Windows) + / + + + converted + from application/postscript to application/pdf + + + derived + converted from application/vnd.adobe.photoshop to application/pdf + + + saved + xmp.iid:CECC195597EDE411BF6F8D436E9B2F4B + 2015-04-28T13:11:35+02:00 + Adobe Photoshop CS6 (Windows) + / + + + + + + Print + + + False + False + 1 + + 296.999959 + 210.001652 + Millimeters + + + + Black + PANTONE 151 U + + + + + + Standard-Farbfeldgruppe + 0 + + + + Weiß + CMYK + PROCESS + 0.000000 + 0.000000 + 0.000000 + 0.000000 + + + Schwarz + CMYK + PROCESS + 0.000000 + 0.000000 + 0.000000 + 100.000000 + + + CMYK Rot + CMYK + PROCESS + 0.000000 + 100.000000 + 100.000000 + 0.000000 + + + CMYK Gelb + CMYK + PROCESS + 0.000000 + 0.000000 + 100.000000 + 0.000000 + + + CMYK Grün + CMYK + PROCESS + 100.000000 + 0.000000 + 100.000000 + 0.000000 + + + CMYK Cyan + CMYK + PROCESS + 100.000000 + 0.000000 + 0.000000 + 0.000000 + + + CMYK Blau + CMYK + PROCESS + 100.000000 + 100.000000 + 0.000000 + 0.000000 + + + CMYK Magenta + CMYK + PROCESS + 0.000000 + 100.000000 + 0.000000 + 0.000000 + + + C=15 M=100 Y=90 K=10 + CMYK + PROCESS + 14.999998 + 100.000000 + 90.000000 + 10.000002 + + + C=0 M=90 Y=85 K=0 + CMYK + PROCESS + 0.000000 + 90.000000 + 85.000000 + 0.000000 + + + C=0 M=80 Y=95 K=0 + CMYK + PROCESS + 0.000000 + 80.000000 + 95.000000 + 0.000000 + + + C=0 M=50 Y=100 K=0 + CMYK + PROCESS + 0.000000 + 50.000000 + 100.000000 + 0.000000 + + + C=0 M=35 Y=85 K=0 + CMYK + PROCESS + 0.000000 + 35.000004 + 85.000000 + 0.000000 + + + C=5 M=0 Y=90 K=0 + CMYK + PROCESS + 5.000001 + 0.000000 + 90.000000 + 0.000000 + + + C=20 M=0 Y=100 K=0 + CMYK + PROCESS + 19.999998 + 0.000000 + 100.000000 + 0.000000 + + + C=50 M=0 Y=100 K=0 + CMYK + PROCESS + 50.000000 + 0.000000 + 100.000000 + 0.000000 + + + C=75 M=0 Y=100 K=0 + CMYK + PROCESS + 75.000000 + 0.000000 + 100.000000 + 0.000000 + + + C=85 M=10 Y=100 K=10 + CMYK + PROCESS + 85.000000 + 10.000002 + 100.000000 + 10.000002 + + + C=90 M=30 Y=95 K=30 + CMYK + PROCESS + 90.000000 + 30.000002 + 95.000000 + 30.000002 + + + C=75 M=0 Y=75 K=0 + CMYK + PROCESS + 75.000000 + 0.000000 + 75.000000 + 0.000000 + + + C=80 M=10 Y=45 K=0 + CMYK + PROCESS + 80.000000 + 10.000002 + 45.000000 + 0.000000 + + + C=70 M=15 Y=0 K=0 + CMYK + PROCESS + 70.000000 + 14.999998 + 0.000000 + 0.000000 + + + C=85 M=50 Y=0 K=0 + CMYK + PROCESS + 85.000000 + 50.000000 + 0.000000 + 0.000000 + + + C=100 M=95 Y=5 K=0 + CMYK + PROCESS + 100.000000 + 95.000000 + 5.000001 + 0.000000 + + + C=100 M=100 Y=25 K=25 + CMYK + PROCESS + 100.000000 + 100.000000 + 25.000000 + 25.000000 + + + C=75 M=100 Y=0 K=0 + CMYK + PROCESS + 75.000000 + 100.000000 + 0.000000 + 0.000000 + + + C=50 M=100 Y=0 K=0 + CMYK + PROCESS + 50.000000 + 100.000000 + 0.000000 + 0.000000 + + + C=35 M=100 Y=35 K=10 + CMYK + PROCESS + 35.000004 + 100.000000 + 35.000004 + 10.000002 + + + C=10 M=100 Y=50 K=0 + CMYK + PROCESS + 10.000002 + 100.000000 + 50.000000 + 0.000000 + + + C=0 M=95 Y=20 K=0 + CMYK + PROCESS + 0.000000 + 95.000000 + 19.999998 + 0.000000 + + + C=25 M=25 Y=40 K=0 + CMYK + PROCESS + 25.000000 + 25.000000 + 39.999996 + 0.000000 + + + C=40 M=45 Y=50 K=5 + CMYK + PROCESS + 39.999996 + 45.000000 + 50.000000 + 5.000001 + + + C=50 M=50 Y=60 K=25 + CMYK + PROCESS + 50.000000 + 50.000000 + 60.000004 + 25.000000 + + + C=55 M=60 Y=65 K=40 + CMYK + PROCESS + 55.000000 + 60.000004 + 65.000000 + 39.999996 + + + C=25 M=40 Y=65 K=0 + CMYK + PROCESS + 25.000000 + 39.999996 + 65.000000 + 0.000000 + + + C=30 M=50 Y=75 K=10 + CMYK + PROCESS + 30.000002 + 50.000000 + 75.000000 + 10.000002 + + + C=35 M=60 Y=80 K=25 + CMYK + PROCESS + 35.000004 + 60.000004 + 80.000000 + 25.000000 + + + C=40 M=65 Y=90 K=35 + CMYK + PROCESS + 39.999996 + 65.000000 + 90.000000 + 35.000004 + + + C=40 M=70 Y=100 K=50 + CMYK + PROCESS + 39.999996 + 70.000000 + 100.000000 + 50.000000 + + + C=50 M=70 Y=80 K=70 + CMYK + PROCESS + 50.000000 + 70.000000 + 80.000000 + 70.000000 + + + PANTONE 151 U + SPOT + 100.000000 + CMYK + 0.000000 + 48.000000 + 95.000000 + 0.000000 + + + + + + Grautöne + 1 + + + + C=0 M=0 Y=0 K=100 + CMYK + PROCESS + 0.000000 + 0.000000 + 0.000000 + 100.000000 + + + C=0 M=0 Y=0 K=90 + CMYK + PROCESS + 0.000000 + 0.000000 + 0.000000 + 89.999405 + + + C=0 M=0 Y=0 K=80 + CMYK + PROCESS + 0.000000 + 0.000000 + 0.000000 + 79.998795 + + + C=0 M=0 Y=0 K=70 + CMYK + PROCESS + 0.000000 + 0.000000 + 0.000000 + 69.999702 + + + C=0 M=0 Y=0 K=60 + CMYK + PROCESS + 0.000000 + 0.000000 + 0.000000 + 59.999104 + + + C=0 M=0 Y=0 K=50 + CMYK + PROCESS + 0.000000 + 0.000000 + 0.000000 + 50.000000 + + + C=0 M=0 Y=0 K=40 + CMYK + PROCESS + 0.000000 + 0.000000 + 0.000000 + 39.999401 + + + C=0 M=0 Y=0 K=30 + CMYK + PROCESS + 0.000000 + 0.000000 + 0.000000 + 29.998802 + + + C=0 M=0 Y=0 K=20 + CMYK + PROCESS + 0.000000 + 0.000000 + 0.000000 + 19.999701 + + + C=0 M=0 Y=0 K=10 + CMYK + PROCESS + 0.000000 + 0.000000 + 0.000000 + 9.999103 + + + C=0 M=0 Y=0 K=5 + CMYK + PROCESS + 0.000000 + 0.000000 + 0.000000 + 4.998803 + + + + + + Leuchtende Farben + 1 + + + + C=0 M=100 Y=100 K=0 + CMYK + PROCESS + 0.000000 + 100.000000 + 100.000000 + 0.000000 + + + C=0 M=75 Y=100 K=0 + CMYK + PROCESS + 0.000000 + 75.000000 + 100.000000 + 0.000000 + + + C=0 M=10 Y=95 K=0 + CMYK + PROCESS + 0.000000 + 10.000002 + 95.000000 + 0.000000 + + + C=85 M=10 Y=100 K=0 + CMYK + PROCESS + 85.000000 + 10.000002 + 100.000000 + 0.000000 + + + C=100 M=90 Y=0 K=0 + CMYK + PROCESS + 100.000000 + 90.000000 + 0.000000 + 0.000000 + + + C=60 M=90 Y=0 K=0 + CMYK + PROCESS + 60.000004 + 90.000000 + 0.003099 + 0.003099 + + + + + + + + + Adobe Photoshop for Windows -- Image Conversion Plug-in + + + 4 + Coated FOGRA39 (ISO 12647-2:2004) + + + + + + + + + + + + + + + + + + + + + + + + + +endstream endobj 3 0 obj <> endobj 5 0 obj <>/ProcSet[/PDF/ImageC]/XObject<>>>/Type/Page>> endobj 6 0 obj <>stream +q +660 0 0 400 0 0 cm +/Im0 Do +Q + +endstream endobj 8 0 obj <>/Filter/DCTDecode/Height 400/ImageName/ps7F12.jpg/Intent/RelativeColorimetric/Length 77183/Name/ps7F12.jpg/Subtype/Image/Type/XObject/Width 660>>stream +AdobedS +   +  + !"12ARVW +#$%&'()*3456789:BCDEFGHIJQSTUXYZabcdefghijqrstuvwxyz  u  +!1"89Vx2AWw$7BR#%&'()*3456:CDEFGHIJQSTUXYZabcdefghijqrstuvyz?_[yLYjz'`+mXcXJ8qVJj[ܖeYE^ +oͱjڛnEbMHUӏdfIT|’.\tSžE)Zʵh 3ģ؆'f'}-"N\W;$>S`ت >NmjjAb:=w'5#sFؖ5dQI3ܖ2>b[7_c*xOfE>sVhu&j%,]qɌك蔤W]M$nJ._55,"lXg!9fN"ML2E'RjEY/fMuM@7Kp_{;B,vyܒ:6eKP㣎-Cї;O,}J[Ey -B737=,4v_7lHD%!W[Jzs_?ƛ&{6M;fk+[bayGHWLޜD1Pɚ4q>suQn̈ovߢtMih _BױvO(;qXm@ٯK3z.>8Iiڿ]]`kjwVfo&`_cp-%%Ht'U`tLP6uVqr-A +YHrzvyk5PbDMec۾>=X_ɱ6KFk-3%|<\+|x.}g>0п_cjlӔqCnbjƮN+r5fߗo`ox[9F:mm]&fBAP/l5<N)Zx 7h{+_òbKu +8bs=?ɘμFxfF=]Si=OKȶչT\VǭRUc芛Um(7څͷ'#%TL=awILsx2ˆ`r3Y *Rq,r1lc>C cŌrLsg +ЧnB[;RNk16h':X"-\zٻƊWh$ĚLf(rJlgE\7]9H9j"<*"'2j|}P!q?d .G4 ",B{PSkz۶#(W:i֢ȇZZR)Ve&fZ1MX.2c( +\d$-?X&b |$s{1lL8)SH6qg $'d2+޷Z%IjՉ7"iGnӗ~Q7n_pvcp xYCߥ" Y6d9En̓V O"٪DAe4! Q@g3cg}k@7fw#rqF]xHoe2P9z v0̮nX%cC}16;Y"f1c<$AYϰG^F&JwQgL+e5sl2Lτy/lƪw1L`XI|]gV V.p\f0b3_{&MIڳS1%[rR?w܎Tew*#Ok%61uv+9&d^}|,c9 n{`v>!GZ9 H&anԝx|VzUө uԂիdPW6 11: (1kZCvA" "v\4QDM$.="i)qqc]u +e*묡eYSET91s6}6s =? ѿ_Pm$m^T@'Fq9[d6N5}LW/9%|(ʁ%myLWdȹ"0XɱMP|;İ_+"< 7z ~A -idݰU[(IhL풑7Hd"I( +`3NnMZc@巿>9[˦ZV{Kǿ L]e ++Sdb+^ʊ@,xK繏Bw))wUUJؾ9g!{"sI O|>}' +tdǠ51*i]utyjZX#cяvN>,VD]Z(IXF2WΧ|^=F䏯Y6cCA)=y +B)vT> -\-;ʺX;:T#d9%R)3 g,.6rbԆL6tO۶O ] +lgܲT`ɮK~o\}1dT5ARM"yǷ%Q%1PC @uu[->v$.\?]ٕ*kW%*nvUruչusW/Yy)QS|pUfm33q*J^s9:/&ӍZUr%Iӎy]| $i4,HY&iYezI$zW=rUޮUU߼򪨺.Ue:cP|6rc99~~I4SMTHI$ɌpRǰ)qc폀y[9GmCUJ;92GNW1j-Z+TEL}Hpn{VH(9=?h9pvth&3Y|)B7M +rTPW6COڙ<<^>qDEcWNN5ەJDzĤsv!]Eɂq^Lj2R%yS{n2x2jfIB(g[8e" x|9L7VJ،'ߚ]^|jIq4T1O@yY"oG9hYѝKell,r#WncBgt,P|ަ;E),DB>SG4Nn9bLxL hʺH/{b} [qx[dVFH-&ezETEidlETEszk07R/GD^r6m:tnxqUT"eclw]vكGO,F7]ۥl3,;M"s۸ +ن}hE#X4`,mF%4( DFːvďTErdSmDԩ0LZCD˂ÆlIc<Ǯ𻵍%W9w+x8l^?69%+6PAۥTjԹs-l"υ$_o`5hPI˺S.C! \B8k%_ G2NΑύϊ?=պ;uWW9z3$B<8Ra:Ld5B S dͪPhLe'Qg!SIT3֒8h*(óќjKUWi9ܞ1̰zruC"|XYzj/Yѭ U-'\!HϨc[O7}|=c乴Tfve *$l6I2;{^t2kWrb{Ƿ;ܴ :y QB6]LL<4b6hG~r)_)55޺^sa&1Ұ$ri佌S8r̍s|)r!CNF<^U OW#'QXJCYfrڿ3QArhcf2^1{]O^_M&<̌1U\MbDo%% rԻc^ԧ{Xɖz +QQQْkTlT ܯfjݥ Y$2YCX$lE&31 + _t$ fDerQk%$|"d2s(,;g*5'2 e6ᳲ@pxo);j0Lz8۷; xdxҒg!- [dEulQ˕e$R9QGԣ1R2d^6`ygN#vҊBc]k Az\丒ԹC{5VG2r^YofK .Hcc͒-ʫ+h2*'RRaX)0X/q{1B^vW.FVln yW$E$֍5򵮕VrΑDݻZ?L멛־8kCEOsOϔص:U (F-\(L|3q(9e7E.‹&IB%!9oNDs'S33g%ھ+,:bV`ptGRu&5klhb/S,|`^˫.ƜɖʨF$͈WEF*ACMS²3g07hj{c9uLg>f3 g+9 |519cQD +gؔT]?Ӹr㫹芽>*|ʯs\UqeJ*nWq]e),P1&d)O9sXY9 /fvr̓Ş,RQc`1cF}P颰Tm [~ +L=Jc2zj;v:تۚK6b[bM hcZm[Tx9ޥ ؑ,HM*۾*:jkgzʹT&KqcэwEŁG(+ ZTJxu}F!7ӷAT9Y>A2 ۬'h;KR}]ٴ>s{:꓋sfs.9ꫜy:Ǻ|U޹yOn}x{[9:ERxcGI=W߂m|֦hbQ&/6e GZnC(x$Ld,so@:jD!P;U'rAYl֕|ʚ 'b8"Hfs4pu1R!kHN;y:f4jʚ{guCXޕ}6K 2ejķX++VcEJ3Ty6񂰳l!(HMd [%WÔDžPdP̚?\b0n175t1qYT;YRe%"0ѣFL!]dPZN( 5;g]UufΙK;LM)?*^W/ QďP?*njJ /⟺ y\y$Vc#%HsP#qꝲlx d&9O|)"_(42gr+YB5PG@@Mɣh]l[M2O隴srv?P`_.;#Fqת9'5>gb Up Kɦ4™.s Hre6s)T͌){ջO)3g6|8,LI-LO0z<\)PCV6o?KKS'NLUX5ܕC.J5Ϟl~FEN}e^e,0Kɢ_4tZU_W#m>7!ta]! DSedw@W+C"T\$|u\ιM|lo9Slԉ,G*8*H,,̱ˢP6fv{msEt&3^VHږsY֕[5ĩrN#UJD]e=rgm)yIi;9 V̲4{H|*g.$)3ٺ'LjUǛ78h`JjSRz)V9r1.̒6p(˩p|6rd$͈*l^S^K@$Vp7|oxgt[_b.xG$R3o=Ur%S|Jl+1%#,7OǓc8L-ĺw]YTNm>C.ъ#|NYqc䨩3@r Dݧ2gIGImjvc?pHkَfS-,ܜu2`ܜNcm +W.J5Eb1@J#"4OǝÒՂDntbc\$HCw)Jf1髎"F*Lv|<=bClđBvmG'\Yod4>k1#tr^?3ʲ(:U>6{ƽ#㓂7G5s4x=q;ʋaR2D\de)B`|'>HC4ݕj +GhQCg&{K(wQR%++ˀtI}DFQhArmC{ +d\\| +t֭ifYgm")m9}Hvf(?*y6 :=u.;FmIx/j U)aO«XkNQUQdcV٤M>7|c8igsg) lbls`}z+$-z87 9\ȻI,c‹&{vH>I5Vbe-sYLNg9\ޞ$^n+W?4;5bS+IOJLTɲ7jr|>XD3@'cIJK0H4nNc’$ǰf;w~-fy''-q'~n c`G蹸{[Z)EGݽ"$K̏F9c "2!?*.=>)6 +[LGZc)=̔6}@Q9P| -GNԒn+T`F5ΎmʬjF:2fl&-Vw zuD,5u|2m^+r]a|| !3srriieN¦LȕJ6G&0w-RGDne[e/S4ExpWPmj9*v)`sⴾxs/ڹs9v=tδ(n%}y;%UӱӺ4ɭa>jHiJ*Lbөwh`)j\fh,/sX}!m\Dvi48Pn-.s9t;u<+$ |MDxտ_ɬyrfי:Rl .b䯞FSRixY,֭>>͹WIb_bĎ{{h惸˯;;"ԓttd}7K1WZWb.e3psccd\E N9 +dd(M#$"cE*)*d)J\;Dhl gAFW{n?R:adr[*oz&z.LIfx{bM!рFWa>U+(nE1HCr;ڄM2ګ9W&Tzl%UOJ\'.D1ݹ3&S1dڶMi`Ïm^).SAOK_c#W9y|dly ŗt^.xFb3h4=tR’՚\|Ll%1E"/d7OǂP-Ļ-]EU2bNjo>O.T֊|iȗS)spr Dݧ2h{ImecsߎWf/- ޼d14g6N%{emWx^5Őc@Ik5ǝ-cœe{nde\NB)^E,g+$$L|=Rlđ8jHuv]IK,flNY˗Evˑ%tKr:s@rtV"(ƢA(ZdTJDSnDE,yI`$cJi4TP +w< l|99#*YW9r ̾ѱ,b._>nB+x\2˩P9r~n&f-!5*'nxN\&U\1RO"<)"La4B(r Sզ0a][Imj|qy5=F[N!wϻsܯ{=C>\i2w B&|3)`[ ;c0,{1so)c X%9ˏ#D"]HeV'ˌ8j*6-$ [!GLg#T{u}d#k$zlՍ5lE 1&t֞G=g;gO1.C)ϔd8nC)<$) +Bڷ{)Mi~sEE.LBf,\&r\c0w5?#MZ?.lN͙íٟ>gZ姫[q7viIbKT}L:= gR~cZ(r̖nlyX2媦]\|>DI!" q#$(U۠_EV/_6M"D9L-,"tΖz/ GM,+M1tqj5+̯Z8ز#5ގyg +V%j": +2Hئf l*(ʊ*]ceuNs&fneu!$gnqYcM"`rTHI"2}@ѽs3+XϛNW&¦"f#FWq xB[ˑKR)34ȟ2ce`jsc{g>2 i9uS"O+c>^_LEťۅJ#9?~ǀ;! eΗ_{{[L5VM?bg^c'dsuF{p9JpLOj>a͚X0P.rxJj UQS"/eX탚=#'+yqĭLnRϞSg$魔'LdY.%+J_ cXvfV_K+֖CNŎz)ڎZkM4oF9Zz1d:MI(ve,WQ*L$˜3eב?vk&KW IvP:k g !1 rSκ OSzԾq꟞Y]PuЗUCǯ2?|v,y߸ޯU9s?o#r{?w'}gREM +xe +TUUaj2*V*FE 18ڈ5 bŔc6ǰdmb7H"H6lES.0TH! `1tSǏ$]8} ;O.NWT%pcUPɎ1l6s=`ֿ_1Y<&Rf1qyrnjIǥ%^:B&Aa(sޠg(ʨrgr=dتd'|Ŕ%ŁA\;1z[T~:VTR¯EBpc0a_fM yB91.rS+!PUF""*DD說As;9cÜ1scs=sc#ݤ[4:xYx]=V5YnꖅwG=\usu;l_.[.JX)O Gdp.Kf9w.Mקk*]W)aQmO$OKL?f3'7nc`.; +P6tS̴|u'cRV"TE83xfWnkr:Z-rULc_#}.=(XU=ӨIKc) I\JG-̹£\! ؓWz2gsVdĉQ<f^q4cd)Pп5hvǦ{Zd}vXt%mܪj`)"W"9tDF{Ϩ%3{B3JE|O̧7g/ܔݳky0be7sJ؇Vpxzdw,lca$/bbY"i摑C Lt,FGQ$F1Es֢j,hUS4L:(s`M21sg! 1g9ki&uU9I"EP"iLd9l! 6qs`aCgld{wJyOՅV$e )b9!Z> /O!?#f|2Swv" DI˧3'O1E4UÂu8 \3:XrO9r8h>1/s26}suq|&B89[FhNH|yɛ)ruf*.[:jA56%r2(+i^Gls5U^~."9T7l,TEeEUPSϳs~ l3SAS.L*|&d.=9bǷ&1]ϴ2ɻUꜾZrWMnF)ne:mEMq[pW`l+\'$؊wW',k\H5l\g*Xdza?S%wprv6̃vÌ }v#=urٶxRl^-4bP4: N'_z;^=VG(k%c⤽*}M%fQy #\ M׼7Io:­2_Ǫ%` +x, п_ tsLvt`h&GfBI{ۀow+|s9d%17īԌOڗ8~^7ߦ5U,* R^"+xL(L%:K1?3`rۀܧ2g|P'cTrGAu4{ջ?JU܏*=Q2ӦC`lwĩRiw{à=.>%&GvD{%ʰ ='ɼAbODtѿ_]Kh YhLjj5K#9V~N`֦紬IUl1TsQN+x4m4BCDŽ Vq>cE\Q"IM9+v~,Fˑ2K9"2S&lgI6Ow b2US#o'BJhؒ"oD|3$n㦯k+a [3gܰzOn8$g!K.Em$ɜ%J޴\\Y +ʉ(CϮf:rM)fn nҴG፹C0ưc`j.Qa\{88WlObyIa)~M; Ҧd"qtǴ~"kB!WhR;E׳ԌNȳDUt2gU]Һ2s8rHmx~|t#Tⳃ镭p(>̢\O2xχ^2d7yzviZbd| gK(g3XVff|>2巄.K(t45m/B +MVj|>YXUFțj9=-]ZTEݸsPq~)X=s:OÌ͖:S%s6qf_(RiVkI_M3g d,7o2bc92uKV:*ХuҭJo UVMqDIjٻ&ٴHڴA&͐OneI/4R`R`+.ʧ]˥pe3Qe9USN1͟s'?\mlfvivwō]gk{o#,M;ZSOPIeb9WVhZl<ˢS3) clݬ##"8)cW)F6}pM*k)ݙ )1>px8U(j !*κy;lN]+.3]mU#CeSsV|}{qKýe؏>fOd0Xe˞oV#]T;+2Ax{dB|Wi64^q>MDqnxell ;tҿ_egKRX l8vʛ@Z~G{r5I(w +I4jrC̚?jQ}|%pc1e`i,9ȪL4Nҕ*T}U3>Y⋌}{$ċI\`.hmYzI\R2:OQa F%~ ^G7l ^v*9C,ccBjZ㳟^EͶ.𢱏wb|QXt9S)Z=N~FrL) VXϳG*TP9rS[L?PLgPclnKXӝz(מ9qnŔdMFƫɰ_텙?l + ?sy)y;zs(dH=}3D:l_WDm/QlĎa+ %7qi*;Ӣ#\ww4]2x=z"UI#?ϭɪѮ119M͵IKQLggX2tdY:Qvq}$sݰsɊobyO52=2=z,Ye{I#ʪ9UwYe\,:ˮYe 'QEn9sd1s9I H"EȒI&\4L"i킐 +Rc{:K]d}/:ԟrQ¨ ZNNռΟw;J-}\W)/Ͽ߹ӰÃyfa8n>8 `sa^CW],~߃%?`&PDʷhz&&½GB.dz<Q#;%D^$zRPwV&cšSc)*RBY.jTP,ӉǫڊFMdfN$N QN?i9ػNLfU݅$LxfY4{P+X#mkk +7Ncs,!oe%]OYvǷ8W-kXֱkƣZ֢5kSsZ֦F"""&NnXܥ)K)K.1lcdz==dzl91Ɍcg9ɳssۜۜr<ӿ_-Ӯ󶴮bXu ľNj>o{]ruF[!/_q]PosgQJEiLsgR[Bz932ެ$*bq;$sH|{E}ɳKѳevs!o|twtצd12O飑fH܎ctYx+_ IR=pSɛb[a\%oPfg~1b2P|ga%_ǭ$lHw;]涥œNWFL= kW=ZJVeDr5c&ۂzI 71+f),1$bE6rI,NRqɷօA\.!)pL)E}֓W.^6`lL9.N`3$>QDM;iz,:^|,VǃފǚQTj$,ȩ®oS;5ΣȮQw_vRK7+DB|d$)ń۷qٺjѤՌk!8i2g4&x4acr|%lKꮉU\c0rn1{gKG͛X2D^>r6u9rQAuU9&;LlcJ@a4LJj o# r+bN>1i;}TrF9qWN<ϽO_֑YDXko5#,$ϒb¶a÷x S9gRKxY*jFCj1٤iywrԫ|ej3]g(.v_#hvImwQɾ1-Gű~g(.v_!ۧcW}%}C<[gئrOemZ~v5w[g>1-Gű~g(.v_!ۧcW}%}C<[gkdپ;+!&)VJ +JvOwZ*f nG5ѹٛF7Eup6M64d 2Yݭt"')j;`3ds +渶aTpt*r:fዄڲuUHbw % 1e s-6F̭ǽ85g{'ףnvXh VȇO+ǹu ʹ{L"3Q1V)>1d1~Ƀc>d#w4ʵٺxbϋdTymcۢMH.q6 %EN4WhF尕fYq94|=5W*ܨb5ƶG8n)(Fh>ȳ>VYLcs&G18/|JRÚvkn>MtG)'%{Fi=,aXM͜1@UND]7z/dᴮ l?P0`U9,>}Y I,ΒNpZvة`]b]v":|bZc7;P]쿭CCOƮKl%x?z@Lܟ۽>;tj虜ϻ|bZc7;P]쿭CCOƮKl%x?z@qlCq5ii-!ڂ1ʾT +cDǕ)cŜ$ !*$^l~ҹ;i7Cim^Y:.-]R$[8[JըBʰ6yӝ<?Q-E'X|*IT˵ɵ%+tGfZydnTe>EcJL}nHDZ۝#^WNnuvAA\2|B8+ 7d{(9 Lτ9 =W`BLbY?\fcHv.7tAr&Hs_,rg|-k\)atfgSךz3[O&Bj[mށU4adb_Uk %A +$ܤ[dG&S;3v˴vtrVT./kU׺ᄣ);-^^fn$X#,Vګ9U%W[ cɅRˏag{lz|.Nz#k6͜r[tS1WMUU)&8Iن˄%1"d͆mPfCPQ;0Fbʨ\ "@Q=k_gF_Hp74ި-wP-:͖Ռk~XZ7AbI`N|}zǭEs`gGoc#դQo|#΢R MUdd¾o5AmZHv0u+4z_Vh$N|hUPһ9{Ub\"sWsEEEEEMݸs6Jld.rS Sc=>gg>̉/)l` Sc)gqq3n3fq@ :SSk.[߃OX}+6?f">]v9'hc᥾]?;>͏#پ;HO]| 'ioW~?`ϲco5>,عK ̬="FiȭUDr2Gpd$tr6%r_a\ >{}a䢥!b5SI.:M%cø}M45ʼn^RMTYuS&:(sd1V;cts ٷnFL$D5l0DE"cM4Ɍ.?K|9O@{33Y^ݬhms-Q3wu1d{T+Cdw#tej:8 jGVrn_u:s3lR)3{JdX[2FMOJ Zh^+chgۄdQ>o׎x伬 +BxpeagDJ5O[g;ez#zL.j̞΅2)-RD[}E5W{ڧNg`GQKd]_]ԘYUBi$U2X{p` +5ӊ27 d΢),mb&J|j:Q +,T<7Pɻ'9J6Xp)"2%Ğ-КPlXimXRN{yX9Ցs^xWܖkY-2m TU:^gNUUh,`l,9n?j\ƨbዔLx.u\now#%4+2SKfMÿYd~2Ov6^m+B: .< ӶyǓq?UG A842K|?ts>3Dj + +5r<*̓M%,L|ጃd^R(w+*}fǻJq_>Ua~?-J;,Vl{{~;5ϽU{>?-J;,Vl{{~;5ϽU{>?-J;,-voeSDd3٨bzkuarJ|R@;AJ7wW||iu,bXC?f,g'lK͠t.3Mk=I`R\nŇq؜N;s[dc­cZKw^VPaiٺ%\c_,l$A&HUIL"rp1)KmvSٺ-eW]Z(U$c YlT;t&2bW&s1CV=k]{}xiN}8Ts9kgsvƺE{Ǖ&T"UVc)1t36rb! +Uc'1r1s8ff|&{{üvb2X) |)l]Eziݫk-ֳ֙;.^qq؞JZ{%ZW+)R lc|kbfIe}nfƴtۗN:3F+.B2:216Jѣ4)LʎyA늼enɳvZ6+"<"%*o&0g.]ĮNsIoyWrSһXc5[Vz5E\ZUwuǹe2񜶡EE&ݏaMU `%; yF߲mHJlBxUόqVӷ5Us=@Qɖ}/S9y/{cL$u ˞җYh[evUDrT,Eo -]ȜJos]ur $E&k9YzyT7|3ޮbqH폒ɳìᖍULS˜cH؟2lqYĩ>TI+ͫeqU\oDG9<2](XOv\rȉ:1\^c^[Ő`Olg|x\]P az ϊu9GΣ\w32 |! Ժ<5K3h7 BK]{feySt#I=8II3*Y9Aߺx_ď~Vϰ4$1hBZ,[{[eF{Ey^JBS=quW~Bƞe&n,ebǑؖ{R,MlJƶ&|U%9&X ٢^/ O ErN)p?frÒGuY?z`i ?;[w o,GVkErNtG}wQG?3~ҵݥjZ_9׳ڡs+&y}k.ϲsZV:ו!#+}t6M|-*s;b)/[p̑_2vdpỖ$IsY˭JKq n#2!Zļe$}x%MneO*C7J 0-dնݱi 7Ա6􎎣GbGuּ^}q;Zݚ mtu NyU4PPb!$6Y.y)/Plĭ\HUkɖnl3Q=uekô[9LJ(Kk ә;B/3k[g;J)^iDs\ݽsUW~V*F +NB]OGȱrO-G2.Ooc \K˜8ȝ&1eݢ6I{1tFS#NhKPG2\3ٝ"$:2bs|T]{gLf⩊R乔`ٛ|`*M;~rb7) +c2GDjQu^np\ewt̖`nȲNBۙlɲׯԗEZእ:Ew769d1V.wDGO1L]I=> dD$٫t]-SfFM{?8AyWO& [dz&LyYo$YS.8e3Sa5vҬm/NF}6L$19OZd:c%5DE3Tz7#Yo6-~W UP-O &ء!]*|/p|y[WH8LϘƴϜ~EVAMsVlc&L&(E0W|j}ze\T%fݙۛ~!4ϖwL~b$cUvGl-rVկ,Ud8{_f_W+9UftUTXpM#b@Dө-S^YXEAIdm6&&GTg%*e2{3͂g SS8ˈq3^s?0l:;9^~\8?ʻGoġ~8d?~#x.B36%w s3߻vFժNEF+wADʅ*Znq1-XaP1$`6fLbժxM<ɔUSʋE99h矝MXg$)+9p|) $ETHI"2B}ӿ_|'0Yj̹crtH5vk֚X­w rSѓe3!$GJwG, WHÜYN9{=G &Azl5Y. 5c8$dPw/h^.vKQ^MsO4LG )WES)\%ua͉/Ҳ|R~9r$.==+IxXVTz.i?tH"%%H*~ +ɨ1*:hNacM$D8[죆*&)rOUrا"Ex%:8_a?{33gw.0HM-ݚgf?At?G>=3#a4c;^_w.0Hǿ@_l>g#nDV?f^q9sk6Ci7dK:~Y =֣Ya̎.q-ΖyuK[GUhGd$xջvhD3Y*b#u UR>Pq%Q[%Fp&Mw?v[@!MR"_!HtTZ?$/@V:7ReW2o%YUsF1}r-eM8aVWLjVE:gfy0I4V5z6bՙiw +Ϗuz j9 mkP*ܽrD6 +5P#>l~9Kl)kVIj\2ΓX,c^l't+UUQ7DCqc9sǷ9~ ccKsc|>cs07y;rھr8dvy{'tW-޵Gj֓+npY,l3k,6|FqE'*%lgPE9:U>E9)%2uՑ#ŸKA֌ݰzrLhh%]l-;&'AHgI,|%L̴C\X9(TΒGosj݇-sfY$zȍm:@DjA6fml+]\8t\EP>"m۽Ne|ygp$t6["R ٺxE2wN8Կ_ /|u UJY*uT[*w]ݻq鿎lvrlYȴS8ʍ_EcN(s;w'\sLpW~d~DZ{8}lOZmX;s˘}-ZcUV9)QfTz+UUSv>e!HeLWQ؆ +bg9&JVi+9Ks#tˡ,S`3iGc(ty`{g;qտ_ֿ_׿_п_ѿ3G}]8׺7^Z]⮭ժЉ *}Sos%7Mΐk7¸QCP6㎗;#dծhn@ϴ-Du5Hv!ЎOfJQtPr}s9 nzWO"RH8ʲQ\ꋶGG?ɀ~\j\ּqdl׍shy=hY]:)|,WC*::n@2wrߛ\WnzR;^_1C\, HBYf$ʵ/Rw qO,{{% +W\ oZSܧi*>3I\v4"?fn=M%a6e$;ă(]*9rw,Y8RP"^3_wNpC;vomVj̼Ydi2Xm{)f#Øޥ o \cŃ +l$>' uv#y3wƋ퍃_RfSVľmpaȰM s'IX^ҿ. EƮ}5o Yq\@l|!Up}t|jÊPKF⤧gf_5bNZZIn>69K|AF"I&sng֧tY+ U`3wK*j'c߫wNx,a)ڐ8ޓ}FxK+x5mDf{I@ߵg}· NbǾe+`@x"IQuP$2I$ɃE9BɌls` C ת>a16u]j>a ޫ;$U^W֚gfcG0JuDC{',8u=5pr>Ocj"Ic)`fJ7[W9WE/ӗX=.fw1by3fv͆E7DYw r$)*ʚe1C'uߔ;jJ$׍Qgɔp&{RR4ZU3)6Ȩ-><l/߱4ng?66vdz؇U +ʧIXAˇL 6jd.mIC ,?èW=/-)m XlkK֘I_)Y6vėeƥe;5^Jϰ}N:濛, f,qš"`X.kF*u=)jfT;/4z*,d*$ߵT5ѣ5ZE5Nן9V,b^)&`)L`< vA|¨=#^Ϧ=cMP ;#X64tW+e*QӨ=lET$rϢ/TT6"xu&%6F0mrfaVk*lIL.&*xU8*+*D®&h 4߮1O1~3z?}^iNڗ7'e׺U[YL6׶-rIF@ץ#pg*0\1ۘ):p9.8-QMej.5e s:YXtVݪl0'oYǶYM1f܆Uç" {EYB$ 1K=W[6n(h#h]Waܤԣڰ`3"HC1@fމOP^;{[;kx:i/ JZ-yMSƉRp+l=yyԷfٵ9&¢OHtDs{b%!fݑ7L$:L:j*9qgn̲? `3g897Ϛ[Ku2|H\ Cx}w*Y8ly_pR7p ߝN%V ;Z!i)hQm#sqe~<嗽Փ|r*&]""&׷Qr뭡JkRjL=hYXGF?XQjϫ[Q\MrFL53׹+@Q=+25:CY9k|ս'#u68FZIR6eiS8oZn3g$ooWu\oTyK^yfd^ejSG`yR;',p6ez(kxi_InnN\0t +ƥXJ-Oz)]eY,Dz3عi[Lmɀэ5)t9]Mےc3 Lv쯥RU(i +r +4ki*V*auJS +Li;XnlRW>sĆq0QF9۫koJ$$$"mjBW'2+ˀ r7FqǪ/pݙCYصݻDޠ e+Ťex0ā&峔ESJ D=#xO͎^d.`h_ *UYc׳+#*t8Vs^џּo5桪ju5ШuK_qamG׵13ٷpyJpЌ҂r}Q9 :Sc[z)  [ئ]HFN ͺEFR,ޡ/F5Z>|淜bV:;VN:z»ÄYvMP(KYotaqb7:{; VllyTlz8kFղ>G,pe"!),V+gD䛖FS u8ҫi#h]Yb#D]5ۣ sRqӌXݯ+WW-V'cp[@9i)6 pߊ`Qk\Ɖ:ѢsV+7Pc ܠH2V&#M&cC<\${#Nh:~]Gfl}ɨlGL63u.>mb Z\M~ʞ[ΰB̻A%5^J, (lbak;kHB*$&MX5]2vI}$vT[0۫w {;]V[qSҫuɲ5uJ;}6rSMDfr,/:[Ftqk:YQk=Y4bWD:ǟ`ͱM*ygwn^8#iq]J!plޤtGkm8rfD6IBE5v&TLȍ5 o"P (m{Ccm+ok[\:}m,>e%~ n052U̯TN:2d"5srW{M)Fyb\'%Z.XPrVGldm t"N;T3cRQncj['ƺ;?u"u֭כ +M[ߕv{m)PZ+k[w^N$Vu7ٚbصy~Kk)ݪ%mTI/hשEG[t6ig856Կ. EƮ.=0nSrsHu.M/j֖_ ɨS!3cb8Yެ6=MȐWք\<4Cޛyr۷qm=+(qВ[Oa[v 4{\1ymqwÅ4QU[icj57ATJpBM#1ЉlEfDMoFDdبE?*E.pB 8xwnYӧK*˗ +w.s(묡,cC9l Y]:t^lpT[*G*$nLQJr[ g$0a+T˒ͩ7Q:ɖ@} ]YپMUfiJ_,B4$q1 X$MjNʵt"ۨXCTĎHrٔJvFA`M9J|M,w`6 3r'1$k|vSHac\>4r +aǙ=8)|e:+fc5 +{'ҭ%e7B=R5 +xJ\J\yFz)|E-j['+]l; S#A`r)/VQb+QQ$ɌCj`t@tp裕px_nUTꜭJLhNl"ժn3EI"JB M\vPz.5Frw -6R.\2B;W40wL4筈˪$:ELj +[!=g/v(t8ɩ淳z cպcIl)KQf,dyiH$vnѷ1I,<m.IXs&[v(nF7n'FjacOxrѽAU#0cpv ~.xtfˏIosN_^(ќVUNjMn&뺺y-+Cm;TwR3[M؟*}=wj';]MVRN=@t }Ez{aw-g$%mk5eg$ig֙H95vE nR*~u1rDŽVjqŦSl٠ޢgR}Sf?֣3 ";KV@j(NzRyKjh܉]`J`VDJOlNL3sifH޶&+uJ}g_S6qsK+P5BYp^2 KCGYlNUyQ)d+ƭjl_Vb-'hKi!tXD̄Ur1*"W6ڮz}#HΩӋ^Shvʞ>TﵤleWol*oahGRCSgf+g' -xۯ~d箁1:tuE)+ +f׺ivɵXw6]>c]ŔJ~_Gq} EtWILMLW*8i[?M=z|45UrV}fr4CR5Ӷ=j39 iGTy z"DBښŽaYhl>)iW .Qƫk"*̌čMzR/$YFǸhyQ7qv$r#ǝMR:̽cZꙝLW)5j +Q I7zz.GcYXlijm^>1tB|N_U,pFn=,&W8mWi Y<*^lZT +'&Ns˞i<4r289ӘYSw#wuh0I7o apLi|(&3&դᦔPe]ȍw.Q&K)!ՉeI24S6ke)1$VAđZym[2jmw)h=jŋWN1flӑַu/o(ۮX|.Jl`jxUku#ݥ*hm3wM֖kS\ Y*Y*ZN.WR -?L~q9҆ulZa̱N!d3#+"wG:ߊXǀ |KԷ]T7S|e_)ڞMģ2XTkق#v+Lfgaϕ?E=MF.b>ի;vڴ^sI:I˨ +ɦL6N3be##2UVWPUiмfZnhݵYR]XZlt2W*f_&?$13>T~^S'u>g\.bj2gEŪh&*M6o䎲F}6geGbɡ+I֏>3æHUTD#]:EJї>>X 8JSش|=A&IF2 +' ,3A'"fer:uzC}IlUbnu b- %wU[.kF)TQwQQBEuZ]ˇt&s{,FrvL Hw +8AL e*`Zw:R[[-t+i9mWC⣯Rg \7ʵM2M%_0 ׿_п_ѿ_ť8Ji⾍؛ݞ$hp.$EO =^EG*3MќG4uJgoi8kԃȚ<|1FaăffåY'%C>o{@@ҿ_% >'@!9d|؍>|5n"$g3jV XITxY1P-N5U9Pt02._Q}+n&v9s:כzac:a+\y6] N~rey cLI3wpW|I6]MIɟir9D7.OLgVZEOXxY&#E0sG{@(eIOt ߗ rRWW ;Szi78rzj57AT@K'Yt~nP(,Aa;n0N߮3GƟFk:rdK95>dqIl(T12$, 5>1982|Iu]zck&]XSbiU?]'"LTSSP\L<61RR<׬#$$G,W"gMU:G9 %äRWrP+} 8*Uj7Nd"2bGLRuXT1d +Ԁ|oGhNm0&uñ O"dN4=W.]5|,;c#u_H9Ef^C"?SvsrT\yh֧Z :V989`ӿ0RsLaؤgd$$=4 gOv2Bɰ;kInZQ6ݖ勒i9fRܙb+Z{5]ui$QAu D!g 筫G6v-jJ(>=~˷"+(SHnD|9|r ª}#ut߫E6ɔbMHImM[aM9ǪE>&BFM@?x{}Q޶ZIXiu6+deQ"Ǽ;G +aiDR8 oGWNV^J񪵵|^FR kd֒k-xu &aZkLe%F=Dٝۅ2Dr"N)w[ZbY딺|,oիU}/?bH7bN)Y7mjLKe1\'ŭw97a5/9fj:lSTy[ĴD,o*ve"9Ԗ'џ蛼: -Ilۼ g Nxyi+M9 Ka]*ITEQo +ja<:kMjvۑ 'T)҈Qu#\FBIKRg,k*-kMr*Ťu5Es19&}J볷@Ν) HUTe^Yr, #=bioM[Ǻ۶maZ%jy.˒Fy"qzj}}VdpQVy~&ssseK6􃗋\VNA^Ē3 ^{ˎ2mi ńl;jmU!iv]}fSlӀչIűRCW5:{<[ylhAO sϠgs]M.uZ.j(ug6yF"M :UyKq#7v)7'ez3E1Zyxg #S]78uNֹɰtLd%*eJݯ5聴?g6v4yݔxGXl֑ߋtm&9R?hK"/'kcDګU`I!uOp׹5SJ1NEVMfA5Faj`nb,b%GLNr xNqB]mROL]y(`Re4 :9J#3Ɖr{=o([nA-sxk $4M\QEc0s~)sv^7ӫON/%xZ{>/kWV)l5QIr!$;xA|@\gATɪ+/Y*6t[ffm=;L83bL45?1=)>SW,,;fֱ_U.%[/p$J1GU { QB}߱J;3Iq*\@q#7b{DFӉmVM]x-'R!Kū-fIa9sYh9@}}=m|4Ku>RSbC[)RI\K7IbۺVd,VEjjIFYz7jpPNȇԍ+.=&OdJf<[kk*LrS~'N~Čsۇo*Ұ4V{HVj׸ht .٬YY`geLq58E VWjӍfk ;*N̡ .)D]4~ ;[9]Dl%/o>57Ê OSt?+@T~eH߆UzUu{]sh4;7VJS+۩UhDWEwh$YEHᚅxuۀ K4W=^zK6Kk#_GzlT˶0V%Bqvdi>ǒkbwcHHSf! 5tthw}!ҙQC&EH?R-ZRY^dR*Nb2r@gUmBzbi̵U &nU"䢤9b* *!MtAu.^gܮuR8V$fݾ˳q4K,|FI?R5a2aGFk9"E\Bkrf <뺝JGkpSpe !n圄J(YY,(C35I-$RwO|kk2XE[)Vat- eT9L9f?KnsN<~^F#kgR,zo +ă9h5+̮@Xpߚ֢۲֥n6lmIy~1mX+f/~iSux}WIWtpђC˚O= bc+VKk0̔lR9 iX+ vη/$:`+R*@\Y +%2EqGO"QZǎ'Kċڢ7WP- ;3 +w\ț9N-KcTEF^j_/!v*m6p[3g+Z@`g"p9W; v=18l)[a)Ln]VNC%]ݣג2koUMkZ4͍a͠H:^ڙ3h}eyk{S+XGeCYs g✓8J:U8J&q݀Ȟ&aqWf;*|%N'32闺h(KrxхQnP:P pkR׈:{Lr:L6źKSc)Eضc-_Kԍ"-6=wxCpe=Ȟ܉um;ҋW%^"GD QövG2/蹫4,,oA1Nzl9HڨgھCSB`YCgK|d"YrM\[٭%ɬ ȇVyJ(YR*Qy6ZU',`a6* <zϊzǩη\{?amndSRYɝuf+ lJ 9#j[(]aTHv)7x_@v~u9.07*": + )dXnKf12l(^\S@Կ.%iFS"o1kDlcXnIv{9fS "힗,ǮsڎL6&M + }vɖOtKUJ_YIpTntU?/!]jpP՛ch$*BACT,Tس*EeD;8@X?6 1keZŝ}IORSF@)N ]F MnS*]],E/ӗX=/u_OsKG4OE+H@^FRvgwd гyY' j ?eYQq D}+Π˃U8j;Qmc+kOT5%RVrF6y*[ v=v2xQsDJ4Z_gOZmb;45ʮ24tfXUo,ˡ&.Ꞗ2c alg:(i>Q/?=5o Yq\z&\sXޕ[$HPI9uK j, +i&u1@ÏK6~&-78~ yEpzQ]jwoM>#܂=eNKQ*5jq3M^ħlXgddڄؖvJ"jR3VO:\޻Pl wNƺX46]keVY[G3d͖F-I {KRo˸j}qiM6?\7RR[w pܖdavfdpW[cin7/`<۪ lWj:Xlu-DTʥY#`""ř4dJJhuwugq;܎Wo.ȭr@r]2&mr|7{[?"݊o"LRnѲI iuH>V8:u']cuRDՖ'[>Jʛ[jx&^zrَ$=TQvd\lSl䵚jYl MJUwrNxΞp +9=.exՃHk69ڟ/hS' 5)- 0TNa݌3H<$ f +\c/JrZPbv5{uR"36 E3d_f-ٛԚEEl&dK  AT/<8@տ,} g[p}.d'3# >~ܜZ(l%Y%]m})@GSt6;K*E5__6Rmbf#GV18HbKl:kzG5}ܦz˨_k`kNThYX])r^k)kM c*j] ٹH9HpM^w\uJ}MKH8U8w-Վe1w%IbdݟΐiﯬZp#Nq)`W"1HMڔbؾ YӷdjWCmrjSojMV)ԤԌ< +dLc{5,͢j3k֖w_Wˋ6t +cgVԂkqZnGYاe:907'9!8ǿF*kzlf32-:·ޤJ =$/k_}Cxqq>Í@S 93ю"ܡ鱫xEEKrm;Կ(YH:DA?&j+\oF CIX#X>X7jW71GHSrUVgTu[SX3]$DY5]>peTQH:O'P"s/ MWʽu!5rnPeC۫-* ;jĐp&R2L3fXwޮr.rsM~Tʍ!-:rs +V/ uQ*i&-\>"l` +> q\U\i/@n_-Oɯ86:R;̳69?RmqH֤)r$se5Ld}G\XkIyvyi6|m“rRtuyxM +`)@7l걡e$e)y0k,KEm/9A4Nؽ}4F,Q:A]7Z׏:A$n}Z3KLMS+QL"G\!JR[2`NޚG +\/͒}'P +vSg-~tɭ;ۧͩ/G<=Q5ө[8Y}R.*_,e}(t7%m9bտQim'˺)=PILXݷ!ȖR8"^]޸lؓS蘳9{sX!E;VE9Zivfվ$} #IGrpC&V?Λݬj +/.%\y+$ɋ8 +^~.1y wץ=kg$5CH5|U}s'ki22 ,Z#GHGAQH ֿb+? +8w*UԏK~ݤNz݉_^mF)5KrŶfw YcyDY_=0<(Pݻyn+\hp*EV:~iM U?q HeAH'֢]SWu>Mmv +Șs'k75tW5DRlXP yp'jl1t6Hx ]U-8lTѶ}vTK-5.UőYbB.CۖҎo6nƝfuqVٛ-xI/-jTaR?"KJ +Iۤ>:9MO; +Sj۵y&r'eդ9Q J@R?ylj6'1R)%&]J1 0t6w+saO /dzvqz~.<{Tjfeq?R}LRFBR8udq.}FuWq{JwrGʝ2_ {B^ձB^⨺x$Upk~xrCX#Џi~c-L+Y0g$5H9gI2ZBBBZJ-=xP犜x*3]R[ޛjPvŌv3~3h@"NjvyG&E͝BN4lG}w ,(g8Tw=Ebd +*حftKWj𨿞\v6z7 q]c_JuГx9/;b&F]!@T"oIK[OS[k؞<7az.4e{k\2rɈЭ++Ld{!/Oߕ\վ'^|rWm^z>>K Z?rnWR{&i܍v+ әV+bP!o`_NE̸f+>xf-F$$38=Ql&i<$6ю,2γckpS0dB v7^)~ꖯVmw}74~]{~*wxt!c!BQHɫ /?))"0zuYS4nKLD캛Yj5^ɚH鸛I׶T[g̙?~ X7HZa)g 'G.DkK'~anyJ4]S27ɨ5yRUd{#Rp >OF/]OG ^]Lt6K:f.vXT#I$^^`z)iE/;5zbڴoUS{YvFz͇z%v]{iAD6(&y 63!H8.X[} o`iUn)9qJnn2촛%NXܠv+(@8oSξ'sߘ|wEܐNR4,$- UF:h[+-xsV:!vWhuo-z]DҕYIexlm+e%ڒakZtK7RO*Sc}8ƬgÄ[u33dՑIxk%xY2,eJeRI.ȢwP>} |Kܕ_s3k +.%XU7є3.e=~L$|bǰd"<k OgP,&g:g9)^IJo|r 4[@sc D`.7!r&jL;[B`ZXIMecQFIEdkd]=Fzp=Oqכֿ"%yxqwaH4S 8L^p80RsQM4׮d/CO}R$םƃ+Sҷ&qvFћj 4ޕt5_sJ +Vu2zrarno›ƽǼVBW=,Ud}G/f'eї #$kP+~'6xޠornqc𖉸{TWyǫ"G IU5­\@o"쐗.Ak}fA9jݯrl%~QE)(I۴LI:I)&\SY$P=":lޓܽ6k"b%zՊȫbk)w_H4dcxu~B96g 1c/q-6^gW5§dm)vPie̕H-cJȽ]f5Ԅw]hU3"o|tq{CgWYVULL,ckךBڻ[-μUa@Ƕ=6LWz{˒ZxY$\)U/ UB(zm3S~zs 3ή%49#-D$e\aH{kex.KJB@8 :[zGr/bIl,o15~Dj3R]vkbQ[9gViP/kS5gN׃@l~>:mrXWJ A*fWtO6/sAvWzvIflPϞNڔ7sߨ۬X3XN*hL-gxhRZmt5fsjCGצ+VƸvzJw٧W<˃;ڭ3Үnd%;|$ +i:vsa ꜝۏjY5fwqw/o@5~&hv~:|W\ZmWjIYYwrh{$?:+Yk\´a ђWˆQF(v;^h0؛sS-U)21"x"`cWJ`ћNpKjy+5VRI)M}.y¥|}3JSkZ홻;Y [i籏YFu#ظU/Z*EڼfgML7pȪ*&r0^:OK斊R]u9YWmZ땉M:ٚ1OZ`; +weǢLKEd>m7 ɍ\rGFVq}5|k{!9kkOǺt[wFc]2Yˌı$~GJ:=ֻmPIxp²y$4'bg؝ Z0u\]㠦W{ճ'z^(MWV LEk$SM3{m?jͤR2hH9ln?ѿ_ҿ_._z8w(g=j +R_5y)qk4_fbQ:s}]wGh*U;mheog*D=K} 3,D̼k՘[—(ps9Rʞx5i5ߺZ\֫6%]YEJI FdRI_ \c$0ʎ:)Wg‘U06 .ڷlhJ5,"qhIeN=s3tfzVrW[HBE^]>ڸeg(cPs&(J'4ITӺҤ3K]JZlOlDrf.Vh$a%Tld%?נzas#nyk ^쵖v8E+E$BIEWMKVm*rsW +3uz祉yZ];Mo]/}*y` `RwEۘW aPR Z7`{#N7+魺J!X싃Z1_.M] FrF?p$"9VOiՊ¦Į$n&t5~RdtY4+vԖwK93|75{Ez)Vس]ncd:tHA3e;淾3h_wYh5n1WU1+)Y9cZ! y$܀@X3nJx2;:yXO- ݁\{8}vL]27cIkvpV9WG;6pV*-_*0\ Ⱥ/O +k]83=U+۪MvpZ)2$馉Rg,ܝj1Zfn!sxWc'"g oYY3{BR9~[ŀ͵o} ќ><n^5mmyFד/FЏF7=uG,wR1+\T(9U*w6XfZ ^JKl3!ժ2YnE 9mwEhĔ ^iaŎRR٥hg9d!X "xn1rSO#8ǝ$ +SGmM}orRAuvE2D:3HC\ zpR-4U-orkKx-E\BH8n!,sO=/&{$ϡM~| +`gj`-jړpnT:ru޹bx&I׽Lt[,N.~ >~ +r35 +b1C%9\1L\L\81sgl#! Z%ȹXcdB:Ar8I7 Q5Y2*rog28}<&2˱a`{gTj46*FmbQw8iUe/_kD]1yI+Hn7q;Ng$Pi큱"pMnZ_Du,f?dP~ËC|gz2.mwtmF.@Gηʍ\aq^pDuK0:%ԓXǰ8J]'QJ.N9&RURpGDHȔ6L `2Ú܉p^wZnrOu?Z vh1aVn᫢Q#ȺHtN@GӏGE^-i7J.$}UC,(276Nɢ!P'Vl5ls|WMBFFxeBggQǬ3OTb-GO6bųE6mQ˧nT[le.Ȓ(C*i608jmSCZ`V-PSlp։Ĥ8V#ZM9 &EW EBd}PME/K=Y *,CSud4oox̭ź:w->Ǝ× FKMs|Ʒ4ei| 7'Nwn߶3^\AHA+V+'*Zq I9G9j=TEY$ϭMKF>kT3Urw:ح: Wឯ 8}!Znp#ϏH>wF +V~4amԨ-snaE,&F/+5a3P*ƀ}':u/ҟӻ:5i" LNyaJ2ij+9[+]IVvm@O;cΎAqy㩘in+gvDʽUۣuP!Y3e:j`G G +Evnj$oIaNqrLcd㱘& +N+1jmE.I=u2^3Gӑ7Q\5KIfQVE9Yp\eA7W Ƽy:=nx?]ԝG;2cFVA̝*[B<窒zoT$,uNSD46>EV Z kN_G`gmyH?U@-P9)5oljװXoBUtxI7 +j:hԛ&IS"rC1+oE>m/յsˬJB+$ P}gwY]XNEII]$iKmWckCK$ޣiiCR0gѕT.Eib CO] ^+o+WObZ ujKخԸweemM,1n,Y&y.Q ]ϧ&(6P9iozKsLɲ:rv7ۖ=ZZ$sʆ:<"\nnհHꛖڕs'zm)HTpepb-2m(TUVN4ؾ&p]tuK T$,udb٫ &Siu mucHUT)OagbweaLGtZ\J.TdRDLjV~'+SHNI*bMWa@"@"fSp~U,ۦOZF$\ +m\ɼjf34zVDkit_CT>;.7#m])ZyI9xjʬAW)qXװơFJXsV՟ʠGN*8Gkc>2pu;[YG,rhe B8 sKIzRZkt'+_=rG[WIFъ0uhbב X7+]0-/g޾;" R΋|r%A[:7ܝyJw&%ޮ`$`蠣K$D#\5| c>;t^mU47tu.z58zGMk;ucG̢bH *JZ܌qcYa :7DV;VXzE38kKH[<&fP/XtD74,] u^.D wr1{#j9hTmId,U+C\dVѢrPY>!LVi&\Z[s]}Uu+Z=&^oS>:Ij+@ED8j$ {Xcɿ?9D/뗊Y'LAU(" $f +3/fctpvϪ_OXM2Y62ѡ-,54}R3MT}U{`~)F-fnM]c+X}o53:Iֈקܼ}{YU6+ +?~ޒپt[i5qӍ2RV+[խrvUulfUW5_ڶt<]N"UF$vdT'iHmQ;g5}2'P3J}ucqWlT-"i`t!CoK*ya4Ee$8kldf)#+Jɨ\ƾ$*إČㄈ,y>\-߼AT[u Fdۍa?^Lі}$]Pum[er +RU2pC}n^u5JDD&]dIF\$C0Z=LICO#zr?ѧw#䫙c۝TsxSJdS2r+-*KÒEj&GIKHI:տ_A5eқ=K,^ue6meE*FW];CH;HTAu'. +8smV}r܎0g^L_©Ž>$d,+JZ[i#]J:;pH~7OnѐоˢE ګ:W!EcSjr̐?U\+@o?hW oN& wDw% W+]ܭuQL*#x )j_ f(1dX򵑶ާGLLW#d|G9]]8)9SX0Dʑ2ݢ +eF#~LyULg$v Yot2K d IxGՏK-BJz#~Ez°S&=E1! 4<sGO7;eYN962f +C3[~s`BO/_[ovrm꾹zd㳰'vz O#PnܢtiA  CXs{Wmq7U*+>&>7]rF͙)O#_g]GR*G4?X=R;+6;gQ)HMM칹həEזfߴL|ŷ<$ V|K 3zdcpD8Yo9$9 +C >ks@_@)>x~Y&Šu}`q O&kK:OTqk.`Vwo%ͤ#; 9&r.4t1 99mM=/eVsͻ`.WL ji DI(@xޭ4>~֢?Igy +ЍϕF|to^GIlr6uH4Ro~gI7OeZ,g4_YxԜ.? 6AFX,clMR`6Q) @kOQƀkM[?V~W*.1>_Dߋs\[?|qv.VB:5oƝۚ]1"9̩ )"8~ư;DKM^nG$ʼ`\Uwr1ѵQ¦:e)Ր61=LFje{ x +rYtR3 +Ṝ8|N& [8握 +ӥpˍ|]Ç ,)Դ,*19s&r3ꤺ( +dVGdUS6(N:j&r93g W$/ƭgZ5@:ܭmRƧkdlLbQ6},tK5bEUi'HvM?H[t>Btĵo걽ΠZͫӗ:md i։ +2SH)MU;NJeGH tTzMۗ[UWl+!+xM*vAJFADE֪\5[3*]2.+75|rNw"s}EQTyǒrAkyIhRYU]EIG,u Pֿ_ qiO e5 iYbީƏƟjb%oٍc^FJslwrLIoI"ל&Tzݪ*mʹܶ3 DɒVk:cg狞X‰w 0jq{+_mw0~mIoeh{e2m&s'3h<_ l|ITzY}+ Q^Dj%FI$U\sza(}8쿊(C|@5Qá,/$:c`ro8'*mXٯNZzιrly͡44aXn9ՆFB]{Au_ڏ+}?*̦MehI5,sg6|6=d^4\]79qCm,z޸U6n6ɶa)uWx:jW>鰗-Hيn0T +q&L{H}Яy7kj^=_1YRZl/h/H,:3H +}nf]Wӽ][כ5p4XZz3|mEUnJqg G sJm^zb<aw)>uGvΩ!KK8M6N1aW) +2cyD&k_'gV+8@>qƮfnǝ 7owͷ)};LgX?qjM ٪]bzJAJ,*`o/@0~)>=CaۇōMԾڛR;JA]#gY3XVr`DžvVFFV? >ks@_@؅mU tKlÁs;,)d$:ZAι֒4%Z)JDcb|S+'zq.%A|9PY>Y5k]/xW5Ha=L|ɑY"R;91u(ĉj*m8oFwizeWj:k8[#(,5g2I p7@^]Mf] +nt-}3e' KD克GUn]ƚEԤ^ȹλ=.#Ƽ1Rj\c_e@R k;RdHWo TKpv:vcNYڻ 5qka'9N;TnTE.Vst]{ [5^М+II'/V4l]}Quث7OhqSuxy fTVeŸe?isyf01mŔQRn_<'u'7KEiw+5:^^ҦJj dK 3I3Ze2᥶2ټj3Dh,U|jÊP_l5뤇,nK}'mƧsk$T@KOw>fMj +zbiz-ǼRfigbJ@SrqCt%) ]헭qvhTQUgVw7hG&0q^OO5 u[=ˆQ;LkV-`v,C]K4}aK7~" q05f6|pjjMm,b+vʵ:qqGw(0v~4N˥Y[:4mrpe\&j7kHkj}j]Ym_sZj3_WNԸ)dqhǑ]9u)*0yŧc{ŧc_,E-I+6MvZAӂh n[e~ 7_y۫x7k\ٕGCޠuY-.F9WV+ +0,ymq&V +M(B #z-78~ yEpp'oӮRiMqq^nkvU[jK+*(=]*yP-%`V]apHjMպ"foɩtYY6Ⱥ/s[[dk9|mZ,P/KʻZ!]/)_&6j©.Yl>T]\sRr7 8Adʢj@>GoOh&ծZ#N+7a$pjT.rç'.i%upeejǭ+ HWT*Vtҿ HWgz'r`ԚwlN5aX +2*6ue8wa;EPjK嬑ɜ71<ݣFv6==Y1tơ³pU1un3:f]scܱym;yWƽݕԊqQqIG"  +uGOM~!A徂5Y[7D};@G4FiVh1֖!-eN]BE&ᯫpi]Xe?^jrԎǜ/}Wx.1~FLvɝ˝7y-iXE}UI5QuX4!PVNb5pXpcZSzHV;a u@m]XbeB*6Z4M=rI(8lMqks+vCűi ^^uy͋ :]GokIjPKF٪Մvb)5R[6nYkgϽ`aw8ne&`yjf̵j8YDřdXe;5˥ʹYS@@M+7v]_rh}pJϫ74UH"G'ȴUfO +2^9Ø6nع]5կ[ޡTjh>lGed5υeϤrwyAId<,pvUU}idAjyTm + ÕKV)҉`R) "@jͷǷY׻e9'fYfߩO̺y+-$\tM:8wAEj8l座Aw" &bȨRL)l"//8p]I5kxEPQ["#m^ -OZVDydG +wM&Dj:oޑ?U.zP.qP؞6۬5QGEwh_aȷTejϮ%ʒuc!6YTbFJIzL'ΒxC"LMtS1P! ˒81y#Isy{Mo%)Z3VԈ+=MB."5ÄgVGG]*ě(lD)QW]eolqnPotf;6rNjMS 2tV&I۽` E1 XP[c5mIRnQ۵hѷ'VVhC^kx]‰<:a#*w/r ]>}GkΨ +Fo|Jjhk߮UlKXo2wfs$uhd)Pl&V6vJ]_xd$n&b%ʭ&gIuNJ KL0>xu'R}\|=S[jxIxJeVյ" +pFƩPpՑWlwʦ&.f g-zrz37;fl=)DUWa XBZ%aS4_Xr|W9?:ps .ޮ\:f'wJlfZ`e/? 霬LEqz7c@>:kZ +FnU㛷hkiJ[lԆI}utĔSWD>rgn\ZJ"Ҩs|{H5i$V՘bb^^A'qQNP e"c߰Pp6,.{7gjjUzfF +R9Iu5vv̢"XH\r&#Coj=Xɧvm\NK.g*!d3~Cg\WU۷O9|ˇYǎQ˧ne9rce.Ϊ*s26r?i/&ӊ[RG̭R"/nLA%MMx +q-6}c]hѫ'R3A$ +%3fz]bUj +ߠ UnkvOjh=bB3['Aac+rY [m/niٛFf[4p\,V4승Yܪd$_9S=]ÂBп_wB>]?6r}R +endstream endobj 7 0 obj [/ICCBased 9 0 R] endobj 9 0 obj <>stream +HwPS -Ћ!H $!.HZHǂ DAJQDқ4A =3μ;͛y;7g5u HL쌌]\t`-8`nn :\ ñQG܉n@% r KQd yy(D7/2Af)ԛ2 dQNr:@27T.YG3Dd,@/tWG`ϟ +pݑfz9eS+q*8 /?& +1r8jF=(HpE$=n2pjb ^]oMq G-?~:A엂D?0^0*MNQyPp?22W* Pjs5Z4m133u1)ccMcepiL\€*r]p337t4l6|-G,,ZS=MTWߛȔN6O MKkHؾq w"3FjVYvg\.4O0_䭀۷>İԵ,zÇ3!UOIE}ϳ MfրK/s+_ut~yMFp;^>l{A!vT#8jBh1?=1?;12_wt ̱2Kڅu⛰ŭov"v])@s0R%BBM4)t~0)FE.R#,86.'\a܎3.\(O)/?'"%hJ A*YG$FEFO:/ux1Ᏺw '.[$%&'>MN8{Mefޜ\<|[ GPߕg_tR21Uդ'IOKj:j꥟=~8 oh%|վ!ة:B;|m_xCQHcqiSgftgX>_] Z2[^L6~nUbqf6݁xk  LAQ(л;1ɆYyH35VO6U8+|#Ӊ ~Sg/̿)q4$C +Qߎ'JHKJKde+19X\#P^IA\G^iWyIeLOs' +]tub#NcfZ+ 3V֟N ~85`o08zzi/.[{P"ܓKK ȁ)M!}a,(h^bgT_x{q)DaoBT4'WFAKfZވ̺\p]{닧JKe**?sPD-˟ugmFME-}mKtݫ؎΁n7o= +{ /@? J ؏z~$Os9=}s&w6w|B䥸s+~_\l׍on"ߖvwǿM_ U D +2-&6Øa YNL(%#,Vk 3*G g >70^_><@QkbJ$, w\uD65eI(H2HKJee;J\ / УX줢 +W]TkS/?nyB@K׬] =I1!$?P9+F'М$埈s aN_bg8SaKbmk`/lvp:&ғIFGh HCH'8+y ;89E,{P8[R^4V< +Kxl qQW2:HG +r;A;bjJ +߹/3?z(HjU4r6\ttL(ӧ!è^+!d Eeo_87}/tg}KLsurc.p eӎ`qt 3,#|Zh80I5]^K= ǜ;yyC1TxA6G6zW[h +><1]^~|h hO#PT +>$P@%hیoK/{W4yw8 f8e D*RBy;`nQtVy:_@ϨgaJ.?c}z5M7D>XP j2{89 +O +#/a^#.y?FPgq?:K1b4wߘUuF]WqP&:=9ݵ`ez}1mޒpd7lY1-uCrjz19"z/ +2 caZnpHu| +zP1iDhTL.YeP]G&G,,` ]` Aѡ-/s">BUuF.{T}ؗ) N!"GB;dl߅[LpـnF9 ZXcL8xէeW[o@ē1VL-#C&k*K&vV,*p$i;Rxټ_PG?+\ʽMbL6))r>=@x5*fv]^Zduz]X?P41p 9Q~*^ *,0#%8b;Q'p*$LEf"޵wǕSC戽Hah :-"dk>uy7C/)d%x`'qyo SY "&]#6؂5;4uWy +tk/ G &0,#Bv"R9 59oQm@;/D5RIP+-GM#º'uhAt0";=kմ?{-We_]ډ[jA )H>Au%W#Ժ>D.ٜJA1~ S̕V asUB +䪪/j)+68˼=wpmbnv\ߝtGOx;`uKJ ̄wAߕx~Ϟl.ɂQ!h0RȥjEGlsܦ5# J58/G V//"N1J;mh`$?,Wq$L$0lJVzq+ĬЈAaix!dpTP/H_ zZYs-dqN +U)$Yǭ, H -Ϻg,7xeIHh6 <{*M@+{ Pw/fID. O-Me̙mu+M­y!@*D> Ox0LA % v[Flrt@q+ /4r +X8Dm*Q/ZB\@a8~r;E=,7!oM2D[..Reړ7tA};GbsWh q2A];%mi"+g=Uf*l3xݲ?I a~ /&.u +궥 +>'ggUi AN?oO%),z~U޶ 3^Gj)ȀZMۂFiPnQY#TVtgSVD^O˿:JOg+SMnveKlou"̋'gøSzّ[ oIpkк½+/eM=Pm4?EAO =Ф>˭=@tVw {[u)jW>'jcJ|e57R1a7/zu c\V˞ Bb-C~}5ְGU*Z$SmƩૌL "CƼ+g~>dwE͢B`Ѥ*]vQ)TTڒWЬ~E0!U~Jqb `,<7q |?ķz\w5)r-C#n[-V 1/ceSˤpm^/hOC0eծXd#GQ(HJ3`7޼yofq-Eߦ~_ڎOZKW>(C8(8>=%šЦx>ǝ/@'3EHeʹb#ӓ"=ݯQMcOu䅂A~d+ʡ^yk2͈pRtzdswB8u9]7}CꫲQ] )>^6&$Gk{«C\L`ȣnggw +;.ˊr_/C:x)P]aΥ:媀B3-⊗cpcـ=#ӗ=Z"#j%"b7KJːйcle/_>‡*E7@+V6ŸnvQGM]wTnG<2 !_,>P蓧VwN5[,*tgGvR20B'džɫ+ tGj x1jMTn"AKFoUkoȱ*h$e1%#*54N nRΝ7ⶂĎ +V"8%{4G(ȫ*d+~?ɟt#gG9w[wߺ4ݑĈvOrb4鴶ר=yR:p(bHY-Ƞ$D~)5a:GXmr ]c^vzKS8=UĊ3c7o1UNϹu!8EGpҮ69 Esu|?Wx5ɻ3FI a ~۸ߕ +TCY bY#thG:tW5-BG^pw+.xZ t#4r uI_o$郅t/*-]V:SI#< +BqEd_07Ɉp0 e,%(IkLgu=Xin## Ί9W"o;!t%-Izx`to[!֦Z?Q,YjwgW tCOTmW}9Ӓ B$pqL?5LRDH|]gpOhz셠kJ$ۨ +sOk|8C "rզqc (:/k~%Dj[ihH5nߛ-787_A%V"RjxwڶᎣͿ3"汬6EVÄA'X*{G~GZVAZv}&(lݽ6$>Yԟn-ZT3(( D;峰&pۜ :J2gkSIJ}']V +WC;KX_="ŸXʰ #ލ=Omp(e{K  nK 溞b@mfl_#va^Xw4"f0aAҰUҷ`,."4*kĔQ~$pwf k33vRIܞ =|߬oS-KmaRf@8(M_!^3<.ẂXש?{غΏ{h*0I 8G.6hy MBYnW"v vhZn?lL,6XS(i)IfړH|E8Mۀ])>ZɿݳzK=IǴAK)jT|~/|x7L |{R.YXv /hiqM:=cMYCgHZrqqeNfFz.R&)φ,+.Obp.5^W۸&P4^?7H~(+Pjřv$JӇi|zK:mS`Rץ~q1Zo8#π)Ɂg.<}CL(pd,KWJKJo>v܂1%~#6ÜGyuQ`|ƿopCćKc˴WbJ>5&0"J⛰)nÈij||bocv勒WJ=h0Ρ=("hhψБ{oj{;cFVPDJht"=ލ:0"ݜ6׉20}{bnbVEJҒN=~80="ZӋ2z&njub2~U/^IEz=F0fJ"5ƗƄˇ¨zqťm +aUIrÚ=! 0KN"𚙓0qq(ynmi]a PU>?IG<բ038|"5|;"yh!lYf`TڧHϦݤ<30ŝ)#ae^ڼxภl`ST_'HF<{ڤ0iN#({-~~r}f}Z}OGD~ C~7H+)Ѥ݁j~n +rI;fS炜ZKO^?Cm]7{‚+EܣՄ'd+т~@( rf"Zv&NܶCG67^4+(>0N?~/m r7if+ZegN͵ҊC:Y;7R5*g^W΃}̪qwen"Z/NPCF7>n*H2HSՃU}qhʙfe{/Yڹ=NZWBђF7#I*Ɛ3D.r݃},kq;e-,3YVNB'E7 *Xxi<|pķ]dྠZYHMmB}6S+ffOBT;|rp8dX0M@Bp#6񧴜+™@ |r|`p;˯dNSXMpEBPg~6-+- <{$*6aWm: ;^h(zUfb 3`7)GH$I܊賏[:.mjrupTFgʛQ_:= e4V}C?1]@8l^|Eb?,Υkz, +00X m[<?bPAߩ,C] IGe_ ߠ .1^IxO/'`c R.1B8- 梛x*g;ԗ~KtCP^W.T +Dw2EkH|0`W*q"]|P&XbĀC\1=.kCլĊIUl(ha^ȊKJmXpq}P9Vaâo^Q#ŜdD@@φPފ YAɈ~joJ V@ZK.9@Ya΃d˷glĝsg5Ņh7\ |[X̑BAa#7qb̔+z *&3(Vcҗ.' +&1O%D'M DzFHq K0;J5 7GdQX"/! C\8"wv%>+>r'ф1N[Mƿɢuo✔b/HRl+W|[{ṕ)LvŝiC؋pׯ—g߬ +1+KL!Ԙ@|m#>`V(S<{;PXVK~JxY'VV}b{7anWT4[ ҿ\݈lbR%oNCl:^sZEѯZQ-33*HqB6Jwhgڛ:gդ73s=?Wѐ*vn):AНy=liC4X Qע.273ghgq4WZܜtm|>x xRr!P s{P"_PŠyW;f3x^CSW) ((\< 25;} y$RrF|_*@uN$-'?hp +08^`lw`Yll`ײ/lp q28u{lbۇ̝9M;]w[c]|B[v4hL̫%B"HPgp"?es1c\cekE +B7)*ѧ7{>ĭGulk(67aRܶcS|}<()2L/ΤX.`sk$Z<%S0aF~l7'y i^2N@HS&xpyRF}Nք5Qd-!c%٘$cL# + Zx..m}1K橤ybI֜%sSBqrMї8mr0)YͳRܹB wWX8Je3)}U[ )WO{eTS pJJyςG5ꪲ5\E2zP$\ +YFtQwd^Nk+J*6VDy[JB~3{?=cƌifhEJcpn|\VtP rfW,ծB;?Cq9eXc8ß+͋ǚSO붅R.s+ƀ}tຎͰ՝W7۔Av+dol6\9)<:`Z2^M{ר8vWA1it}+4~iD?Q)pC63:>lm~8Q=ӌ*`{3~|wT7Q@AX-Re1CYTL/&Na%づ!o<.ΆD@hLX!V[0|rrɳ$ `M[q>/C +1wEtHt8Eu%UTTl^*!%U,kF܂0!wi %"I(s\׿knu6F rH( &U1?OP|vINI"(* b خ0'kMԸRO3 +KyشvYV:^tFƔ.{od%;V:6C&1nG(y%^eOacD=4ONi6썂; ˭L`f7Qk{2f7PI"ăW(^\ $b1S.%.F6;oAAj[ T>f+(n_I߉^ʻǫbȌ[nq 13ߏBb7C Ӂ|S綵<*/У%ڋDrܱo|RהulsUZ_fת@^uP6T)#:ςlama$Hl^z'1`XPҺ}*%]ibd9&e@՗}@v^HdnKn( +̖{]1;R ;e#ZT"?hpiK Bzޒf1zlRIP<΅R1bm],2;%E7THM>+aOέbw?R HGQK+6f[ev&ŧj|xR4X%kZ% Nhr  HzOޢ[WJk2V\^Jpsκ[GFH'3Yb}O. =דgM!.grWsG @d+Mw8|oA8a +6'GCg5ɇE-h-;^)(pdϔPY u_Te.#!S*0zo#,,~vï:9wՔsU CKWWP)PbE8ʊ w_{zr_ YY{X~ */? 9e!+s<>&.F6һL1jX:U*$ION{y/Yf?ֳb fRowgJ[9T ܹ,$~Z͠I3!MZ)%rKi&yNl!쟢#" ы? p{1(n?%#T3Bym#la ߼oÌW$e-meҡrlwũ ߏ`n9q#l#O#&&ELI +*&/x }vuL7 Z +ڡ>k$G-)1="Y_w: j˱LiYm! ;ʀ}bZFr'^;hͰYնg0hE6AL%eO%wAݞa?UBW24a:Qc᪜~yʦ/ dWm_Z!ÿlq* MlX[͔+l;):|UKeo3W # +)ln>fĆ3 _yL3̀yVii߇k4[p+Z~ɮNW +WB~l^Q%¸k=LzbBw -lƯ* +BD+R7[T*Pu2Gn.(+QO^K#6`.m@6?e÷ Yk7|RO;1KKCXo }Ic?bVx*r7k23{7}M ;=3˚P1YldHv^Jg1͘܇L>Lۡ=mz!b= ,;1) ,%=3|~XEq1o[9^iUSlwzXRkTNP'JeR@݌1p4@ٕK\Ƽ42i|S`D7n.\|"Pm4QX!:# 9Qqb.'$g/jj)?cNF=R%ȟ5TC"/A%Ԡ̟uVmvMI@V#Gxt%CG:T5ɻ5?I'Lwn|ͱ |!\d-CWnd l[ ujoT^6ݖDJ(?X`yt+`˃c8Be^bUvRs-ga>ru{?VK3(r[ܓ|%_#|F|=Iާi m߈0l108 1"+9L(h_UK4wFw#ˏqyZ)vԨ +"kSͲE~fy,pN<<6 eݽXYۻm-; ujp]ɥcRd94M8HjhpMq:)ޞ=3U޶ 5Oq}Ri'!.gEWOL::Le˾FMq.3J\%|G/)^yS +7%Tw#UUCs0}* ڇ(jWA,ӘTR r`]Crz5_VYA9?uayK$mZiin%44Q5Zq%!'Jj$;tр +a,ߛp,=Dշ{nk>Rg,*CcL57iRXZ#EoP ?ҶC_=~vǹ{*N6uW2'{R_irUR(5kx;$d#D^vS:2r[i<WΩ텇wƬw.n4]hlt9/ъx‘;vjjG)Df{׵'8yGWm~MSE"70]˝4Oڑ5|j/@@t'("2h8@$$j$pX]md%WO, 1{O?mShʌ#e3# ($NxX{OZlߢ@Ñ"G\t!nTӺ1~Z%I9zBu-r]f@&\Y˥%RMN:g@W2ݚ $cMSBԶ(~glqIeY8 +LԠ?2o$?9a s}DZ4qlse -X"Lk-?pr2i@$~Ó2Mʉii}ppʬdsƝX3K?P20l,$i|d%|_^pc˧jWSKS>񛎛P1$Nݎ/M,{oi{c6WK>112$6+ X;݉ӅQ8c{ anBzbݮVVJ>W1F$"ӘnD qo3nw9wQwkax_[y)SfVyGqz:{-|}Kŀ`}vػ}j}^~S{~kG%~:k-Ǡ%𑙂GmvEjs`^< RFߨ7:-i Zk/J恌\u9i$^;qRr凋Fp:V>-Y'q4ᐹu;iwrO]ɯR1#FQP:-kBQɘj``t¹Qhⓧ]H$QEp9ݡَr-L I'ar+tLhe\ٮQ=E9D@-2Fg X}F֌r^s˸hf\f$P٩EZ9pO- *7+~s>g[魱APnE97<,- %Yr[~e°Frcg2[{OPD9О,曹 ,ٕ{o$}߼lXrHf["tOĨWsDƦ8ܟx,ԛ\ 2r0ۊwDxlGŬy`*yYUyJz?h{3׫|p't}t~ S%? 8w>~lĭ~`/~~U~Jb~?KQ3Ū'iĢ Ђ?w;8kð:`r:UZLJJ.?873u't⡤ 읠8 ڂv>ks°`4>U>*J<χ?1H3 'C ,aIvsk'ޏp_hU%J ?R3'ģ%U x͏vk͖j6_TmI۬E3R'ˢ׎7Y [Hv B|j/_b$TaΖI>r43u8'ТTꎾ9f#-u¢CjU _T7IC>ԗZ3c%'ڡm#% niu`Gj/^к kS̴Ih>\>3Vc'ǖmH̗ЊXՃuҮi*^S$HѮ碟>:C3Kޝ +':Ғ1)Xtjwi|Ȱ^T5=SV,H?>V3Bs(Ț1V6IȋybtPyuz_v֯zwA{}6xBxvPŬ gcn +7N\VYgM`TfM~o1*:hgKxD:ppqR /Gx-5-Ӡ`_ol ts&+s0K2'AkO* +7UdAjD-Q&!Q B \ 3h(;l 0weX{!i)5$uۙ.mD&WdXQ6l44+\e8\SaOƞ*˞!}S|ILJ\ +h8񜴸x$<~PZ?wJQԔ5 FvS:r]P"6(F^]Se >:1*ٛ>LUh\W-[VLIkIHl t0,x Ԝwe\q$**&6(w$׮|~<NDYo@cuh"hA(w3$ϛvY?qz;*܁ˋ ͔o\/׸, %)gaNh{N*/P0v(= +0?ER.ocqE-輏'l$m'X +<۝|!b_7sD]&1b+r'"ؔ\ާ7-rܕbMxswq >"5OE"ϞGG2/#w5m_QwRrRq<$W`K(ABc>%%D 0oD`D :P˝nYE5e۹+F2Wͪy"9u/pQF$'ߕ>r3&=70N@9 +mUQ)!..U[_ +?KFJ4GĹÄY$ܐ''\]fG63IAv_mfax"C%k4BbT4TՂ"k<\{dq s7/d4V +{lhxZ]b[~=ifig 5Fb(ק9;O٧ViGGX_}n]wӸik6f:,p,@бkbmuFR!s37:!?`CW֧&`':gUDtx4DLؠ²CKh#NLoosR +mRҦUa9B6c.oo18g JVnv[[mFGvzB+J02Nhļɍr/ 䜲Cy5(raDlGx~H?I.ȩ GH;A!A0sARxJ8*ۛD[Ѯ~b +W.Q{!n(1_9W'IlCw'Cp^~u% ^pV& > Mфy6_E%.xA01݇"QC͈ZK+gD2sϑKtOt z nf9 ?Md$n|c-G\zx 1~F;ĚBtB":E&'>"3$vAPrfm#t&pJN866n^yOOMZ,z~ Py$;l*|\7󱇭 ؒvߪUDl?ᐺ,"uy )mܞhqS:wdREZk4cS>nW=kvKPmGYpfo&]*YV.#^LCxTrz )s=\||V+w]mԇZc&r~2fAcS_ he)>t*qQt`1x w֏+I۾:hYK *9I|8Yk^nT| uڿkVܥCA$r*S$s,ౝ+z`;mP걢dbP% @]6 +UUu +nIR:^ar]J& :þҝm)%қFҚp} 2e d';(MdFڶk ]*HДPPCjߙ m> wE2j샽/;Έ?* ,oqS6wniZMfOdI&~Ej*tcHV=֗7<Lk2XF]E=m,6rU蹲P/WSEFlPyzS8Q:/~`~kLS 0RߪnFS+d@wQlf6Vkd`j⻪5)0T5 8+F9yᲹl( ܺ),,&L@!A~VSHIe"3o%4*%yV "_;Sa8iqk¦&m&*F^XbBϓ.$%_d nC^36^$LI|yIB 3Uu ê+z;EQ^}NW%'%3mD35+۞AFI#7'_1m 1˚wEkG eZaV7Uͅf5‚"m/)euw"FYwI׵Xq [8f2n88EOfQk:sXpcuʒ@}5u ?TUf݅]m[-S]Лc<"_.×z;,^Aɝwp36 +i‡WRj|pI%(E:"L{+:eȾgdOژ9ؔgF:fՓ ԙdb:JJ[pdR"QfQPgeGE}bOSZ p0Jd9 ܽIrpGm]$h$0Åzm㍝|Si aYvq%ҞY[iS= z D>x̢L# dsV6S'ɷb]T%/y%7[]X%iLjj#]W=f&0]h=0yx\P ؋ǯ]uG_i?M^.ZRbG*I;Ҙh.}h!BQ0bPEYBtZi+m]xR)^FПf:s.C?!%8^k gbztٱh]3YQǟbFc:y'.!ܖYi3s{Wrp?sBe t`Y|u]NZLvB@w6}x*@z1y{l <1}8${ +uxo﷑yӚRPg΂MyiniƊc]*,X;߉aMAI6:)phgz<όۂx葿mݴbʯeW9.L2A\58)ݛ?htz2uzv{'1wR{Qx|Mlx|X4y}PCzZ}-ez~ z~-qԃ s-t;£9u(iv1}wjwW5xByvl,y6ycpm9+qr󊦡s2t|uivVKw߅B!x,[yiyweoSRp3q𒩠sōt{wu,lhv2Unw&TAzw+xXxZԳntQ gXSТ(LRp*৥U +!!$$wߛ{C I0B{M ED[T~{QfiŌ=~\C¤P/P%`vָ)Y /Y4T?5hMsqjq+:m'E)̐/kby@}{DR39놑>cvvSDžƖM t?65)`o&Z]d?qF4۳}lA(h|}]f;+ʹ @갋.+'n&oA\!R\;u"Q<7!ia2Sp>&ΠڴA2NPKGU;PomBp: oBv:khC8|Zp@_+nPy_@iiyi1&o)y -wSuP$-_gK?fBX/zQ է+v [+Џ3(-]tY!(y e辬9h ro/r%shxu/cP}O:kՏ@9`Ys3Crz 'Xk޸?i1GF)eDK;hز_6AЧ;rl%ۙ:$QFVwp04sf8) w|1-R͓ykx ELуCSL]*R)p̜:Rیh_<.9]QqAJKAmao:Bv/20%!;9)L͓ka{&(}{9lI:RV*҅VG܁`@*a/&]-ad{K͔5-O oۄs kgNO^˟J5YQhl:/=y%qNXD2D^Z@:3sz0ow=+,b{/. R0q 3NyG.:d*K%4U=أ9Wu"gb{3Umg5 g}xFO]RqޗŲfv5gW]eWC;SpFbHy flO0: W띀q\~#?RҤwPw@TzښY0ldӮ㣖e: s/:!g1!w<<>`Eսºshsj-AgAZB#J>ݍmȨtwXTa))A? +wGPXkm +_BIѨ+ ڣ㞠t7tj}7Deߣo]3%j%Hn- E/GXr#3,+b=?^'NC%}Uss6p)n2|0%wiC^0mo#703:|ܞ+¤ sW +TmJocz}a Ҽ؈ WǖSKl$t_@*CTV z7vdr]&4DiOQi lp;#K}&B׉/4"a$+08Mh~TRiu+a2&dg}y j`D/%@3J`<[rO@ojƛiCA F-y\H4tj Ys~T:eK3 +xJкDg&vhh\ +6+5DľGѺHs͉}dU3 ͫV>2  + ]-jxP$#LmNܫyZ44CDcXj66DgmZHSd}Wlɾ[oy@nę&)Ι;-~(.xrZG`znr YoB)`cТzٶmixC,WSeH)5ڗ>B>dS#YZ퐉FyQ R!,-j"~jo**e; +I`h]<nVD¤Hb,q(Ȕ4ZcGP=sQpv/R0!pxe_l&!?F%GNw33䊘""=XC7Βq/߉)˗M9h;F奢.qY8$I-BD/ĵ#L(>f+oZˎL;T +O'{XzE|H>PcU)'ItJ&}>wͧ3dQ%{z ;-'L5CXj>^!#ͪIWhMsfZC&9 +3WʏeL)!acE2'(h*A)?+f7GHtcfի-(U+bІ]Qx[Beb; \h3J0 DMM;Q[9Ԙ8L*fd@kR9rLDg5ٍBuJCa&NOlٯAM :m!vİ̞;('y *1\_M +UH1("D H٠hdC fܛABf"S"Y EQ˧ҴFTɍ +Ϧmߔq;K/G(:'ܷb^# jQtkA}R*SY<~522]t%/pN+t֬ Nh*{]YqxJ<+KKG/4x1%vJ1aKtׄ\&I0GIW)O1)}+% rD"Pc@?CNM_^(6ڔLAʯȿo>-}r7"w:()2I1_vZ4^u)j'6kV6V, Vb# ?/;̱;o5g:nĬ7},4mG6_n) yҰ_2l(󊞎hs`L]x7z.թQһޜ첱nEͣc:6ԥ4ݨ`j(a֍4kɪRM]Լe+-[Zb_Hq6Zن:2+}Ec]ZH&:LQОkdèi_V.36$o^ϰQ-E4<7*,+}3a$}r RHjgKV\zRffmÉl@$]{%qf,h`=Zo:5snX5~ ą(J||5v hGa};WO{p S*8"7xD"U+7euIR +wejwtpO1Yt37z h3HjYh+0`ҕ#ݶb?&ZQ~ )TKty ɘ1r)G^T>Q0ON\PP+8\6zQ-*Ze^Pxe +dP&ub~JY!Y/!]1h>@jVuF'lqV螩m1:UH≢8QEvWb\#ˡyNſ'\u/H$wuψ +MxoI&v}!&yh嫎\0txcL0UA6,*ilȔntmTiy+n^֯pLTqIG#s>jt2١2v&&Xw+Ix +̙+{Sޏ;~sRsi +t^yuSvHw>-xx2!y&.z_| 7~irzhz^{S[{H|=u|2}|&~NE hw GrW?gÀc]{RπHR=l2h=&j BP!qƴ%rgk݆*]ŅRztG77=_285&w3%ח :.q=Z\f߯ \wQ=7G= ׉2z&ff P!9pKfU>\r"QG,<ş:1՛׌t&W-  Œ yhYp,Leέ[_Q' FϢSu<{L1C`&A/; 5Èo}beHq[\P}FkǗQ<*#1g& ; un4dʬZnPM@FOQ;❰12D&Y <Ո6nk̫0d\Z;OE̠b;R1䛨%ꖞr TS_Ahnn^xo{TYcpJWq@WsP6OZt+v[ >?wy9|@%hz=tq^\uTI6uJHv@Niw6N;x+Yy j{$\|h=1~LW4h9zd^%szTzJ*{Z@S׀.IxB@%y6;+Ĥ7  +Z5x+!KVӘЍ ++B eq~[8RtH^ 6>ͧȚ5R*+p!$ +ɑK<ł0e9P[}Q-H.>R254$+a_!8F +feh`Nrj3.s%l5Vt#n#bu oJuqzvs[gzwtTaxv@vyww*yxfzyoѾotK*puH|r/v@sPw0thx"xuzyfPvyS_wz?xd{* x|fy|`m~o#~"p~8q~_Is~wt6~ewfI)wNgxE|k݇%mêo +gpqlqńvPsjd:tRQuu>Dv}))vgẃ~j +OlJrmo^pƋQu!r$c9svPt=u(v'w8i^kdminsx(tOgu@jgyiikȒl 8ԉp"GV_lRȑ!R1>f13fc3B}]ښX߯6ax4Ḫձ쵺9U[sKmyS GP mWlDk#XLꎇ }qK/cH+Mg53Y;+' 2rcz(NwV@87S߾kRn4M5> 6d\t"gE7scLìyCQte;Cop1\mFM9ky+@$z FJ(lSʐߑ44l1/W1cVģz&yOqu]&ЉO(aKv\qX!0͡#,WٖM + r]S~³Km#jc=Bf3>"d',EodbU})XO%yڪ!J@U~e ѼvӋ@qnM!{ n3۲c iwuCcS:dZ7;Kw%7@ks5N'A̝ra{;N93&`qhJۭSיά׺#420$j9CJ9gVK0+H`&~=s* Da%ZCC B l#n#Wϑ+Kd0y WĠFy怙V\0FjLMa o ".3y;XJēj3?$&LmB[Bzth1Cӑ|MƸkXm4LP3Gq!pbM-ܾtw$!2fFz$(b_n-zz1脝[Xdaz=YnQyKU?؎Z'c+U܋]ʅ3QC~"tN~R184֭5Bک+HR.MJ0Q ,; +=PmhbaOZG|mXs̩^4 >?@Uzڽ'a8,Y oۃ<)P [i H60?[^&=NBG 'i]a# +@LA5&i6u3QsN=g6P`f+]i@'RG@=`eU~Qa!:ǶWK_5PK)P>-hΎ7Tհ\W9'i6["%ӡvȘY) +IN0aI !5t9#$1$g]0d 8.{t7MO "nmaa1%T*CJPyj^^ln+T,@ :b̴S6,Ik0JA\,H!̭\R(`H:.pqIx5ͯkR|=m;WRq|)Yf+1~M"%gz6[*eF_gN>OEm{Qy%yI)/O"mr#yBAԐJ#ӖQz9Gz!dA[~2di"nw^XO(Y /"%gbJ'GXmlz@EIDz^9sޯ9̫166j?ǫ֢e,]wrUX>>%{|K@); 4jw@QOZO'8ey`2:<@}]bQ_fy֓hе>"!R Ycݚn0R}˶5\?fU$ 0FuR(` y>| \c]m4ӫ {RiB:okd"*> ~QuIP.|u7 d%T_bB=ֻI<~E=cn~ѣ#ߪ'l͞5u S[ 7\pBEbQL^:l +RV&yrQ՟2G4&sNwԶ3+Ji}/jZx,"d{~yGRX;w)G="q{,xں?U>)!崸tU3Dz.#>8DÁεǰ`G  5T<8 5tvnk0'#O<2PwndO(aY2~ ,⫈o0"fwqrMnHDKC BP.U%XdBfЁ0):}`8M{ğE[KHC沱K_Õ0A#^Z}G>lK0zAK؁7{"LA[ +CA# -nrf,lp%ǜ(l0yL@-yDS~-~e +S4c^z +]5Y&p^G6 +tk +΋@ qѶN6I`a?bꢗ `Pl{i0>#xz)FXہvgڮPxKkn Y^㫳3\~qUv*mI{RXj;,&9N\FD Dwx#YvZ򚹠NۙW)+(YCv:+4CYM,ٸrNF"I~y?)LZiI|`N]{ɿ;fHw2IİeL{Kx`*Q }7c}*72`Sٔ# (%,FS>?cu0 !.VvjnEe6f_^uUM~j~@∋j&}TX/jkB_yzn/a2=ȁ#v u({X/CߘGs ;9!猬/~u읪O8YeIqKLoRQӴfKK.ADcgT4X}nzQ+i=˸BXK}6T {e) rtv}I o.-p`-\񪰸YxM78WmM' :{*p^ʆ8_׾@u+dIWЧ-CRy:((f{3/ X']5ex%] +~%^ At "X]-ig48|GҴ 3" _pd=DSFEK T)[d/JsI.].K.,T *VWgŭu<9>GIy1iAH"M Pq n_}^1E:c:hڶ~*}kK2g%d_o: ~_/l9PKo:~Ty(mmaWHЫͳ/stMDxI,LQ5 SMzt)$"`rSh +K qr#D O[5}yH4&{zEk&Rkd)Y%V2@q3(9w1>h?h FFf &R#`T>e 7kv1ЊȬZ5mMӣЙC^(Vϗ~Z՞Iͼi:XjXG|(=EY6{T 5aȭ@<_P56{>HZV)r}{)owYWc\i#m5Zݑ4ӉUau +XQU<]-}!e \NfQ,u,.|O|f~\Z? έA }sy%*_I)ο`ߞ6_ҷ;I\la Ch)Ha{~ T' 3zIgKw{5czֺUw: bĀvX~fծrCi ˳?qLr(|# +/[cW}BwsZk>KcYpڸ?fr+"4'90Q&OVt\q]s_x>[2Tލ (Z_kN4 +LEF)"bv׸ۊ<.|ԲBT?X  hLcԀ ci.W$-lBB5 +_ƭ$SYo^,^rhT (ʥ )4gɒ?s"z`Gyو=\ϣ_RHO Oq|<  +6J rU>{E10Ipe6V DOy! + +ldRp*<s-qwTGJ*_Y$,';b,^vO'χjtZJԡ' c;l?o7t=-~Ԯui87uԕX.W涐h'y` Syn?wdT [{/\߻یל,yĐBs S-\r77dho߁Ua[ancOIw]}Yf#Z  ZBLmDCᖧnnGrν79 +Ep/dtu]9 _]l .}oz"{D| {~׋lajͯ{a{W%|%M,|C$j}9-}.VM~S"  ڒfJj*H`l`VqLŁvB x8ǝ8.+V"΂ƃ6 +/1(i2_VJLE0Bc8~u-"ٔ' +{ jh_`-RUKJB=8>ˉ-ؘ܉p"ۖ1vވ + <kсhcH^ۨU>K~Ab7--:K"ɕ  +.d!g뫮^Y}TO"KA]“t7]-q" ^ g|g[]٧Z9TLěJlA 8S7g-> g"W Ŏ .fê&]cSTJ]@Ŝȝ57/R-"q蔻H D=F7a_iGW¸RjN56l?D9m;EQo1qz'@sEwtbxvјz~a-oGWpANqUDr;3 +s1KuY'vxLϞyX |`ܹu)WQuMױvpDuwG;x<1 yG'zj柤{/;}ϕ![`oN{VM{QMY{D9x|":쨖|1}`'U~Z~9nK3`MVBMCICm:1c'<72lؚ3~_efVLZLcCJ:/1`Ӆ4'Sb[0(qtU!ɀ_gVL@Cyɉ:Y;1D'zQlqJ x_uU/LrڏC=#:(0l1#]'ό&ˆA0^UgxL&B@9s0/'uÎ˖H[[^YTUXKjBç9£Ζ0Ӡ}'y +5,~^BTѮŠKߞBl9I0'i6f *!^ȁ ne og +pirl(s7n;sGt\pBa|ur0O-vt<wu&xv ywxƹk^nmpx2nq;psQ+qxtrru`ctw+NHgŠ;i؉Ck\/m^no ]~pKr<9vsI%Jsuւtd6wfxhҐCjP}l{mn8W\oފK%q\8rN%rUWu'3cA.e#g蘟 iՖL|klm}[o.Jp8q$r1tb}d壉glif{jklҗ[nIp^85qJ +$q@t2ua߯媧d@fx\hozjX)jl2ZjmSI|o'7pN$qDsfaDceWgziͧj)kYmkIn7p;$}psN/`Jc0EeyO:gnoyii[ik8Y^l@Hn7fo՜u$ep&+sAt1dK#uf2ui`vk}wAmm wo[xqJ <ԉ]*DmW-9:E"%f}` rXJVwmzm,j[Q^KٍHG(َE4kXׁgJ./ w$턔@OxP +y9VlxZk|][$HC?nW3^#4#`'-q%;Q/خf̛`ƭrw O'erϩutKeJ4@x!@/I_!; y@8,Z=lKzQ{T/!G=Jl-x A 3F6rpJǚ;jhi-+ +4OyUVX=oRNwPFV<m1*GP<,yyfC%T/QyM&_Y88$ 8Rt8 +l/E@Cૺx+6]0Bl)q +kd "Ym?7hk$"P!(0 ,V ohJH}nJޣDY"?ޔU=a-\Zq`8g9f\ +Y|7j) +[ݤ^UtsNo׬!(rZ7C5y'gϫA;?JݎBņȐzc*K?]3'7(;\ޮ4*|KNsB!+| pF`OWp"+&ނhĤ=- {/5&2=(yA+=?9SJ} t*DlBU(ѵv"9s>y1zȭV!eQ6_T~7FD]Cw[k>D3 |LEH-'P8YOz2j = ^ u)>QJ$$~=Q Dp7!aa΄E?Z6n;u95~VT^>) +x\q})Q*flfwD,*'}=?BuppQF~)GOFWW/h4^֪͡kUj\uEʌmd_? +ʞouQ) E) Rp!%~^݀mlD+sbW4M +I"Tq`h孁;2-"1̄G ?XxAs~=pQN5F +T-Qjau!MPNi.? B+SO a_BL~nhw%G~y]wJB`E} oe7c[_j$'(߇ |6lTB򴽉6AX+aO.-P5醲=DMHPo5r1O+qkխfIRzjY).A[6FW|{./]Lm lcŻې/13p9紸9.Ï4F>Kع[Gi9—5XkhvY_݃ͩfs?% ixy@v '}̓7ŴG>yC_A^9zM4̠ug(.'z Oӡ }LՔFFO3^3iIfW +ENֆ\$,K*䙊,rBV.ܠeXyIiw[8Z'Uqhc%(>5$ܑj2\gvi,8ɂԂ;^ q8 +N(7O`AlYʿ3WGvRF wy&]=B)+D_7:zrzC%?*!SfS[x?j(S:PKѭt*tV{>9}ޣMJh 5ڙ" +)dfe$)eǵ5ߜJ \iC &)֬ Gb^QQCBe@|%xD2,Z*첄ɳMI}{Hϳ^k +:%(ʩ$?'펠dIW;Fs/K->#n\J5d["tY`L-UӮx["!.vψoKh++쭼 'VxhU]'V'7 |IJl!ԍ. ~;pcn +kT!8+G6|| {H+ƌ+h(4f[  Gg`W': h?|&b(~Rݘ!|_nCRעGL$ EJqtʽL:#sZD,QREIpY͊ŴX.ϰ),vUO_Q ǁ, &˵ +0kěY +0/J}+^,"8xd@1;t$6c-IC S~1L +%d57SE;g65N|v#e!!YH/(~*!)h#j |xT"JJӆ)0nGya OY9^`%*$'LTgw@!!a=>>j>mPbػnX!mSY%#C!ﵼ='4Ut|KaO+aWc%^^[^=3lXqv[^dVo{P fܮ=2spӏ7Bl{B +:ط3&N_=@ 9ˑlW>` =Fx8*>zL[`㛻ͱ%(U;hn頑̯ϛ'@5[\#/N^>-a#J-P +mW +ͲXY}^%=<\7yE0jw\XzZU͈޻g7{BmTtnj U5'_%_hI*OWVωsCU%oT_`-Id$,$5~u>UVjKDj2*u}? +MTC.aB.3j:@c~h$:䧒.u^H^*GAf5\џ] U-Lpt]TцPcY@V%/S%1z$f!h)ȥ,g$:b,6Ь5ex]>9R 'I*krG]ȴP$菜)LZ͈|s-hxVQWtTӧ'1uܭ}[3,n YYшXfU| qȌ5sg;\_Q=oqEI:GW-qU& _` "x{8pfj["PE֗9Ӗ-۔7ރڐ肇nMvz`'pCQe +D[;PCKE.x9Uu,ڄx|njozycp,%eregZiOel&DnX7ɑpY*r1fs u{Dy|io=ikdzC +9\ݔ.ޓ#܌iB  fhS_dU+LnȜB͒9qn.r9#ŏ` '2 +)eS}c\eRhHj&?0lB5Wnf*bphrC\s{w&}#di[XkR'm[H$n>ߠ;p5lr\*t6uw/z~Ud &oZqPQrHs>u 4ݜ"vX*uwFxKz:x} dcjuZIvQ swGx>"y4zl*Op{XOc|M=}]9<W;b| Yh|PV}G0z}=Ŝ}4O~*,]VCxGCbYpPf)Fʞ-=rH4v* v[H, aqXkO#FqÆ=*3ܘ0])𕮆X_oّ!؋pG`ٍgX)ȌO@ь2F|<ޚ93zn)͔#X f (`n!>WaNɟvEBt<3a͎)GOD4ۊr 5W:P_z.W1lN`tEYsרNx 6 x-<|y#z| G}3t&XQ{xP{GX|1>"|5ᣳ}A-&O}#ʝJ~r}<Xi`#5Z-W#ԜE(뙑eWق@4+X(4pOFܨ>.Fn5]-m#ݛcA8hdWծIO: F_=l5l,蝴R#ܚZ2 產9܆WpGN4?FSS=5<;,Ɯ퍐#Йƍ8DՋ <)WŖNvpF$>=˓@5v,A#Ù~P8LKVANDךEޥ=^.4,{#YTO +osP>j _kbӝmSewnhJ} p#jl{qm[|roZItAq~7u\si#ut Ixufihkjmlo]{n&qkForZsqStKIru6sw"t_w ewmxd's@ftEhuNEjv\zFl[wXj'n#xNYoy4HGqmz 6Arz"?s{ vk{a|adj|vf|h}1y +j}~il}Xn~ Gp4~D5q~i!q~U u~P`~Dbe,sg^wiyhkTWmnFo&59pz+!p tγ^}aR ֬:ڕPrXU6_Q8Z}^XpjCNd1dD @Hx*55{he5~,tUs;GyQF.9[YTʼn$fW`60|Di]FJ폌t;g\Ot*hx]/G$m#iZS;ڊ{s7K.>rv:܋¿zv ց h/1!y[D2j䛋 ~P4W?_Ia%lM wO ]mk~絬*Q5K_9]]V0c3KxVHK-/DP>H\/$iv",w ڬ(v ܳ76Ye4T" c.Ɂ\ 3[5]|ޢA +fL2`=t"C_P(2NW>K$ +Iy(¼=鏰5#Eli+qe#3^d]$ h7F2:c/۸# KBOq vJb;\VI; :O̤Ӥ`_ +Atp5X ]}=E-c&%k ~(N[঱) 4⧆x W@F6ȩٰuf#O~ W+ y_#Tw#B>(fbK%,rИ5yS02xbymbE##@ 4>-4zڅhx{]8)9lۜ{dX+$PV?V¸eexoz2u4y/o;I;,QjUO#?w1>5>S{)4\s(nfY' \[gv*!Ag6f˾NsN|r0q4Jby@Y}LN2M2G2+K7W <$?ъ0Gy+)~Ia/G<(z@K8;HҽYLIM )aQD*W3[Q'g4fp;&]It:\/&S1NbXsɣBߓ#A_3qnKnBp4E¦WعK%8\8{BOy$X1K!Cܦb b9!]?z_h8O.ȣmzL{8i H jE^ %g{2ekUsjOW W,X\5h[83] &ӧ~j"GmmnWi{^U_`LfF_~!q%>ߘu  "A6pGK1?noAV7nb֭J2wlk11`O'(S7JiO.v07U筂L,biHb ?D307!iX 4{/#R& soUAaW ^M;ēȋhmSNH>5VzgK'6J~.O]PCKCDkU-e' +TM3U$o;* -(oAnUqpsz?n 46ڝD%.C kXP$,P~ I)ldIN?Apc\\1k?6JCѩҩ9i)Ih_M͒'ږ6syuV*s_WaOUcJlt*! GcP,Iyi&Rae@(v\ RxBڕW/!GU,OdرAaV\ǨT0n|z E:G-X23nEOBQ`EH2ߊ8bc:t-= 0X(x6Ctca$CvnqOIl lO) DZ]%nbJx\>^O ~Z lV+Bܡ|߫8z~ܵ\_jՎxVGR?>4ցa?xN }g wFue>E'qʮvl"h(6xDQJ8PUd +/T$; +E1TIYA:H9>`'rd'G #0k6H,AE7e %a1% J"u|L8>b>_a~is[|3J e_*$6Rv{ݎ +|.'8= Ѹ)Î̥x{*\9RkD.25t{ʍoum xX%+0_NjEG7Ům}*V`JÖ2,fMsқE_g'ڷnejiRP GZ)E[Lёh_i"jeڿgm-&rG?j-< CNIUq-*lβEmS P""ϛMήӈhG#Gx\{"IaԤg@ry  #]3Ý HSGrDDD7]85/bEF"]PuI*2,[VAGBx͖;h/TZ><a(XdLg,hC~DW[޽j}2埶holpQITVE)\`MBU ^r"9vux: ɋ4W.Q26EpOhb۝{UȢ68dC]X=_v5oXk)aYAvKU`/IS9}Z=U4=h(݁{s07dZkNhm"}&\I&˭ !} v0V|bO&8>A 9Ѵ71iK]"]_@3W"CV}(s@pJvJc>a54.QS2ǜ(1#ZoZe]dWP_ֿIe^R-L!VgFz'j+~f]@fgy$#hw̦<{=IնS 9޷Ȯr>.~i-14%Q,{9&mP5&SS-\t94! l HˎrBSfӋV#aSL@Wb.{Qi\B;ыudqw0qecje* #3LMV* D4UA@e#CH `2_򒼑e(T-XQz=Qi-ZkUruz[-Bv )-|-=]󨌖d?PM;+{(h +ؓw8+x*ր!4Eǣ(ܨgè (1[ZBU/Bwߥ/ +h[t]<\,S +;H%JS ' aRWIzBr2ɑSads|b%P&Rdރ |NX9,DaB㬒;܆rKaH(_/DˆlYDzEFs<?;%-:m+ Kk)~xsnRB<Ÿry`^ye!d$_.\ +B>ق)p]4\RYNYenvV>2H5;qз=S$@ Ju"0@Gs j/fXfV!옫*մ /€,+ +]?TsdQ8i9CЦ1xWvWuZLOoeb0;\ hrC.LJM_OՌ5 NY@8oQ9Y7g:m]Řc pcMcu\Oi +h)%L۩Z<ËBMg˚pͣ1ZFx~|I=[BOIOPԧUAq6ڼEyio"Ebg7h04FnQ1b<IT?8=DCUr7? +sv2BԬ%F`w s0/Bw\CM0A& HԆ[p70NEӜ[" [2,2xKȈv@]uCE޷TzȓtST8{C2O%.x{)w95@j 6Pc@ N7a.% ֍.+:>XRP:UH(?˕7O.ȑo%[3ύ^D`S*7_&JapBc:%f1hu)j\m+;o: "Lr 㒐wPE}ReJfBeh9j1l( +npr Uu*Zy~R!jJK1l9BCm9UoB1[[p(trȜt7ěu 䗑xDÏ| QopIکqAr9ss1+u1(؝vxϛuwty 3{U<~WQnvIv:vAh]w99{x1ys(ɜzd{f2|} ~=} Q8{I:{A-.|g9 +W|0q}(›~4~s 3ڋxЀPH@'8X<0ϝy( s( -)PJH@*8a0( Ӕ, jl! UP1H^@{/8~fB0 (ъ  _FȀ/OťϐH &@=Us8N0cʎ|(~ L S`ËK Ï"|ЈvUPOdTGĢ[@ +8'ړX0E!(jk , pd:jkeZڣg^iCaLjdculg3eneiUplDqn3rq 5s0rw wtbdxdBfǒf]ihhk`tjemydlUo~Tn4qiCos52qDtqru qv.*rx +YrxwzRbu]Sdv:fwyhwkbjx]lyMnz\>Fp%{ -q]{-qR{w |ա3`~ b~1e~]xUg6~jJiJ~\kQ~M9m>=n4-fp3Dp)%u-cgfIYhQK WS`e)ꩈ X, (C-(8B {so !܈ WxĞj}V=u=p|?~JuՄ9ҊMnUMI)8eռ`y~~hcԏ.6vI6#e6W|]Agp-U&SMh[LӮ vuUnE![sK]iR:tP+gp6U~U/~(Cg=yhжsP"%/V%5}◄*q0Rœw0g3ƆoLD>>C|F^ 6oO WW.!$Ր OԯjSD-o!Z\))2ege.˟ 8PB$Ũh$v! + +fQojvlK|7%܃(.CDZaM\)>-́˧!ct (Z1n{sBsj*!-QU2!w\h?||s:#^.#LE)!56Fy.[%O:"m].^(-#9UdiҰxiGMF*]As nks!Yv-XsN8MU-ɉF-@k*uOէdB٬3VxeuP<4/۸X'ߘ&@\ٵm'FUpW?<]U4fˏ"VYղAkJ)n +K{vʯl1krȴDnʚS}n8)re]Նl*-QOdW*b@8~(M;H?e>amаcHlBy>ӡ/ʰ%iK:B/ߒI +};p"[՟z.Mfہ1vX˅\^0S}oe4FVZ~gZxe FaL ˮWܯMZ?Z[Xj~ـß++V!+*8X3 +syxhYSYhO>yi*6D `R}䪪p3=]rM>\ ^9#&ăOennfj)Ĩ4_Gg._'HBhwj7zЉ5T>)̵;*lSTmVlؚw +Ԟ64%O5:N '7Mu^.V~yG޵wBuh`4K%?#I>/%O +f c~՟%xoGP*/91KOGcjGc噉X0oNE +>X Jb'(%7^Rg#=X T@NKdAב!i0j-;2nLtO/o]eJl~?'{W x<}G:Eo-<e;Ѽ$Ϳ2H% W!'E~R'~cK2Lf nZlB''x j3i%y15Dȷ"@ 'c8~<F DWxwŇ0C\Tkq ̸ lbLst'FL<$&ec爗I՘=r_c>Cl)1^шnjK/׶PqB?]#-XkFϫ[ЃjϨ9Ruf";!8(ae E;˲Н]BSȨє(C HP +iw1#BmÌxhp;_dRJ I߰!_cΒ#Ղ*MWw[q#`~]\zii&Nw-;e-=aufKP;j WXuXs/zjՉ‹\57&Sj̵4 h3VRf(.wJgܺ5-\S ‚zt.1m͝_n|WX0R:rV4&DYovA^iTm &I5&`0dd(7FؔaXv[sG&?N}kb*7\}O愫V% þ>еK%J>=.w56]-8 +bsl u _7L^c"^hϥQ&RP=FeYs B1*Hյ!,^Xֈ6gv>hEs׷m}NWp:,g~a +gRQi"hū@>"iVV!dKAd2)Y酼8ʟ"/CgGdrǝ--D8cK(>5!LqU +r*d$("eu1Lj9YlhW ߣRUΗ4K !6=%5MQ&3 +s&$&H(QEf-1n%/ش‡i BnKL@h&>W&Ap[Z72(MIIҩl7l'i)3KhAwt-p]t"r"k;)%-[[_px޳:iqDG_LÎ̭q)?5u:gm/H "ϊU + +[Rb'3 )m{7Lm(l,!;k-X5;o)0w#+fk[ԑ<c6[^ h\@6Lzy: VZZQ0!V7߯-i7yOܓ|]lrcmY@x:I{sT3Uy9bWͱ\ȃ :|@Q*x%MnU͜ D ԕ{S˜8QU^{v[>o!za^5<zsr +/i DfhsSNF|QD1_-&AʘppL/lh2t3fQ{ 6 + RxW9)?§Xk%'_nXHG)_3p<Z i1TU<-t9K<TWRA2E  =[JW#ʼnPZw̗O{T[N: )8r.F!>2pĢS2-kBؖZ79=B)ZuRzt+Ey/Gب\rLiqZ-0  o^njCiFy=>2ҹ.Cv '[jxKuJ zTEz\qP]ټv|}%vOiG{l2FEYs7\"eJmA:}K:Al8ڲ65#feBZZޙ DNC@@ăLY+k'kwڬƮ)۲tl6Y{YSuY9[;ܤN iAEOX}]8E2ua<&"v'ĹIpL) +LWҞ3]LUiyZ _|pi#5M>AV@V! + s)lx +"hqblyR%I@SsbO(PIe+{HĊ&ӽ _[OBTF]|}ہEҷ-W 7O ^b:ޝ\TR]SJtæ|9د"cl 1V45.^z^t5{Z\6]͂pEZ[<-V;s{4%Ikp^?]ir{b pS/j8(@+Ԁ` Cr-L>Uduea;-(KOsaU3HEې#ce7gc?ݛ@fXO+ExF3ׯD+jT%nOgkGW%[XWw$g8g=I2N''$JxXI²;co򚑄2r%C[(f18dav1O f!}y︆d`@Xnd.# 9h-e12IaX\a :D&n= ~!mo/p¬鏆=^*KA׋oLdI?$%KncTM?UK<]VT=Nˆ^Ki+y*Q.` @,C7zuBz U8@îRmF$+~P=Vhʍ*zP/UQ/mx/N2Iyj>7K.g:R 0*g\rMY~il_MxĪSrPSwz6c9b Q6@['g(WZ8DmkIz8^":y@N> \ڛPay~+(a]3DŽ 9ݞ +nqwSwVfj92DT1DvPF k8b~;d]~>n.!NyN7NXəC+T8NIQS`Y0?4 x<'Z7̃g!mDmm6ߑ Q쬣?h:il2vNR? wϢEQYN,Vo"~rH-ķzte>P7ϘioΊdXYq[p0VkWUtڰ &K_$k8d0O#VneYH36`e. )2ZNf2LS~]@Ld*Jq7wE1-S &0)xnZ{DeYJ], A-bt?H4/s+5iCD9ڴ$"!Ղ@UDm#r5VY5?bkwp\|i_91:eM4m~2@WꞁlZ틐Vr+S#Z-^[s1;QثemYeֆ$9cքZ˺eM= ""Jy\@ +.lsMY#q3'dy)ZmŴ-IF^hFgmwp97ĤՌ^U,_{ܳ[ǯyTM'Ӗá5<\abcP%:9;ӉK}*WP­3`Ŝ(jJ:vc3%ޫ$(DJi}f~s4G1x"n<rz<"^Ֆux371|;qˁZ +8W8SX.yކ>MXƠjD!E8];SZ]O!ﲶ+'+{_"6@ cpZDN.᧩X3Agis$ 7 U +6ޢ*$EtQpj\ bnIH_xBPe4K˜\FTQ +FעkRrhiq< +CӰ:5տ5<)J)79[ |#{N9X2O=xp?AوQc_;|0,QPm Yůh{CM6gk uZk9>gjc:cY[.[|Uۊ9'a%9IOeUN97%|\-$_[׏Չx"e1/\gUjneji˜n`U[ %b%?dw}Zs,pvH[xr|S%PE9'#.xjy[/jm=jݿ!i<4]lmuS"l% :^hh^ԥj9ض3t"w݉e dzv~6CD],x36H!&V>;[hdtٻH{q d|Y,> c9xD$[B\%xLGԂwYlAMk2 `jP_4 TG2¡p[st?pÑ,4<qqr1g.56W[yJ忢)[HE|ou|4.X|$^s6lE2C#v/^X I/ӧ yD"Am |y̨,̬MHkU]{i%鉪Uo*c`YO.ӊ$&1P/* _l4 +qڞx 03&<@öAoްRӉ p-bѿ*pq&s[n)kŻ뚒ӊ50NC q,1˧ʯEϴ3T֒=Eʳ +_s] ʞDCheG)I oT?NbEܜf+'}#hX<'{NfHs$*'Ofb:JCi+ά֯cXgd2_ +y/\"çs T=u^an`. ґk# ,hs,׭c/K_jsH;s]d72߰Eΰήm{KL41#_myZHTm v3n8r4aᗰ3HeG[v;#6_֔>!IFQG '|6,܍7Xo`+.8aycM}M?E$D%Ւ۞M_M=.ZT@Q(KC[Kk%%ɪos<˲Khhp+PlJn i;YӎLucuj8R%lWf&EUC%X[9ᚲ~$~uۖ0Tq,D]S䀡m{W?Dn:V,QW +N*p}5y HQD lElY  ɳWd2DPpQڏB=ֽjښ‰@(={zW7?rv﬷@c />QhxּĽqqѻ?V*w}Pm0ЀJ:# J|)|)ǿ*RKDžQYk(PԱuA=- sIfXX@x?X<[Kz 'ᖔr"^lQVFJtJĹHqyB+h PE+(@tjp['y `-J9:ޥv]DWY94AK+EC>;z\5G?Ko 9 n-,@շ5^"0u;^=I'aEI挪(Wζ@_s͟a8+ A e5mu݋%a3mN&Rjoس?ϑޭg5hRRXL@,L u`~p),?CSI[O܃|_HKES<5JE)q@Gŀ!/S oz.A9"*Za[)h_1pl@`ڞlHR7x!l~敟 `sYC`OItny)ՎQԦd +AF~+Cc9/NtӯܲavUџ$MWM }ō1hmohF^*; q'-oܤcE[BZ[5)8!j RkIT}):Sה̨]\B`~] +4if$"׵aR?\]i1`qCC6g~zsə³2_D2ܪl~\ܟڀVCf?/f2]INTx9"Wsu.BuN"*Ţ}U4LN_ψU>Ѱ$%&]*_u7q28}Gjr442/%dt2m qS٦#;WC37Y((Z_qN՛oKc~V9iP0" +D729X.i' P# rCpRML޸;a7ʠ+-7c|\LY05|-lŭE0ERJ8:t;)adsNr j,܋KM3 g3l+\do9 c6 ]]7 rPݰ7sƺtl˛NYxnIFaxKX9|ޤpL.6"YƯ\fbl~#W.v ݠly%yrބöuW. SskhnsY'{[̅d6=Q20Ha `Y2}z-j:\Qw(LkK܎u3Q;OX-_Jȵs,ӢHy_al+I1\vX8Ɵ?3E xn>P0p_c4ET~OSؽxz!^߮nYn,9p^ƸiiEyS#Ui1FvHo6T_?SvSthfցS&+O(1;cQ.a";=JDPDcL&aH'lZ}GuyC cfBׯ:-IPS}*}!G{nu`Ev쀟i4i- 蛨I 2@""'t-æ՘Gj1#@ffkB +p͢Lp 8GVms\iiIIWBO2zig?UYng`N,DLs9Vv(ؐN\+f6D)->Èj7zYO3 M3v]@Ĭh~LcptGk4^ZbEJh}]K'eM=ƧYI/ #b Id}H/0,1hg*%X*$v="}U牮ℤu8QE S!ڑʉ!J%x-荺j8FD +q`5zkE!sLFI{ML&ًEt:pbi)8Ϥi/%N`s:Gu Mhp_y4!i2+ +l4V?lT4-w Jj?ƕN @hQϦ`RP1Ȧc+_UߗTB7Ia -P` &h +ަ^YvUYTWv-sVT+Ť`()z:ܚE<Cp BT_ "U/<,V#J PS0uF5E@ Fr(:Z'NWW8\[ P%BI m,3K2i+a) h^VS(9sP.D}ƴ%DfB+҃ +-6 +ڪ K(ڛt[ַ=sWƲə0M9fmS-E5i~[H3NKt-dI:;D&:I4PEJ͛$n3%lO +si9պ11BR:`.nX?/ceDh#-/~xV/FS,jLH|h,FB-AfC"49<jY2hďlBV햎PY}`4щD/P9[_񚏚Ή!3VTSsgO߯!5҃N,MC,RXQjT_Tښfbe_OJ{|\]EäۘɊm+>@3%io}Ԑ{@\ƭW}YM]LLyn(0rQ>bFH<)(K((pHOK P%:HBOTg=/v\e )/HŌމTyjj𔎡bj"!N}ܷ! vG*&)H!J~NN3wA|Rj&}z54E=sWG>Rm#,RQm:{Qưp>mhVɞ/ Gqr +Źd*G>ꈚ!wM/U?mvtKZȴ*;FQ3lI(Qe'NUܳmym˴+[o)>3SF&׺n‹9@-Υ/C>Sc%R_k!xԩBn2d^0Fy㫀h|oڒL6ǍB> 4 +6۳+ wկۓݏ?ݝR,R6dvCSO\e=~|?2}^k[Ez+Q f۶ xޤBB%],]`4M/%Cw)XMiz -J猑R/ܴ łb掲Qp5/_^%reD]}&g{ !e 5"b(,CssnօRї+cE)Jzo^.Mu?% ZN{J1FWś5\.9(*7Ǖ#h5WUL:[%ΑHۼ|R2I@wƷ*X[J:\ר +㉙"r^vۘ[z1:._%DUkv 1kD{$cf4a5_V}ӌCSNp0@jʭ4'Ua([b7$ p& +sn^m7&9都،_cDUPlZ[ʳ>${;^AǑnΔW{CfG Vj<0AP\2{#g? `XH-)7ٲTvTo4n/iL >f=4k=Èkԇ>B +R:Wj??8T5ՁzҸ9Iه8RRhLa<g-Osy:@Ɩ^gqɽӵI%*/9b{V 1]-6v= 1 r}ʌOex-HS\+MBɉWPGIx2^sMGO-V]UD` bOǞ ݓ㜢bZA<((&)<I/Hpq++Mt}B?5XHbcLb\k>Ex@X(eJSq!dUG3OMRiq |-!at.B.ɯR|])P!dHTOk$'QkV:~FnⰖmU W*qCZ\k>E +#ؤ'k#t]6M +^qwQXoM9CPAQ),go! X.zZ,. +ˈe1e*S%^[W5xQav53< 'xJ8:b$W[Tǘ%-HI;Ѭa4²6ܤ8z0҈p̩K{oU/w +K>R,VR;c=eNfMHNI?=)P7hkʔ]i"r:3S8=3n뼝X6&ՖO6O]DRǩGvT[UCay;쩢}.g\ 8^O(+omd)Ke/Ψ +W @4)q&*KJVo''7F)$b4^RuHUO0b +*vc& _'ddEP[+~!nZ}A`a e52$mGhTuxoHAR4F +u.ؽo {A6 +2:JӘ;rZ9C7h]]yz.olcG`z&y^F/~Ƞ_KAƧ fZ:ol#fCd$wg)xp{WJR;%=NH9ﵽFI+dvy ֻ^K0Ϭoo;X2 -G4KAĝuGZ5uQڛAmY@FO+/2vgrZ)*8߬)hR89\` $u,0(Ԗyn5bcr*bc('X=-%@gdM|eODs+' VÓ˶z4oПXS-տl1,ddnc ڌkwDu![M2$sV}@P9x4xKD1QKξ;t0;fN Htݰ 1}-_Yv,}{] inxuQ~LzC;5j_:O᳠Gʗ + *hPV5 ohiT$ǯU{O`[|qmWհ=$|w2gVkiVy4AeLRakpWC4tzEEgvؤ2yA3T8#)RbGaomUCuHa!n@ȍV0OlVZFkSh/9L6A,Q>ceZ(kWaTw)."1ߢnag=c 1 +R&!Ӎd%WS.Y]-㐧qbE($L\J%+49-MQ蜧H}1HRڂQɀ+CJencJcrZ٣}^$?)CL~5cMBɋVJSk`!rjY>E]Ϳ hC5d-~sޚ+2f;%l<)P,l\(N5زM1bǬ揙Lq8!1,ws["mqO~[tY^]Y|_~kMlkd&g~(5M'Vڔsm|2[Z]-j㪭<[鐟5 j|s$N;xGݮ^Zs_Z5PMYԤ_<]q(MO>\_HNW/Z7Buvff{R9VܰK [fISB3E;F<BBF>F97g9 +.V)mvpx"#nɿwqN-U5UqNs\PBQB[9zvfA4!k'VcdBuUWC~&?ܭ8ktJlf!Çx%< +U5D@a-{Q"1uE⁹&)?Gϳ7bɓ2`b<[X*v(4Y%bAi-ߠ54_L1ӑ~Lz e $Vٞ5=[TĺnqA+ +,} Z/xD@'ʻIMPO;k( XnfȇE zX,oau +)T_[# Hc (\8 MҫH7ZkM(K|)G^*QŤbV1Tڂ<(nAHPX)e";F~ 9 ztybTނ4]W@̆y!R[sdz|T&{}0G= +dgn=UTcn`"Ahn~k{/} +}Z[i1Xsɍ PSeWcsoD>/Dk:=*lagzN`CCU+kSiտ< Y6QU/r,gF<'H +IoGi'UQ2PؚEqmђO"ٕ-`#)t˴|7W2c4RruP>v +R*\a|k(㍇Wdngt~_hרZahGHU+]5T:9HcG~MLߩ]B5r4~ΉH օ/Pf +O(,Ϳ~*w&{,;>UϔRؿyXTԊG=d +V^0"@2 o=VL2'\0} Z.D"O! B!悰U )P)sy w" #|8/Fs6 |l9WQ}VөD]3n$3 +O fu[}M:L"C8fXI]jczI<8yS);GwwtƱx3e᫳2fשs6yZwx ԦҩIC_MB?H)]iRKx9e= {|e i,nAspTY꬯jzb1|#~6[(4 [`! + ."2.@HHɗޓ$$0PԖ{VQfHXlSD3l=;92v^µŁ`l'ԱX׊w`5qꨣڌ:~!vbht8x\JpFG[zP9P=V!:[1^Lע6cTDgt)egS:HpK>\S4փ>jo8D|(-@7*i cAx6Rw Dv_+h̔y յKCF'6^8I6k|.,jU +x4>40wPs)x|i5t{.ڰ{KJ :u[p \A Jz!`Q,Fiٌ8D?GHR; +[vq]'UNkB%?2/N,w.i$e~ +֌+3: e.BC1'N39OP;6Mz%s5[2`eSO)YZ6֩2nPDYY^gLGVɞcdIvuxn~ z똝KvPG*KsPydI=X&(I6SC7"g#]V3 NyjFo7e R 2!]$u#?*^M38_O/hPyn6* nen"°D shF0hÚc^'ѽBB-BP ;܄)WNܩߒ(-k!7o<&X7n*,4z%_=^ I6"56`F_T9ܴGsXoM +@FM1 + %Pw9'{l=nZ +ZĪ8njŢx\g}/N0NXe0Bhp]*lbNezW,Q򏐇ҍ*2er<+b"g!L#@rH +H4TGDR*>]&_ e Kk +PyP*Vo致ADZAZC .Bh3U0oPWT}wwI^8QP@_M` jݸb{?0Qe{DYP Ah ::*o=,:IsE3d=XX4?tS땏TIoCC#f \&IdR + C&X({%彈>S©!JT*Լ»gfDWCJPǚ5(ZLϒd(PwȪ5hTwTSo3 E|e8bvmrSe{9#Z?Bu&:f9I2 ,,H(2I0싟"[ȏX>6 bsx杴AWV$|mٛƚE<֋)zf&1HD7c #Xn +؍k"(oh3.w榈gF&r߆t]炻S8:c~_X{}[i}xLJxy_FopAhg,d}'UZ8 ͂Z1v4Ա6I@SؒӁ0R;`m4} +lQic5O򡖶c0g-űZ;wN!\ҝ?l !uK7#ө&n (m~RʝexꟵf>&|Igg 6Ͽc~&BNŜmȓ7`s2tIaunv:c* +zSҩ3 4ɛZmhe7]I&Bߜi$/P:7ji<zՂ O3d{4ycB>"FMA zK@~ ![Ea[mkn>9 |^ *Ř#tÑ}<H:S`9̌lv>h\4pEqyIu}^\2agYs&9~DV =W?8K{Za׷&[]P$`)9GݒFS6ИHzԱJl_Zp7',n)[O:kL8r 5l6rrK ȡ@}Md&pJ]zѺRU*RD_UŃ/y>y:?Z_>;6kfD>o]BnE!6oDYb-*c,{VU DkeQstl5ǕuRly"1 7YZ +RR V=jeپp@ݶ]c 1ij@#-+g5n@&efF}܇)2W + +~U^rViĠؖ?#SNf4sNJjKtrBs1t\ Vn-WT߆|pUa%jq.>!=NϢu HٯڥJ{e^ 0)A !@+b>"I$uAQOe {CrIYlPfh.<*4M_hAtr&Z^W,1薔#cƤ!F1G&yʌEHbh-¿$V屬y|,} XG]ߵeJu{py5w@]lq kAWy+ۇOy>muIMG<[QgD[0nIr+gKs`o)1op؈{JS6G'2rc%ddu*I[=*ƍ +u#jM|G+Tk*+g7Ls0U.lf!9q]gAiӂb1Yrރ^YvqM( Y^;嶧^GFxIZ*)zE b2Kύ R2J7q/8H;2 ((I ˥y]qj)[/V }P3oppsq~ǜP<*432%)m2sx}y971~X|),4)sk>TQf}-37$ö˲xIb4OxPtmNXUiY6^ٗ`K΋Z]I8XԩWsߡt5[ ;|?ݐh1S Q 5#A?0M:Bg/t]ڐfbNB(sdkBEu8$FxM;-Cfr4v0ࣰ@gVW]lB+6~ƈ=Kchۄkz&{nj&92ڌ.ՠq]!T!_2ؚ1SQp,a>~~)nZd|,&-AB "PwWl( ,Uz 5K%!DYE]EDVPOt mQqAXx̛7;s9|1*FJ=#ESkh aJڼ +AojJq%{Zpr?^lTcOVIG9z9{1!RSޏyk\7(I&dca0)>wM V{V+y?JEVH3\~;~FC]I<$m %+CU8S\ +pjƷ +i:T 7u8/ -O_zil,+'u^|,%Sbqz1LFt!&8t -KVo~N4Ғ B'~@ u3j,'Y9 +)qs~n +ͳs䖖')r|fql6s#f!xyu4_^O֐#&rw)6AZ o, [dm +rS VY< SNy>wp +zm9 1\09Maoԝ>jjXd|nY!^1GXYUaV(bpm߱q<'u KŭabwLf#fA +1 @(.$0cdJaFQBZU{c$+h&1Ľ8*cA4S"ӻɺ&nǠ8[E7׸m2{¡ 0\½ȏT7> &Qߥ|> R#` +cjmZҒ՟U**ByN,GQh<*.{KTmI1i!(GAO!A,9pyqX)0qP5T Of@`ͯ8h+a8 @;48:/:|@hx^lʻ$6Xqc<y/# `}ߝxC!`08b1 tT3J||5=sEI~*(8$K6#Z<+ųmָX;{'WI6FjR;#sCyvʺ&+6(7J7-[s~k?P]r]v7ir7Ѿa¿D`"c͟[87S?_MiX\FZ#P#jJt QSKրvB7K/Hoǫ5L +LffSV[uVC-6k!7)!NjZ҉LqrF&Yk{<@\+$;rH?<@0A%BCD +EEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abdef%g0hdۣ/Zߪ ;iǯ0Nlɸ +,Os>lśHq̙4WxԘշ 5I[lzy`F+qO, uO)lF!gD!l%m8c , + V # g;^0{N"qE  !"#p$G%%&'()j*L+/,,-./012p3\4J586(7889:;<=>?@AB~CoDaETFGGx?R@,AABCDqEMF)GGHIJ|K[L;MMNOPQRuS\TEU0VWWXYZ[\]^_`valbacXdNeEfd(؀+ˀ:JXkeVtA,|〟~׉~ˈҦ~ч~󆧨 [56j_M.Ub@p, w$}ߓ}LВ}=~e~#z~H}~tAi8~T~͆@'~2+|םB|"Υ|/}s}F2}||}h,~S~F?~p+~| |0|INK|gϣ||ݕ{m}+g=}S}Ҍ?!~+l~aW{{P{ӧl{|'w|k*zj|_fo}R}q>}Œ+{~{J޲{Y{j{he{n|y|ae|lR}>}r"+}D{ďa{ȯ{δN{0ˠK{lv{_x| e!|kHQ|ȕ>Y}%1+}mzhz8tz)!zU9{.ŋ{q6w{d|EQP|m>-|ڒ4+}3zB z[gzȉzNzv{;w[{d&{ɣQ |> |+}z*z|ōzNz ԉCpu>#%4cV5)jjJ:6.;s~jj2ըVCEJV+ǫ,o]i 6(S{.}_gH]W-Pđڬ%AiM>N{+q&CUro*pHh m7:BO"xQOi +a;|q7bA'):8%Xܯul4 +}D0[~->IpcOYd1XF h3SB4rE:"<;$;:ׯk"2wP\%U:%#y+hAZqgwu" {^!xH_m0ξJʹ(%@h3ҭyx +1@]!],\~HJ_? L@ M)LD"%9)ey% :h~!> n`NN<ٵ/?Ss{=ᰬjxkz^[uIN;3є=&^<仚 o҂WxM<iOC/2ECm*wdJ'ni}gOٲx1X{2M+HIP4#x06fV r]2&n2F߯dV n;ʣxfI;Q5Xm`\sc2EAV ]+< =.ಈKqytHK?dy]D{irn-< %c4VlsNg06Oߎ.'p dwIsmSzWzWc (e4VT8k^ԨxD͉I "ǍLŋ]ؐc?fljj5[c/ +ʯ]1GjÖNgGW,T$=]EN:uİwv E{䱙6Chf()VލLu&oޛ,fR@7W}(\N:__zQ> +}3;/e3ކTgMN2_6Ç=^9ADUѵ,S  ׂT]DA`ATT%L3Lf2i$!  D +b{}z_![JR?&Z;AHQan@({.YOwL/ W qxTd`Tk  +18mL~H nx`,F}/ék?٢ɥ<ܧ8d~G% I=='o\*_!9&(=zN4脹QQy,\e;B*LM//eG9?~?&ʯ -8QWeH. hU61f`@T'@@qˀp =­ ځWTz 6_B6P=)O-e7Po-&%x[A/ɷ.'c叺O( !#9KM?!׵MځZj6wu1g+m:z G ˷ˏY<"ExQtꁷ JJQwCy}yy]Y[B𬋆MGpm=>K;9qw 0\u^>>P5Pޗ4d},..^Z)QQiZokH + 0Q@s4rStvse<:lPYՒ&JȜ^4lM^1>Q#f/d!rE@*vNCkVT4*HyXG0L&8c;2: &w<-xe +3lX9cŬ* +d1zFzii0k + sʮS&0g'ǮSzO8-1vԪ{Xϲ5'&'P% Zݵah~Ffe-:K"D1o{|s6ƌkї2V}Jn-k_Gbʼ 6O+*Υq݋Ot7hgݧLK`z33tA7ʘ")>]UכY~ECh{,}4~O I61~W2U.Wg z wr4)6./s>LwW ^:9ɗ:- $ s\tPN1~C_Eb#^a>녻\6y5U׈Tw<)5>kN_*0`Gk;e[eZuNdO7"&ݵA|wpL: +V^!DL:IT- +˯^O8n,t +p6mreYME%wHҮS&e6Nx&Mƀ 0s`R#4l'2n^M\34\HW҆c 8a8m% #(5&^}?q% |^_S&5c8KS"C#%%{$:w"Y @'\,U֭I+Wfy/J깜3Y#q$tkH #ap%Xҭq_˾Llq~zv3^꥘C>e~)~ +?b#2i7 +T~-u\ŮPC3%yZhWr 0 Ulg8YLGBZ9@sʤCYxmԁw ݺrUO\ATDN8I,~,bFAWPeW3rReZ]< WݕiD`6pG,:l a'["[):ZɞmTu]RrdZ!?QipvJDSyB$#уQke7ֿ-^]N]mcQ{vWQLBc^6IpgMiK?=9`Un뢊g$ܕKVp jҙk<|?wbfĩFi ȫi vX˲&e#Z3Mt "hX xHur@j{)NGoAe4deщYZڣ e"J̴7x;buYMI :A4M +ce7F +XZ1 +Jpa;-6{\JdDӎ +aM'UL7,NnfȺU0*B7K8- +LGA_֍ɏCmɊעsO 3~6lMs8X?נ׉X2c B]UtGݡUJ9ܙJ o>.)Cd%ޠ:V uMt лohܮ=ߢܘ^HZHT5&{ʯ +|D=๝9_B.R?vup=oiHӑVuGU΋270=[Ǟ$2øR>6ǦV\l;Z܊V +Kv6Iz D[BGZO7e֢&[)\|Jd('Քȏrv!^!qKy=#ksbh'9rsrY[klʂ4jY8I{P,YM⑁ PƜEB@J=GLu,Z[1?+4֩}֮ZFOQ-81Tzw UsZf;9-rI7x8.ԜY~R8Ѳ}" %Ռ,GAW"VDD_d5৪x CaB=H~m?xH =EKEWOTv>}-jNH0sQIFa7;&1{'"kz,hV~}Hr[gǓR[[=P>F*M;Ec1߉'ъ~ ؝,r7MfGx[הPf]E;w1X( + }vWqĴufKқ[0\{PptE͞w;sD1݌(,x Y53Yh}qFeӮbZ̨P$nE ;`Α1l(I |άpس.ejZsOEss;Pjh1 m(b U>|+^p~neqZ,1O(EQa;C1(ui9 ڈsZ~v0}jr}` +}U~BKg~ATdi76.%Bdfu +jl_޹&U`K5A0.7ueg.&*%;׍ɂ΁9˂u;jx#_TQU:&K=Aτ7i.,q_%[7)̏#uEmjg؋_U-t|K +BA%7d.1͆ +%w*Ere u`È|j1{_r厱U"J@pO7bS.C%VŅ$Wu ܗQiݼs_%2TǰJéЎ@飹7c._m6%4pڀ2͟ tN i^ⵗ^TgJ/w@֣$7d.xՊ&iAwPGtsˠiMVD^T]җJ}9@Ȣk7kv.J&GN֩Mt2MSiѡq^YuT&?MJ]@7zp.ˍ>&t#qok)shź_i^2SKJA@~7{ .Օ_c&A@sh ]곗USѭ\J+#@7f. Y&o |zo|z̑}3{i\}| )}|~ }/{~K}gn~~*S,~~>~*(~{,x{o{ta|k`|ǂg}zX}lJfB}ł R:~>L~dp*~5yOAzrYzC{b{͈ڌ|4y|e/}Qa}x=}܃*\~;;yTyg}z zsz{f=w{xd4|gP|=4}a*&}׃lxE؋xΞAyJ"y!z5j>zv{M*cQ{܍O|i<|\*}rhwTx(3xy(NRyƉz@HuzՔb{nyOl|<|*(}VwՅwx'ex|,y<yНtzm}a{ +_yȤ!Mz_;{'*`{ދ眃tx؂yvz+9zқ{ˁ|?ur|bAI}O~?;ހ~)lẃ< +D#;큊ZtLsa1dN/xN;SY (5eڋȀ!Fvh$lXP+cu}*C+S,A@OB!@#&2*!Ȟ*RXQkN=%Ȏ &,1j= 6>Ǐ@3X-䬛RK>v'A5#g@x+7w~dCZȟB|s% 1 9ōA䩝SUYY=X3 dgcL3a ͺCnԔyr +lf;~7ޓ~~5f$|ZfDu`2@$\]G\@]zTe 9 4[y#'LY{@m!c>zn:> =.+E)pmp'^2%"qJl?o[:x``:X%>]RC K_ 8mI :u$iG@3zs( PZOr_xs.M"`/WS$nw",8X40m5<ńo~h n}DnaϠ+lQlW^Sl,]{ v`(`R顷Uږ6H['׳W6!EI>_pz)xxcvL0bquf 7?jjh>?^\Y#ʯG)RBQX ~F8F_D<=v~մgԦ4bDFzGv?VBa_݅Jh3Zd+XlJ˵a?wJ3AjVjIgu>LeX<R0EcrCBqf`cǒ02`j;1;/FPcqh4$p/)_uy{Q4hݓj|ۗ2<.LU$i42"L?`RԺR磇@*C!`(`@,2Dv_/{ @ 2]ZEWARSx*dR*WSq!Ѫ`$r"?lߡۨ,+@Ymyon-rI|Ԛ:Oe)Cd>49l'C{ K` HzZiLZsz.fT";ib-2(!-htB  _a' am/ruiP[FUYtc?&%'#'19Nu#7od%o ]#k7ak3RLhUkobJ2m% }01<:E4q2Cl^^)iZJ|jlk;> OP|"Oƪ/kQI +Q<_CUXyF|sM{v*4UWp`H +0 8Jm?qWߞS|lLwy ޙȫ +NL헡, +l~øjb7*&"4+\rT'Vn\5.q`&s S.R kICwv&[r{k\(1b0@5l@|=:s|ESҮ(/c[e4Mty^@8uX!L*<$TJx4k?.3wjnItv& Mҩc ,RHrܥJ]2`8ZDЎziX{!ZM)"pWXtly@@^3cW 3Z+mNƊW O16 HOl> sC +z!(A p!UjIRU:=ح.?\jDtE"5c9!ه=0 /F3h8{24Ulx @ڦ>_L֩l-@]Nk GY$"N (64{/ׯl"eGeu1Y/ìD6J*%F@M#x|hUGZ-*|>'叹5EJw Ty[uG)P*Gb!#a-v~0w[gcZ9w( eU2CKLM+2sZ*»as̉ͦEǟ3pG(]3o2ڴjyoM.}]?ڨ \4 n;b~g?3FG{(fi6-Q y)d2'ߢfX!:=\dLׁz|WcGcIJY)Ų܂FC"]AErrz{0j2[%by$(=]1l _dŶ yBsWܩ*pǤ +,g,{?//\~7&(O7Q +r# +jk|h?|s.jb6P^$@gH4<%"/+0i0 =yA ~'Y +NxR#po=F͵ڞO-t&73<á'$RM»"0XNG^1D>jhQߨM}&ǨpjO|dh2:'x iT+kmc{d4.W}iK?^-H,Q.So2P"rcWz$ajUNsZ2i󺩢qe͑ + hIGO^)uԿf}C&=44>-=m0 ji˹|\QXt:!ac7P{TN[\{$8nh/ymp] ve5"1 ԇ[SN[Z=E1U( +A%RV*Ȇ ^^{B2ણ𫟠pZ'Qw?ⷛK7Մ;wb] +Q.7 f#D(xabaO"Fޒn:`VuɖTUUNK}!oOrJoaxA؇u/PȆ2-6]*[U;/reU^ј +/.TklO"7{77T4^uo ?yi|Wɒ4}Z?K5ukqrt-D tP)j}6N_߳Tڸ4Iq2VQFޒH@&5(AJ)]?E,{zuq yɴQti_nE>JEWT$mT- +bH|apԠ#_RBfxS)yka +ex()S0I'b9F`" {1ϫ>ʑ[oc W[YޙwiP19b$,&ĀGht~In+d7*' W<̓'Hfb k| %c*p } +d>_RW2nqQُu5f%ďܖ5b9YŔg=0^n&kk;7O,5|Wz/é/O앗1/˹x%:Y0 +{XG(U.vabYG錝=2 D^9'rGL^ ;Zc3z7+g EHu`V5 IDI|31vba0fsq>5vGYyf?B,ѽe91x"wԲ`&`h5 f0ظAۣ]SMC4aZQIPD" B`Ic͛DU֒v#(snQqƨhM^{M 7nJ&*^(,Y(}ctS[WU>= ЖRl'[N]@X{χRzm0WIGe!Tht7h=¥T/sp% k2ADotm 4Py3#+: Ͻ؇eHqNC%{YIp؞ M+(z|= PW0aKFT }r=,Es(ŘVE:Ȼ?pT,CV(fiEGArCj$Qa_}$՚&Zu2kX(]Ϗ /&ōt}*vŵSk̯ޟaIVLB8疨/&ጥ\vHk[`H6VM9LV*Bs6+8֖D~/B&ItЇ^mܺ<'uݴk:=`QV 矛L#כrBR?8Ǖ/' "{ry&p6‚ykey[QzeQ_{5GǪ|#>@'}4J~,d#ˀzq~p ~ey~[0~QCGl>1G4i~,-#Ȓuzooe3Z[ނQ.GB>)s4,?#-1z7yGoo#dZFQ";Gi>&|4ޅ,P$3myıo(ǎ9d쌼Z0iPpAG}->%5"&,iP+$R8ׄcy n" +dsAZp|EPGP!>+5n+,$ˆW$ymÃ=nd8AZ-P}G*E=򠍌5 ҋ,"$ď1UfyAndEc"_YLPGG=65C,”vy$󎪈= +Kxˆ nc}YBPDF$]=ٟpu5,%2ވx|mռ*cr#dYl>Ow=Fɤ=ў5)I),%Bω F$x2mJc?ĤY<٠OFJ=ʞH52쑂-1%_c.syzuyv +òz|wkzwٝ#{bx؉{yvx|[zc|{O}i|nz}u6{ja| N|;}<) }v(ҿw w͇xw8y'yڄt zY`{GM{;4|S(}Qt咈uؐvӫ"wp(hx8yNryЈ` zMM{]:|(|t tSBuؖv9wvxTqy-_6zaLz։':i{(|rtsdydtTu6vFv8awƕ4px7^wy7L-zg-:'{?2(| ޝrήsctnuyQv^pfwIpx6]y Kz9zM({)4rdtʝsU\t:Su gwu򤴁pvoRwϛY]#~a&uhbIQ;5)t'VAZẀ|%搾0S#Vuv?aboUsmDցzA6 hׇ +ƻ%LP()HPu'^hvPءlDntYryW+Ŵ6x'&ғw-Sq4¯Th00"7 +R.'|aO&>0HS#ma7CG|3=7fx[:I_ƛ[SK'fAр/ńm8,po R-.\ [&g(ǂ\/{,` vbLT53E7\`NE^'[ϮVvӌ˱:'SQ1;Y!%f&]r}0z[5{rKG-Eؽ%݅!t2!mjPwE5;=~&HRߣ[9t1]8tslF0KꋾѤ[Pl݁P[ \Z\!֫MbtݜGh.3 ݤe t e^VAW7G<{;!5JD-mވdta~g4Mhw Vkٍ<%C  HtHH3@6! peP2箖墦!Hy]'N!zAdUE{ daOAy~W2+yzx5޿S?t7 #mE%Wir=#^+#>^Uu{ޓ&o>Y~<|Hr7%#SRI5(Eΰ_hwPI/6:%[?!.`D\bBnHjc(x8]+6J eAF4b+i8&VxqS:}ۍ<ɾI-w;@&@[Y%sd4(aBTiC0IvRNt>Xp^4$림r25BhBT +xG(=?j<@-h5-Ά1J8)5^6JnyE UD`)r.6 %'IBXEuǏoF_Y2 ;+CitSttKn:Inq;Ԯ +>M144b3fP/b$׌Zp 6NAy$Օ2>XчdmpG|j3'l5X)ی7=a/)JToKOӯGI!S~5{X!FM"U晚!(_'* RKQb%W!6Jӽȶ5T nQ + +*TArNr&f{.qM LqL&0N;580]aBe cJNZP6f[(V2T Z[⢸Fj #ldb RŅZMzjq0* UQ,%b 3!=HB2ʼn +n-ugzTnRkVA^BEp꡺a5+`_iiSDOG@r|12LEjPm,X >^{%(㐇j)~4L@}x!YDLPu&|:41L!oΉނym/4t}x2a\D@n]˽hV$s3UmIX E^a'LeW NmmioQGP}ׄR6GrgIoFUٸ +|Mvb [|(ߖLwud|іx\"qmw(Ta]g@5:^A D{l%Gly/@bjDؔ݀:lK1I%P&Er"=1@cJ:G$x|@෺z'ƛ;NP);09%*P 0[F]^k~m(WmяMQe + g*Vsfdj4!N̩nOGjmA8!#)9ʼֻJ'SaZS eod+ekٓ9CHL(B,6X uznzMA*\_OZw%A}a209Tw"G(>bʷp0D7JלX8e~T.¬0~{=#b[1m0#̇_g=dpbܦv/vӽsa>c|̝6 rKm"V7p}1]"%prږC{+uT @=-)fwPU :@b+[Y_璄 Ϳ8q5-,rXd]]a34sU9T/[y9 )KsPת +Vw5/mUZ /VHTM51R`Ji2Tud\ DxC|եߨ:msރYԵ#ݵ}\jb17U@ZGf&O +UxftpΗ~H7qN(s~;}!^p}x5 GwΡO=@7 +DEDTK)(.UR ɔd&ɤ 7a;;;*SAdmw)k{ Y<]%t@,kM@̑nc}ORUoM%I2;5kۮO22֠0}(d͇7-ӒOg`Av=u2"\7!s799x)gChUI!_V TZ8\ x545fl)w񎤲bNJa}(П\XI\t>b7XYR2~8<T5TpUUK +q}#{+yk|NB[I i B]e$5~kh2"uT'A)bƐ|Ϗ-:+<b,tDyI;Lzۏ77ֳnFt2+J)O *Sis%zagQ{p&%pV#/fCҊ/[AD][@ ]eofj̠O>+i:%4弭'DUeQ"h_-$cFۻ +sֲX;cC%gwb3$s-[r`OϐV i DBƃz+)@*sG,#:jg֗ߒ$|tIC尞yP5uTsYmg˶;K7?5'-qhuw~Iܲ^ƺHiw*}݆<f՝lV3_TUУWB- :v_ oSGgn8}=2oNw3# )jM +. 8c +q2 'vذݮhQ v^uw7ok;mG  ;#Cz/G`&0`CnqMP_@]j/;`'?ciwJ-?/L"=[DQFࡀO$FւKXܲ^kl(72"/4L~[mYeV /(Mo 4+1?("$Ca,HX"E>848o۴NzwuW%Mwz mKKwWl/*?/(B/ag}ADԁ(/W,kvkD嚔xUI5ᨳ-5i-LN?{GjkrtoS]sIMHqWRͥXeF XauOs~q.~,.'.v̼b #%vZDUEiF.mmXJM YKO-Yht3Mp;֛\fT4w;SE.!J~ٜ+ 3Tg8~*`-8Ov4 &+ODչTTBI~ɠ 1\"61zlxbAf9tű\'G7r0:b|zE~fS,:Lm~Z.OJ،%ISַZׇ 1,"n-(RD]uZ4I?f6ϓI2ktpW&ҦIZ$";k +TL "]Q69fܕjCf˴qC,4J}O\E+ ]x?<0»kǗxظ*O2ezuS&2V􈤫+hd& W粗uH/l16Nl7 ]p}|lU$巨djr;_֣s}@}x5} V:QOD4 +aO#%z +(*D[0LBof= B 0Bd6FTR<=\`i8ZjveI3yqƨfnw޼%{'J _X3N-ލ}wElg)i=3pb +&|ײP^"#}hKB8m/򻄙Ebov%"-{Dȡ@!5acNm֓;bEW=EEwQ1_牋}+{OF$m~HXҴX+NMDKzW-I +_[JL%k?zwҾ|B=3R{aHDLk½KȞTK}x*͕}Y>ރVՉ'sPF arʉe-3{yh+gԝ:9nb6$l`-6LK9 2G(k7%u}bLjQM4yWPD- +_CPny~3 +9[1הeʞԦdʤqM1jٛP6ds 3p:2_[(dQzI^M,)Ǫ`1;,Iڅf߰+ BkXnXZV0%+r34ߕ[IK265Eֶa:ҭN"ذ BgBS_5Ӫ8CT=ƕ^Y].@Ǻq0y7\U&64@r9ʥlG>·CP7W7Iֳ!|L} +a Q$<4t +&14$P,4]*@qtZYr_D #nǍc&k&p- +-;\T.Ls^Ӭ=XRcap|n;MȹsÛWR􄾜֢6{:~#x,aGp_1OE -:WhRϙ57e2guc# Ǚ*՟Yí+!{m]& ᜬ>6-/%{c#neې[9L@Cd4S6͚W ZFsϡ|/~ !g'>C'G:dTna#| *J|X8R;H4гg +2~WH0G]&&%bcQO\B6v׀QV#EҨ]4~|3.ZgEv7HT{DJ[; /2E:*?2]u4<"?ȥ:)q=DGaW◃da V5KUB*I%T]A%hXxU؝yd}gDP+.~pLRU< dPhz珪!΋+i{[U^<:jӡO x@{$h"WơD%,tt,ͻcdf`KI" .sϩWڞh{,-c(kyH^EL1 y{d79_9+Yx?|\F%-3Ϭ̟XH)["cf]k\dqcxV?6>Oqn"5f+ +Y䯇w͵[i1BHê'a"_?::_?{p9 ],P/e/Y8*݊o,B & 4_^}$!>ra9ByGOpx Ng5xX\ X InW ă-0WXsd$i4ScbX>uq9i6I"N`ASypCwhxY4F4]6mU(cggxc5:ͅoF R,.aŔQM,i8En?ҝ?!ÚGF$NE76[◘xx1),5G̋)El `#MIȑSAy9=h*2 @0Cay-?uF5הǼkEc"x0%zӽ !yr$z±ݠLlߩEkykxESbQl_/`4H 5%Sn)@$XٮC-guc砑 +zܰaZÅJ(J9WQXDhI+@E LhA|ؽ|*<|D7 ϝa4(DÞ 6ua ?rQ}NdƣT?;)IYArCOB_"O9*ԣۇުeE%V(0Fޝ^ F]*a=RÚ#,&AGlG+`GX̱5ƨV̥c7R!`)rt .5vxAL_bYY'Lb&Jq K : ٙd'{א(yq2a7Kj36)x QfE4WwSԙ.T3r<{W  F= 6}G6ݡgh||9Eu;(ݕɶ{?y/ёkup'᧎}oQocI~ki0ʪhJ[I;n$e]%tHzgtnv&6A%f82N5u754@KgdO~Csi4/9Snا]9y7~GƺѦ$$.lwS"'eQV%TOym+'cE$ʕ$ ^QQB^]-6Lj:l5}YMM. '\̔b=daBeHU +眛 %b5?Б9_m卯Iu.Q)^ƿ+zksm5fGN:JRIi:c}wΦLe}I^6,*-z>%X<=&=f&b$zarw;f@chvp u{v+Х6cF ~9lҙh5H#Rh9}.3/N΃@a.gP;)ADwAnlgr?Q#/NglxeFC-0O[5kV\Tک/X{IϚuxܩ)s.\ ##G3a{q P$[Ġ-xN)OS +!іk-h1@Ou9=R'hLЩfJb($i+ ( bW6Mrd'\r}ȀhZţr*BH߮lHZOqĭ~!*%AC {k!Lnt:򥃕=טOKl$M+E9S R +􁐿VC>uM(4Jv?{AEBHt&@Msp)( %ӜP3Xkez֗"§6s͟Fc{RH."#O7Z1upDp@K>am'fGCAe}cX:|Jx+~WLjm®H,wH@5[UHRPgMǴP 4cMnܙ~ZC> +lE8x?'} :遲;V.Ncj\DthU&ptW +T?Ѥm(G@ENux.ls 6*팵aai85Ts)S-?gOĢt78#@ox7~8D\bQ{U0E;C(~fRH)mс@b~uϫ @ߚVEGSojul6Si?*Bø;UJnv⬭6]g܋l0zWy7=O,8C= 4Na\I[-%T)m($[l(+0dj8J,:wa_5c3"*lcqq^yEc3حm b4"}I@zW* qK z]Vc¤>EB)/A{Y昖)yn__[NQStĮSsts( +Wj;й۩T7AZzd!p^;VmJË%zvM'f^cT{oȲXׇL V7!^tjT/h\'M+9T%$oip8oPW^ OpCϠQE#7V e94|uJ3DReb +^BH(~kάe՟+&IUطƕٗt=)Y ޡwD:%b!$gF<{|5bW;F!QmBd]LDdSwb [b3(gYo:@ƒÀZ4CYF>a剺v[_6%SiiGc^]ap;KF 'd܄1UOg^sN +[iMY_~$? c!EUaExc4ZW9Ab.h,0X.Y>=4<5Q:ݏeoB]5;Kq*V7 +/PW%=ƈһ"aY욑?pIWFn^|r g\9ˉQ䈫F;U1'لׇ L`|1@q[5f-a[GQe>Fd;njډ1'V>)暠{fјxpJeޗ[)ёPF -;kz1jY'TlsVzx9oܚ_e-NZh&P-vEƐ;:1%ч0wMn'mocqPY訉rPJ=tmFv%=vw4 ~y+0B{d" }|~wtAm.OuWcavcYw_P@xFy=Zz4|=+OM}"ߎ"~ v~zRl1zb{oYA{O¢K|F}>=<}4~+kt#RMIWu벼;l.-\bqX᥋uOuWFQ=4؁2+q#QubІ kKbQXwO~FL/<04+J#tk(a4XNŸ׈'E˛_<̗4s+T #7Xk2m񆝬wr`ysɄ+hu7WvFx~6y&z>jflnio(qpxrgtr8VuFPwy5x.&&zrʌjƹkߗ]m ro-݇pwwrKfsڌVHukEv5xk&CziIոLklݜ8npvqfsUUt@Exv^5ex&[yeǁhضjy|l<mZouq3earؕ{U't|Ev&5=w{&pyWGh-i-Tkm_+o +tp_dr`Tt yDu5wj`&yvsuokcqISsZDTu4v菊&x0$xcixkרy=myo݇zIqw zsf^{quSU|wE|x4g}zh$~L|2v3s0vtVwuvjx2vxwuyxeTzWyT{&zDk{{4||$}}tU|du(| u|v}6w}txu}dbyZ~QTzH~C{63|?$}rۅC/s˄^t9nu҃{vuswcx|SaygCkz3{$|q!pr͡stoBuXrvBbw/Rx؆By3fz$|qopدq̔KrstqvHaw&}RxLByo3:z%{ٽosvq r'珊s;QtUpuq6avQwэB3x3z%{8oO+plqqrsÚ|ot+`mv Qw^Ax)2y‰%7z;Qnװooq\^rT~!sANotj<_u&PvAx02yl%Jz89nh oyMprq}MrҦnNs._.u@GPvLAKwؒ@2y#2%[zaFn +o p1qN|rxms^tOv>IAwj2x莔%gz2l~i.b~k^'~mt~o`~qCp~s(`~tPvAI?x1zT#|;~|r +|sTw|t@Sg`ղTcC)ʐ + +ALV aPA9zwXS[Zz**z̃VS ]r7O;lW ~xL/'HhwGH\ŮP<7CUXy96`Ȅ7̨݆}j_, 9II[O@M .hv,-B;,Q9]U a4tNNv3Ƿ0/2&l}R|,sd6*Qe%LYp!=%*:|]|ӿA=b7 +L7+ziD-fU܀#Ogʤe =<}* `<bo4H[ Z%}$t!~WY*ѹ$׺]CsKT`[fr;]|K qm\1!7mFCzaHO8!ۢBgh tʼnPՐr`>$N3WujKB-[$9TdbZgsQ3){甎9iB {_okK]-~wzy.Nė+ڋ2nHZ\;a'fër,}9yqa/~`וֽƹ%1xaIiS>ģ՗y᪼}x2y ϗV؟mn&}1|R^Ǫ܋K:kk?Le(P"[Hs?x6@uӈ;)oogm#0 2׬nu͸ nz+2cœ]zXs^)<(l#Ng2qඉV#.|ouiVէ5Y) Vn9K;!V%NDWji?<kLX}~0U{w+z\JMBGδ;ZA.2؝|ւ;s{r`lj uAV_Q ˄Kh?mezlPg/uxQny|"_?=Ay"IJbSh`@U|QURYp[WЅ.Q^Ut4,N :-feWݏ1 _2-֕t |2CloTlD^)eG>:TXOdet=~ $t4^e}'RG3|w ׹䂜^iHG2Ʉq2ݙ"YA5BV,\{\_Rr><*;*>:θ#{^+f:PCs6d5e8,,XNӏ2EGUHBIn5m/=Л)oN+Gel$Ұ nfBP}ʚ;JRRUŇhvuEvo%{^;0aLr|0^%7ULXP M_e/BLm\D;6dY46otlFQ:ufEO771M)չ5ɂt?j1S]a]LXJDLKi3cOU! !_ +"g>xG=iu#J26|&Ue6'L_Fss*vp}04u v*CIi!Ɗ" .JA̗3^{ օbEzr\Uj{߿Jo=-u ++q>Ou&]=TsV\G;J +F0iYS0yHw +ob<ƑjJB5>;T +3D˞ 3wKHhYiE\6+>UdG0Fym^#:kyQZ`J)3AÊ@H9}F{:RאSOADvZZŵBg pg,VFY:{Kv,奨]{x}wG~ozwo߰^$JhoѠCɇHgItoV,&7D'@sBO8AL2CsʡݤwH1k M,uDK6~\K"r_+?8nB@O^3=&lƨ,_\MaG1,C)ÿA(8 \B~UVHTSb+{$=BL.1Px&1ЋɿwXsz։i;ڤ3ѱ~omȀ-U ׏RCuwqWpbu.o+PX: +2ҦpVv|[2 Y&;] +P 8EvgJhռYjrk}D 'rTs)$JЇI.t +#۵0К(w>n`A +NaX-STNHzN7 +:{t  꽭Yw J] ֦g]_W[Lh s0 A)iSc@ qn)N|bj% }ļE'$8ۂ}g M-4{VO +qt\xNa%+c +f6ҁL uDxI YTn32f8rܣ'L% Tܼ,Th +a| +;S|E\dD\)vmyxgyK's,%y-`#ڈ-Z&ԤtPUu<3T>^^Ӌo] bkҠH-$\wahu4J5`JkJ 9-YٗfVaj}aƃ $=.xy%WW Gj5Keo,J!Җ)ˤM)%k "١xO>W-'fm1`*ڮZ(-ꗉ,ŭlXw:eJUC^="]NFHWpևRܪɕV: B2lPRq(2IDw B 98r;w\5I?vB7jª=l Uit .= ƴҘWOBte.񭹈]hA#0_!sKT@cs|< ip3< hl"җ9t%0=5i6@L({|"l|=ZT--,Y}זTAn/UoL.BF̎@8/#N&%eDže|Ԛ.priK_>lUiKǍAn8=7.,& kӂt| +ħorF0M~5\R,h#׉|)wm!dTсZQ@H}>5e,$˂%vףmAXWcZ4;P͖텺GօB>b5FJ,$&#j@Ovlc/oY^PkSGWE>+W5*r,$D{uU|8kbېYYDʎPōEG=֊?5,@$X=tkSbSX>O?FA =^4Ռ~,o$b؃ԅ.tuYjauߙXDǗ6O.̔FY֒&=j4,X4D$iK}sTj(aWfNݔoF=74ʎ,Fz$n8p)igCk]mT֤okK٠qnCs:;u1zWw)"y!"{*~ pof˫nq][rTsKuzBw:%x1Kz^)N| !t}>;oIufM(v]-,wT%hxuKLy{Bz: {1V|)v~!0wpMnԭ%{de +{\|{S\|J}|B~~9~1sU)!*҇Dn<,2e-D\4&NSQsKJ\B@y9ΕB1) +"3n&/mLdCL[^RퟰfJRB59H1)̍["eJqP +m d5([]IRWJ TxAЗ91c)ą3"#pl2cZR>e=IšA 9koG1wه)<"}2nl"P`cDOZpQܝő*Iq#[AX~9@ꋾ1`W)닿&"Lj'sĄk{bΤÙ^Z-Q:I*A Y9x1K鋭)Ul"هŇG;jrk1pbbKYȠyQ?ɘIH6@󕦒81:0)"uX"fj]=l1TmLYLoDOq<|}4'~-W&9 2Ѐ^dϴ \4SΫ3K̀CܢHL-Ӂ&h w`9d})[鮾PSVKr|C{5m{WX]eGOsCX:}6R|t+jOPHFh}A&|1>SK3m3<]@Μ,_@z.=B1OF?{ۅ@o8gݱ]@Z'j@tڥvAvˍ' +OG7\_ږ}Ny Yx**n=n$^p?NiyҎ?hZCRr-N%MoE0צ,棞nuST_h<#޻!bq^71tq)+l55TXF/?5r0jӏw~5`>2uc)p*K֚fS*W}R#(8s*I SQ ;^KE<|qg79b/a;rcc>ymv +;ks=R\T W=$DE!A$K?弓|K ҥ6At&& ~@" ]ꕆKΏ2VDQ2DqyG+=}r;v;M'4w_un#o/c/pCpfΖQ=kCA3 Lپɘ^M)n{.*#1wبkKʝ28g¸׿J 8ߍ͏F1*Ҫ깵N ebam.P:ZD}`J.#9 AvvC@5ޓǴӼÅBfiMb]/FԏiKQPk#8P7,#.F +×Z{^5JgLHy(n_Mê28Ɋ D#ӆubQ[GD ԠUh4hsTP0RLޤ.>㿰#&Sd fPv>%WfϳhH10I#+&tn{.]+<`29oS7,TQ[Ī֔ZHv +L[(1;*NvA并KMUuk󫿌;.Iw_ݧ Ww?/>&:x҄+I˕e*nN5դNvEiU^\;= g v}*A.n=Exd}"_Q2V8 UnHٵf1)2 %#itM(18IXOd6b*XItS+:JCs~NNq?тT#pLXW?;4NLM A,3xIpOKP.`?n9 xb[6jUrt {eA&ƔdA0<;>X+n3H WD | )Xw~&0:6Ha*!2#bA&H)m.>kXoFMi]aL,~<3̜&e[<qK氀iiѸtQu(q|+t<녥eUH`gr<5 6}gm}*?Ш++8C.LGIدhQ(\цʼ> y1H, +Vݼ?ʄL7 -ղ(U]>PoKi^<(mGq]5:+[g=lצ@Q͞pt_ ʈ 98=a|6Eڐ{=hWhHޒ=]ՔnxTD~(eZ8T?! |oߜŚy&nPZ8SZU2UpP>G$Z=sAf՝Uqv&'jl¥ +3H_$U ]\7;@φ9QՇ~麝ډ=)]\UwS&[K VwkG !.a)BEaA^C.%./ Zs3 +kb3OL +"ԥE<c]DxL;7o Cszq|w/g;6kU$_˵xo!ۉWnx! YY8iaq̰M53%qʂ|NX9>]kO$ds n=  +Z 6dHb@ 论!(Y +lo|,&8neq'[Z:Gû$Ҭ!PhJ;j+6*j"[{@Z#Z0S9Nz?+Ue]E#CҾe=L Qo8y*ˣhGQ8oIQ+ͺd*RMJ4d)-e[U2e+ bUֲ&j1zhB6m &.VWH= @D( T@@@F;$!|L2;@wEݥXEUA-Zz]oxr".l>[nIM[= +Ic#.=+) ԄE>!禔0U8)!R0&lIP^xM*rȸ'#pS)rllB6SWX4 \5'kW9[JoG)y %;LI+&k&V) +xƛؐ@FUmA/Е ˧a'#edS,ڑУk@ks=%O>lLYT% 2#T>[ouʎR=-B'w65\c2>c:lm. ZcʉrA rR/5>O}ǂ72u1Sӥ[Sf[rH/nS*$]dƫ\v +hnMm G]݀w*psJN&O߰oє>QT,P:DWKrԅV7,NS= 0+[XZS=cލWEԴPs[9++f$w=\ٔɡIp1-HEl^)㲾[Fc)#gTcfA2N+V  Tq,GD"1{Q2f/9R0Z0X^P?g|%Ouy|sD&1 ҽRWv`-tATZ2"}+:]q'@Hzu۽#_DX[CNqރ";ޱ;[T7ekHy[>K^H{C9(W?'цc*uT5gl%Β0 hUK._d$j $-4k+}htŝӜ.lfˎ}H7>!Ma;+;VWr'IӨ_?^?8l.+#9"C!c"C$ +%cqvFCSy2ZnL%q`W88Ndbo/uItl,4ޚSzb(v@]巽JFܯU uF˚#ĵ&L[vBϕy6Ur ⪬.?6FPI~o)x.$uyK8,$O]ϫ3jZkzKcuV{vii]sl]gaSŘ+lrqeK %p^tD W/kNoԕ anh՞IhjWrL|+LD?o:wQ>/ʦ{\cHYyA6 [ +UfZeҩ=j+7'2m=ʃWY]+ gY1tGt<@!gM"$MH +1L SaPXW"1)\)|+`E,F0h$EOk!!놚<ZcCgBp/^; .^ډK QWIO姬 KlG+ءC$ DRi>7v7oX7-x[eW%iÓrZ߇S7o䏽.r Ct?Q/_l*/- +Z^f*6OgQ +GeH"|ۉi\#$#XBȭxxOuu{mEeU*G>h:h>Vg'6+^hóG +1pXɢ<σe´pSv1\oMƵ>Sg QYADT@fߕ =Y)JV|U~~x&V5)Niwimbjh#b/#-d_o'HEB (~i|@_ho$*7ATN!@UP?x D9 +5Lͥi=^%;24qw 7$dJ0I`j\#0 _'uwu\(5o>1jJt8wj21L) A"HQ!Nl~GASMN!P֣+H;ޢ%R֑dL-Y/F7w-^9e1{Pj49$. V$$(X=d,D"#WdB Pښ3'KBUʞ h=Hi44GbZpIˬIYcMH^i]swƆZ3 [O֘[ 'QJEEL F᪠\| cN.<0r|dbұJɧ*KvM RezI.t!Jln:u<~Ti>iY0w>7>S5)_,^}_yȌ"KVbNAJ_3tU̧>~z[sfxb{wqY^Ú YFsGd!uaeh'< Tj&˶MyyH0{u +hQ/p=nD3fڛgz485ڭ`,n&l91ˈn ~ FA@ L#ꣶ?aiYG NĶ7n k |vZMH] ̗ +p387G *(O\+ۖى"2.&Jވ]],tES 2/n-x,f,?@/|&:Y+zJ^-^?gcM1UOGpUb (;. i@F7Mtz(8c/xxI{G)b-*wEreL֞5/Lw|/YiIv)#!KwkᢈD"TaP\8,|џK5tWRK;+ J/?Ѳ]V@1&j$)(#|/ <Y®0m)u+G}dUq]&uuVQ'!- +("G_|INVAeUQqբ(X@\-z,-/̓ Im.!u*FU0k^v--,ٖk%4k˸Ymz| jCO0K LDPh5&-,Oc|/Lu:9dցD~` ^ b(ʳD0¸d&va9b9 ̾}_dp3 6XCa뙈FEJlrDhJS7[wJ\63B63!&itBP'.Tg`wVvOcsP?IA<ق2 U.(-&:/doNeNkR.^dr%Xrܕi;qr_pRF ES-I ;MC?f]aa~};C֭O3Da:R(Jugq{YϔPXihp6as>5n&ا YB>ڱ5Ϳ&ΖغZ_^묋)|jeӥ jp$+Z*qQUJ Q씝XPݚ{$n0\Jg'qڋSۃCdC𔺥mfʍU?./ϺԴH8'[i5(r$ُ=z>^" /i,'R΄{~SkeNyx&M_FI:}u')aN 73DOM p6T1ѰF=UJc:ц5콬{Kݏ@v +lDV܊QŘNvo SY@cE A.yKqMX ލ}rܑtanQlg4M)$13:/yXmK1 &œ\IҤ:gcքp.J:T<&%I&er (J:pqŻwJObl2}gn_ɹ +q?ky2ra;`U Ff ')kش-V 0Xd}:QwE4j'C>g,zTs :tLx|-dmf@/&_o©|Wc]bp^K?jJC5I0c.[+hkqGҕcAi 7y{&c)أ{5ћ@)~6s,-8 榃dpůCE*iQ롔QT*'9N{9=Nn f>0WM6j]‡;Dʲ]FtGS7l@eʹF[;eJ$^i8Y*=* +z/o +Հ.fÔW?Xlcgl| Tr}r* kAr:;9^Rm7`xM";Mғ'*wɱ%^jײߕyTsM&MiNf{pZ0bw'4U54 +lI5buT AiUs/8O>O.PNo jX[`ޥʁm.m@=XHt+]"fTNYeI!S:,$9CJ1Aj;+{+i:[4`)V +j2U`OR"v +v)S0>D3$[C fˊ1 샭s~!)FagqL܊ç5A$3z8NXE"4vha. D=B\h_}<kizVb# 4pZ +_Baqx%_DsqףOس"zx [;VQT]5D- +AN?g:5g4D_GdABƒGϞR׎45B"R;P-W 2`4dVAWFH>{bNf+Оn/]n8nj;ՒرreP>ieMwH7ݔA^ع}Q&=;4oL_6vF褭&()?,JEfb_M#Uvi۔GCbZV[`>V^*v40ɨ0l71P0V5Lݡּ[y<݋P%>͗`,]=?l{UC UjS1]ySq+2d0<1ʁNmΣ;mRDZkjT>#@ )qQDHWL2 n^IVف b5T(]"z8-."͸,ûIt|J%(ׄTyFҝ2d>XH=?E1~zh5ᓊ.sS9ĵFi܎~,42d́qz 9b*"e-'hEX>>3e_vSڱ.$>_m8/RH`8ʮGH Ur?4^vYߤ`XJ1y8k|)0NrQ, HZЏ(جd}iO_}! ?a5 ;5$1I&nesjn'1n#ԽD93aP:s"`*V3Wjȫ . C妡h|26aW,'qF`M:~ +/xq.~ͻ#XqmY|\lp&)P,} ~Cv$eIgPeYch];RYPTzc}c.{a̸|}[z_)U]j"{xrG,m2׬|ӏ AM>V(нe"Uh 뗴;u;:mhƔfnqT>|QTf8ÿlG<Rs̯5x(`\vY^[`]RSVb): ?3 #:,ΉvT=#]-@7wz }[Ej< /4hr; GdE']-Mk$W`lJp@{a x1\ub ^V(7i?ubcUd9t&0a7aWT 'zIhkl4a<$ ŘG]&}M~F'F0סqP, +yBy47 Dl~Wg.cř!J#Kb BVƭMl_ԣhba]Yc7/2M{ H< "51wѥaQX5Igq?34;ƪE=Lm:N?"\g4ż%"xM *u`玿rnP/gl2"uyiRC{Ao5_8"(wn+W,?ʻ^W}ڔ.CxM[[|d彁,ɦsUՖtU_.xҹ9YT6A-,4]\3Ͷ4 *%jԧj=*x}f\NHL]_՗lv4n]t7u[fypyNQ%0jIbM >3dEtj6h;_מصU6\i>iL@bd0m_ ԉ_Sy * !*IDp+\\{oH<Npj+xUp" uc[uտ%C R: )Z0v.7m+`D1K$5<LQ[B |W 9ҝ'ikQzGv]L2{fZ6S5# +Aʰ|P +;q`BS0dKG,_SMd5y@+t[cMJ XCag2`Ԁ7EV!l.DGR c"1!G+@'u3X^ O!:,u&W;ymM_}%3M^d G~ W]?@4P<- 5&Gb0Rt}'4:?:UGVjD SveK7 +9!zERdNoSckzrd'BRU'z!*"ӈS$B˧M;bokEӼy|}I{fk("|O"Y ϫ[JK5?O> Qv=7dhi/|ph̕b=qm(k ~5)8Sk[Z57_W= 5bNʖC1MeX"Gո +U4% ͘$du-AqX^_~=ҫ]+SF;,|jVL@Ebq[Jod-Bgl{=%ɱcmDq1}4Bvʔ>J41IW%|Ee_/Vޕu~)ȹ 5<"-s3ߖ>Z2zɎPu1Ҥ;yt(#,"!~Pœp#@kg^0ʈ`7P.'\xi69% źLt;OP0鹪R.w"7p9T=FmM~ikSg-~A+ +ѽCwP|%4=B"Ce6̇>B'p-sџ3шSV{%l"uV+J׏zI%Mx:\6玬rN{Lf˛8aQRC[o^ꥧY"Ѩ-/rDM~0KH팕ϲ=xײi٣XI{HWZn* +a8SkJ!6 +x>.1ц2I|m&!{m4% 6 "RmH&b9Pljkt ֬Qfrܢ4f8?$B,hnx4p<:(yWD[ƨo:9ȾEͦ!WDԉMz69f%!D>g"%ĥ܏ke&i5aHq{ba] zT*6Edn{C\Tk=*@$v1Pn(tl]'|s7*Ζ. }2 +Js*oSC8_Ikϲs_|ØXiyRVt[,JYE̔Wf+0(z35c:W+gQЂM-iʉ*B6Hyy[@!`"T\ +*sUihjVRJSWw3nʨX_33!/RAxB?~q=QJOM`H;ffXT.nYLDVt`FUe[ >YtU}5X86"ژ8vu~|1D2R;%_|"Sh:f m;'Æ JJn wbܼ: 0x2 ]2|N{U {OT qb+FEcH\krމW,$.AP>/瞒HIS 4f4۱WX~>f}( ⿑8/'rzKrC%5[ Zeؿj޲nrKY`*֞}e &U$+@d]g)?(iNG`,Ct*GL~k?oyyzZЬoD|FY_gG8@f"8L{Aƨ*[Ԝ7Uj/0HYb$4삉L6~5HOKL@< `h"I1TdW@m0 `Eޢ\v$TC4?w 3RH<AlS1K-(Lub&uM=:"Tn6ULwv @E6LPԧ$|`>0=]?a!o$ v _N寛)%rz*pQrKG(7AbuiP3 bEG85 uTX ꮘpPxT)R<ڥBalAQ?`ְf.ы>Hqۤ5#Xycny: 5*f"*tP +aKؐ s_areE^EӑNt;F"ϐ/'{{d2J*weTsih{}|H\_=K0;yæočdq[o&_vΩl]/5e*y9Uimkt{G}Mć7hø]]SܼNnx&S6՗fk\|^ijC/lS' ߙF@5HYEѬV 7-BB.{$Aeafd垬Su~,;}\6vaMN {짲kp; U}(\Oq*6A(H- U?eZ!ݤה3둗]X(BU̟q!r! N)dRYITۍyYO!Ecˤyk4~@ne1EZ3'b;) 8F5F-`2oZɽx!Hf^&ƨdت<*HA >1C0A`㌷t[1z& 7.}=Eibΐ٠%]3`:W) \a7Tv,}VBHbSIFb|p4$3 TC֟PBigU#䈰] NC7ja[|r kFJH͑<-/1zBIWVMDm)^ͨ~0"v]AkWF7l1ĸeXI7]҄oNGmp?ޮG7qqԿ`ҷXz4\[*x.aP:] )Quon,T2M^j 5 -Y뚇 IEDD&؎D!&T1-U4)6\*K0MeQO!0}&2Ć\= nX+ v[(rлOGeK^mZ8ʑG4Aj>Sw<5|$1*)-LR#jKwZUּ,.PeLs4r$3 Dc({%BzJccfڬcv!si mV1s fgOfQ ;%)i z,O N#pJ;rSN\Rhbn?|~k@0VŭΕ!R0FdeȔBBwo2ZyQTZUԁu.,ru?~wQT_eg2 .1$^ZHuǴxZH2\6?UJz +3t3dzT5mد7olҏL.68խo,*a$<;U-kf³̳L=Q:_2My!d0NS9 f%Ena?Ժ,| +hpMjʈ HyC@t 1Nր+L#l^s)]|+rt%aP.K?R-pp *]ZXO@5иmC'DQ4+sʽcu?нU8m"Eƍzbe ⊫ذG6Iu3ЇUb Ԯ|E]@SX@Rj!GV'ܖC`P2*_3". Aj03j <^ +o|6XazGrx6oD+Eɥ=h[BkI6쁦 PYt?ҡns󪅰;}I9OԥT򉋁=r/&A儿 @(즄Ę>=m`;Y|b[rw[̓/G#Y 0'+|@`?81lo)ʺk`Jͫ-`#-Lts-DPnfՌ Rh,R{`tgNQ7po]\oNkc?k%/9b!8Ǻǟ=r\A8on:Vٚ}!l_)Kl DYΕ7ck!fL!m|kTr$Wf4 *btfyZ%Zw6sʴ|悒6JMsro`||D]p*3gF'v%S^4nN@8-I^ӈ }(W9X2`[~Tto=elKVIȬoU_S.ڟI~Uϗ7s3r=m3y?|1~sO̤lL7N|6ȃ QL3WIY iё>mZp5@ Ya$7HGW^4x5<*G҆8%}5'd]X(Hfa(3"^ߢ~{ @O3JB"d9'@!ŏ#"y{ɘ?*V\3F`^bda Fw, %&F>_3% A(jiq!0DA#Xbfw9|aĽb 9KR!ԼET\a!!7A'G^=o7dv`u'5c.pBȨ-PCJ-,F> Ny\9CC.o?2Рό"{k%L@x +*U#U̿+̡>Uy/# +ޜ%h(+"+) +sL)k zG) <`Y$NմS]L$N"(/3Ql*Cc:MOmm-@Su_%MUϸ8lu)\3l5I*:VPXnknߛ}T` *@xfɝ:> U?vqŧ;ʰ$]kk]kmU5 ^hȧw=T8 Թ|3V+hinP$YkŖ9ƿOU7 ( +EuK "1 2aa_ͱWAH;a} ,2wcBxV9 Lj =`| +O<fasGjmJ"[^Ƭ?ApuBWV ¨ԌeF^-Gr'q cƘ{>Ljآ-mUzU~ҭձ[Jz}6[7}E'&:ۃd9p xLV0p̵X?Q2UE[+o*~(ʜil77Vo񼆴Vw?T{0ʗtf̷^ 3Ҳ(@SQ&z[ a.ufG2|stLJe;VOXJdn9[iySɦe{֗W(YW-K+O26>Шz`oNh&c ;jaSzO$͈ZIUQ;,@cSI[#nU_+&!?J ]M{&~~ W27ױBE9c@Q?+F4ޛNl$+P|JjxW?"J=bQ"/"k!SnՅH'hoYo7,W{N GV*H7rs4i=_AWj iKԙJ),MiE=C*XS*{Ee t:`d 0O뚁:G + @#AR8 R=܄ +s=b F4j/".ܻvA;H @RNYnh$54ņsӺgj7fv Eߦގqߟkˠ׻ DiuY5a(g92Q^y|V`R#XjJxzV3UBo*6&Ķ/eonnoYэT$./Fgv9l=G6ިQ7Ȫ۔)uj#Nb`Poyd"X̟*>r8P.u6 rwWA~k@\YH-d(2j"BB>/;!JEjkQi[z.T] OXBڐ!vk%^?˟oLc'7-2۴ՙ8Zcya^&Kl >z*d]wlǙlD/e=yXVjP^xacRx{jPD'C&3ZVZHzLH53iwړX1mWmUO577xFKM܇ȴ,Ց?|]ONkXAfHOZhMR'Hcir.NI:?['w&wvKOWu;)wמWOcZJWE i3;qŧ핑30j>uCgI\f>^ +ЎOYVq+, rySpL$#'|*;O*F{uF?H99yN8O/pRšRD|ʫT/s+}(uc@<1u_`F38I"#3^(D*+ܫhXj\ @/ȏJȿwRA]CR#8"N/D/J„e\@P[)UqPNPYu#v'u崳 +9SxSKPQ9UXU0əR a!Y{inqVw릜5;-M1u@θnxO}=>ˋ0]XsL<۠#kF(eueAպn~IS% +3NK `H(BXӃ} f*R@QZJbsUԅ#o# D,&dHϘD3þ +yk-:X|u7\@p䶹N F)q.HJ6F|J˽ ҪjqUUJw=E܅[Lכ6c Fl%F@M,X#]7u,Q]kg%6{8oyZRh J@m]E檖xJWGbj$Z`9wI;u bޭfA2_5Ep$>^1ϬI+ 1π2-K>N~#+;㾭uueV7QJӠR.~<`(aHru0 ^HYɟ#/Pp"V=#/duKU\gQ~X%|(,+fYړu>~NVjfʸ\[ J-P\~Shem^K^ s%vL}W-:SNED)0p,M,LYQ K^{ʬg\XEYZ=Vj܋U_}%Lk܂vKP Ajj)!jӜOu'ѳL:6hQ(*7{6v +ԲW <ff6Ǚ_HcEҋ9dk} 85k *la)sW/]VㆣYšbU5׬;|Cma0Gi +~Эh aZn?" yMP$2lž%fRe0qBm.MWkĆݦ5)yyneKeh |1DA_7>J{Y½iP7)'V? 3UH$󑊇ʕqp@t4ԇ3ݾIiPzWiN4S+o +(U\=purٿJPWy ,Ea\:Aѷt݋ j@7gQy^NKfEk/<;C:fD^0>R &9Dz!L&NG4:ѽh)QP@ͭP+%7ЁUZA.-!}μyXvnJ76-I6\HQKV?+A goE;~ )AeG|d~U(1||D_,@6=a-Cl 7T fkG(%xVøoQn Ǭ\Re݆zwme:kڤ=[`3Fnܜf-k^ +:+7͓q~7y˻,¼6Bm2,*Jo!nٝgZ'yEK{(wzen#FFT^b)ړk$ƱT"KHϸ]t^̸ҩ&f"mdar NӋrc)Ndla\6- Ofƭ>cF4~:* 9R& _!$ָycfa󰼂8|Jz+ѲfqR6w8G] Bi$ҿ >wsHe+;+]=Ίi1hTY-lrl|6FƗ,iFE>roy:QaaͶя=e"o- D-Ԑ/❴_TQ DZxK +h1K g7 ?lN&E-CJN$I%O|tQR^76ѧ0.Sy΄0Vxi𪵃SeW҂Ю8jALmzRS +.*G|\ x'I'ȪP}&-Y>Ht"5"7<%5JQ>RBR20v"7cS0W6l mxvPQGKzchND2Vľ`o$NU:ÏڧtEя zٳ s7GP΢X/?89RK."q5r's R|L6pX߃e[Q qP?`BU~vT{8,S/ k[iQjw|aUѰZ."8*{Jw6 +R8fXFnK]:|7MlELu乱[DW1-rd= oެXjo4AG5^ϷO>[ts:]c +㗢m/%nH*~є:O߱?QvԭVt1gis3$YV M^!ɽ gU|hzR8j:iԝXaɼ2C:s'Aæ !j4՝Uqb'n4:UL βMfN&_37ZCa?T jg}%T2+֫wqL ][/%30e}ML/e +M +iQ/V\V+ #uU}9 ,'C "Qyc=S^kI?+cѱ aөƸ *RZ +d):d/Q~_C7e\Nz1SP}rETp,h0DcX_ļ88V@ەhcBփB:GCK L+$\e,#%  H 0+H&obW;Ƚx|h0Y  $Flқk$&M]|ZCz$$\$~S>8/t $0g qEh3v9Q*!rgL\0d%A?4G/ǘ;!(SH0Bo!bp\{wN./5a5UuofK` cR p1ݷ 71aݴݏQ9EXJXNFx=4# MA;[F`vow2s}p`Xkmӳ-'dmo=uMBD5=)3ٞhު)XmWy'?V]Zvا u=̘-U^qfB?"%6r}nّ~δՠMr0~0@K L%>BW.~Nu Oo8dYw@sGȔL/s~C^_JGT X)z@@ %NS%7$^}wL%IL21T ) Lt&ZAGj=V\gf2,Ө|0E%EJ 2uyq 7&vװp8 tZ׿ CKV !h} =@dvv!*zUKAAm X8Z)N8Qwh`P\Gb44TnEY7i:T(;uWmqƭ7AdTq&IzUr$h|!or,mz3=h멺qv"gNt. +Rݼ.Sy^eLbVNm=ZTdiZ^a76 +x^)^hƥ{|F{ FUk4>,h@DBwB~Q/mGcrOpGuq^L90m5YJ9hIFb\D'l_$0tWdnx FO>FƔRC\;NI|W|"0UJ"Q wdTbPjˊ1|'r +򆟨7LA4QТ-ek7w´_lLPEڠSC1U}NA ͚49h3Cd>ЩTDS1|ּ$0PCA< +BP=xFjU9<8 7 >ʏfLbzH)-O{ pijXڳ 8LpROMXWyb2:4ÿTC`-W@NOT{ +v7&2F1դ`BމY .&=Gt,PG - +|. .ܫCL=k4҄$mŏq1Ec#oڧ a%- {ֈ&W&hWoV._QL?k*H깺-2L }2%ln͈i[A¤S݂FwWn@#ګ陻VTO2wMX&HS{b/.ifL +t5dqQG6֫`yБ;Q`/%Nj$1.ȫׂaf895:Ktg8rܣ~6dtQ}ii4["YIV 6Iֿ Pb5 QMSEHEΒo sҖȇfLvٸQ սQG画!Κ +\ѲӏuKPݤmeI4= b(rdQ0d~ qyOPÒ\5 qԵm7/}-7Th:|X}.O_j\mg@?Rx࠳wiSfZudm,AL?s_ `XnR܀+iPC(wm&mʡ>ĕmBcGOK(<=9!J%>솜6n )RQ8{}]aS&P;y [fs[* +᮪%Œܚ-l3^dSkvfi|W|78qmw";%eg0OJʇkmOEUd%-1En T9|+NeN +*:ݭDaRsK!"՘w 1djuDvI_~3|S^kRZK8oF[f*ƃ"i2f=1NJ# Q+,$fNZµSk-]ewtts:fl8Hc0_l}{Pe$ t~O*lE}d=ML>VG̨:W52ĖqRØJ4Dϣ_!d%q!9vR%-P2w|$D%`,fȐk fʯp1z6_o^`n|z(Ւ/M? s)Ŵ 2D]J3*B]T^ڇ8\\ht%rQEbߐ\t(f'✷34JŔ9.`p^g{y4u-3LjF倐kfUvW+MW +eWL/xNꖻ! + \# XAl>/LjXj\,:@f-ճj_;q6XE%“Yܘ1=ʥTS aM!q#zJ/@=Lb6M[T1 QOTر(c 9qb1m`QDYMl݆P(}KĭhOa/+KK*sk>[Ob5 )6JEE&f8V/tuvAN ɒ~݀<&CpKKtRKI24<B)YK1x# ]rSuVP.ee>W[ҜymHBZ^c7 -aVNQ]WvA":m +v6 ai C!ԋg׬TB1AG.зrBW$&]غ3UMp92lMaVIsuTƔ([8-þRd 3Kmo'a2-\/}|6?m۱,DZ_خe9OO޼쾣p;N`DǕ.͏;&u1\oM&FDU@8$'Aw@PFHH_/Hqq*WG롏ł8N +Q} DۦtcRb"Zͤ-+?b=[#V[cd 4r%>v 7_?=`.^*g{d+Sզ> ?VPg"c4oJ*kHc(b鶎`+{m"fUq-µ+NK`HpeS^dɘ&q^R]p ٱh>\ U鿧O]]y:qNRQᆎ y6ɟZgҾ5=4iD!:+Ѻ/ +[vZb⼄ XI燖՟HYXI\$_;j o'Pz´\K}X{i]~Xc-|Rj䔂݉RY8S+AHGѿ@IJLˮ+PNi]$`ld/B/Xldv~㨞te&T듬7 +3)pmF ih.p0,?rMވ牵^D諻 ;5۲)5 JNF2('FMϢi7H"Afs;Ծs6(̴"idج(TWְy#M Jc^eg!B V ?ls“ٹWh4;Gg;@:2k˔E\I8{R^8^F@Cd(h.%``61~4"^au:u6PWuWsV +Z r]FBM'& B1z>2!hD_cpNq +PG%R|^08V*4;}XbLhOtGD:m3 1CbȔȦqfmU|:MM,uinkAPyX^]Z&2V>BZZ,Nj\@園A) |F嫇I<=Nx7]")Xޓմ2dS]:?&Q{CMFkȨ+B?$(qyu۾t/q V,b H5R&sdSJk>Z*irm +gsS{7]hM7e!͗Pxey+8WqRg)JZsZ6]WMZ9;hVXcZmQ5[F.s*Ū@~sdIy@꺥T*~ O~6t>Y0C7{a 40F"TxLAnQ?#C&67]>I:yI"/e=naix&~ZS~eB,ӰRnўe +iW0wBZ (+zLҴ}*|)1&=ŋh(m Coӆhd0`0=16]B;6nlU3^Xk.19<\bFxTB~`K@}5y'Vz=!0BƋʒ= 3!ȖH og0-Z,Rp#UU)*'N՞ ZW-G<Ǻ[=Z+][~=S`5S);z6 C䃈@M蔷;r +B ]Jm% بDD5b!P>K sxJנg ]%K3$]iuѧҽ'>*fDsT1 YdB +6?'Q7j!,Z-c0k +'kOX[T!f<75?Nd{6zmC_cSus=kei4OmMk!T<2|"Ӧ"s*4{S/kvD1f-.߁GkG盉䗹c/IO6x(9 +:B++쉻~3xy?P󠑪ͭ0'M' hh'}<@tiTox8h쯯oRՙBˡXz +^i b .y:+W6̮·3yhD6/a{CoxwBJ +W.yUIYݫ,Qzp(v烜ޘY_.N޾!a^CxdmA$d',1Usg{cϜ_qb.gm ZKÖeo"._T v6(פΒJ'0c9nȘPx7@c'meZc%7WMEr3WxMe>hF<ԧ0ωnehG.Û-TJά05ᯙ(MGKPyP$uM>q8D$.{(v*rt YOC;ǣᇨ AT_JeA )7D軀DE(y:GI1?qk{ +:^KjAd.##ohQHLxs1>y$cm$%cT上n\pyWt=jZ7Ɨ#뒋[ū ,8Yռg0$ɣtê ˛U^>iuت.rbgоfދ{Դx"}czٯ!3*OםP-j6%+Tݑd8Kg><{Dh+ I#}Qc%aC 3F wMHb'rXq88@Ŋiq⮷w8B*7,8~ 6Gd7kރ1b"S9ExW hǢJ2#ӥLC,¹T\OLXb@0br Ѫլ +iu)Y_Ev֑Z)pgEgYk$~JƊk;ڣ@"!=|]ڂϙ(a8DA-3 x! +OZ3t'X~0p@"J1"E[L;C} X QCTk{ j/kwh0 L  6[6֘,ykp <c>f{'*$g!}ߙCHf;@*~]F:*ZuR8>A`>DnAƑ$A5)Qu#L9l8l9E ;Y3G$ܕ _lq__q6s'd}_[Z,bT⶜4{-ǐ}AI(}Y͚֙m +E?Lߜ+^I[CE  ѡ~ˬ/n{6\fhZ*ͺ0wFqe8<`vUhOq*(.59UZ!襶v5)"'H*%J:cuBcc}!yt% 8KVPBH\8GB<騳X7 5 x C!ϐ("",6PCCW cC|&cX\8 xn]0:7,y,YBc(&!%){̤1oڪX=6աcaeHk*f@Jdt BDmQ\0ԔSWmK(5U1ْ\)DQVN#׋?/wփAL(Q-UHo2@I)SwkA-,޽*R􏺄B:$?Q]%eŚ9$o> :rkM_)b؞Mj_k(ҐR(]ԩxBQ q0 kѹ3EDu!ʹ$fS\-T%iGԢΜY܆YW5@^QM 3YT^jJPdygd-ﯩ7 +37>*N792ѓ/ø IN<,™!5@)ܠڤÖ7䥪`4\)ҬVMM\Q{d~L5bx +&kUC)"듲85_:֜CM$n4e \ +l#0t:|ByFqY4Оn<ظ]1F ű}1Ac+bHq N-?Œ'[="u,5[+LU=ζbO5!o׆_|32BDNn b\JXj4[ "RbUi5R"z +%&PkpZ<7/pLaRv%V/:b)&%;¹WzP*{Tbf%h<7by +$Hx(ԍT)7%k[*qیL]>>b-i);i' lm-OL=W!fcO ri8z}働dFTF3wd +r_Ģ +)))U$7kZ6!  dwNH}+MUjx'5I},# y'd8hٷ_x.O:eS.|8Okm@.A.k~(rĽ/qb=[lUx셤ܱJzTAyIeUIW,;\ b:ZtܖN;)\k1WVi:՝7Gw]HZa錄+i:M?znW=jNr1^a2] ms ^G4(4nm]8 *u'§}_#QʫݪIa%wG؜1G%}ʜ=wB|NR.l( _߮fBzO%9=.4вd@}~NX7/O ZCrB]MPnX8Ҋ?usp^ٯFc68jHi;ZI]#X7<UX ;ZCqHa{wf6xSkq[O?T4+:U4o+Aɚz~o&hñpJ=GpT:ק4Lֵ*VeT}䥪0gܽQg PR7}e6-c18I ;)PT{uּG;#xoZ/ 0NmbWf|Pq2CV2@|dyl]r;%L6Sm`}o53T(mc38ay6N^vj$֙m,\'˻^JuuRKXe|~5x:j3تݗ:MF^"]-?Q<&VrZPP 42WN7l +m1rMȞɬ;I_guҭKjdEAVTujjryF :+7Ab1hO|(SY{}4)])ݨ[Xk@z^:W)HjjIhį`wT\,ƆʋO{x_*<h0Ufפ @!֝쒳+auep 7C'a hO'W}H[E +UZUݲ“ ;P_9z& 6RoMfaa~]+J5y|\;nR$ {,/0 !z}M:I1~j9w㪂eЖ +:&` <yMXԃy!O`}JgS\Z;S9; _$^7pxWcA=]xsj]U*-+pBk̉~e 1tk[-?^\3+t[j1A9w‰괇ڣdNb> +3y`C8y7}"K,/Bhz;]^MIVdkӚ4P% zR͋0-}F_Yk}絃x` ~|i/|#e9-KžpUmo/E q^)tkvvRI2OVP1Y1J殺Q}Ѵ@=^ +XbT! ½onNR + s߳3;'l&e4TKxPLUZp _ׄq*geNLy}qs0Һ+Lo5hٸިvC>6i)PjN:GN4yC)Dn!EHEܗu][BH5SQAkaFvh>la 3Yڦ"ciǰYJ."fibEφiQMn"dib0b".)V XȋD/S|"SaÂj='҄O@V8Er0!f+.-m6h#Ƶ (A0e##B懿hn +oܠǙiQ`aamt.MegH GG_?-1'6sD53J52`9e` >2o'TrtU'ήhU]ijkɸxშnϻA8ď)2ye @ڵ#pG+;t~5DmWhӈH^naMa j+0qn+8&oktNKÈhԩEqnxҌ ~;^gCD2Te~ti`iByT[>H (!8HCOυ"[IaO3Ofnv[|Nc"mƝH~ |>>:B!}w4 =i?ɔ6;?t 4*-t$\x&_ "1]QtoD{2 Z3 ٖ!?9ж: $Ps"Dj ᗂ۰1g%3q$l4V}Ȭel*k)mDb{ ~|XtBs[ hN@Zø_.FxvH=r͙#{EDaq<(t.i`PX:tnӮ!xF g.z vaCkPg.c@5jPuT/"p[B +J*/3rVxuxtc?Țzh9UJd؄،7 @%f cB=h7YrCY6)̈ȭ)7~}ljk%Z,&8eG)FR +Ԭ?Y ܷҧlpʀ}{*Γ=sֻ]+] @ffL- ]NQ'tw$UyqSK% ¢VOm'?4\ᵚ#U}ܙsGuE[{ݯtyru볊GU[$/6]7xڌcyH`o }Ɛ`Y /4>i|*-~A>]{ORnu|3f124r?=BBt" ګt٪ L +&+?_ +ty/ockێρ:v MBTCWQPRqGe%2^aԶDG-%a(!V!ى$g46aD%KOPVd&=V('9&Ǝ8$*#y^?_+y`GI6A#eګB*hboXfaaS͇ +pqA37eR[iV%b;j{xacvYȄӘ,7` 6rSp#+@wS8%XBL$cfka\mɅA@L@6}iUh'Q }@+zPLD .|?[bqLL΢H<D.=yF6%Ʋ4`%\;ͪXQmn~10ZHl7ճK{4?V4Z%GЧOÕ{?\IlxpG|<)g3/Vc{U!Q!G]3HU pV0e$85P&N6SK쉎=kw->sE"pHÄ4M*tq\U:, <0y3 etE>~Fgo*۰&6$N'ҒCX; l๲rRW EM(e{O ö֢Yxb?IԓkdV)TP +B\oW| L^472V2qQT`){N`,&59bFRMz}pOV2օY,gBϑZ5HM +%KP#J +э\f e dyi'-V[WChd&CꘆV3P i`j*Zԡj̷o^e ~r5dd~g|1B LB0blNxDdTtLlܥW^7orה;iMw3=frr¢aQYi峪5/j^7zGK뛷mi`П#_ƿNLJd͓7iE.[Orժx +xW]0̤oqfiesgvSS|!g 9IgQث§|sU"UG>8\ddpga乆^\'t{UovՉ}kJE|VҗddCCT08S&r\cyWS>wdg zK_Ai'nvsWfnfnwSvdcbAw`bbj*Ǝ"ETAkfnoՇn2y ԡt>g~n75a9&V C_%Ͳh=Jmn9&P$hl QdOw/x3MgYsgϸcWm8nQYQ.^qGM,Ml}66.Z ,qŚ7/lToߝd I40>ð}\b6ħa,m13ZGuKyO EifQʇPr?q۶vBنfqR`FQeV5ڔ˂}lNp)'1غEDӈLe)0djZ?pF2^ئ[; >4!p$IpkrR9DIgX)YyJH.%= ӽרmuRzY #AE2 %k[Rmc )gIrnPi%uԬ`6ښ6r<SxHڡ7^m0/a' zQɔW0-؁5LOV{>4@.8 <ڥ5c$ok|~y2dVݣ +QBGlZmmh6;csqDFWcm0oU)kfjriJE!_,.s(]fnۛfj/QG{Q;cЧo1 e#,XvOOe:xQ¨Zj_ti}CHd!%G(wp"k+Jx;% o)a t^S0=AERQ*(\))yD~ Oޏy~)rZ?Ey5AqqO;[]OLAJC0!BAyx16) WIVN5 f J:m]tWw|%+%eVT {UZ:iOªWCk7E}+.} y!@ot0/Ltv~q|/:әNhg;N&N6k1&'<1 +( +""(*^"xcu}ӗ}<3Oއp;R-Xo7qr0:'MjqJ-ҦW)URÚe[ܥpi4 l Ր8Ȕ#N0iVQQʊ/2fjr2fd*"t:E=YˮUjU? ]짶:+ H>nㆼWGޱbUI=Jڠ(cTd5 f2Z3W3WP)8A݅2p/鄇1׸ܥyvBZ+OWh "yz*B;[Ti; +dù2B7x@lCyQEn\.Y2ϼ͚TL)~CQȘm!3f  ag>?Y#DUlX;at|cb6gN&2]σj , !CCWG7DCS@ fkhZ+Ӵ(o ec,Jn&y4c}Q *0XOk2a^+w?lm ,jawW%7Fn6kp˲ 7b^D3. W u? + p$vmȼ&Rs,lx.G<˖G IY\O.<͜!,_`o0IA,t[6 4^yyߊ>]0GoCPP,b(d%kr5AR1ei\< |H%rM 6M.8Ų[ yUv W>&LǪ2Jp +4 +h|fuC9tИ0LTdh(m,<<5C4f=)R aG"dXVH8Y?۞췻ܿ1dBc*޳OAb/˩FX5yҸ +pj$;茙Œ#1!P] ON[j7 6xJc~h=Oaȥ,9sxKc.rkzl W{-ajTŝ_WwT}5ua XiO_'/ڗ'c ϫ#N9PK= +&x֝4A[ܡw[j濾8m+n,}H١]\;~.'q1*6&gɅkre<>Ї-moMʆʀ5tj;Nn(oqʓ"Ċ}ײCcDzseŽ˯+_Ʒ,pǺ v$=6x~uMLǙ[ODئ#e)@ןͿJ+@yh@@D1]|4f-?DLjYHuqƸR1BfH \./U +ui4\~:dBJ8T!0: Ee6)k1 KĖNS2/3`K CB!7y͗ tA&<""; 嘍٫En1#cN8iu֙Ng{؂**!JnrF 39rr@A$A9~}<}~}|k82h!SN"ꦈ)@7.x ˑu[2 C5dzDCQ8uW|Ï]g+xBqzk:$'I,DH?HnmV|00y + hґ84gOY%>~WYTlY3MN2 cl)Sd죈]TQM[ ~p~0<@wh@ŜH L;IDvCL($^%*ʲR{ɅF}f堎, +y&`~4p  @ AFHG24y_#zFeqzBTmfңэRScR&o-ZhB '2#E@By˜댫S%4xUg]ZlgRk +ƪXc,Cd OaM-(M~N]LDטĽV1i7CϪ63yㅌDq{Q& < |+">f?,?a6tLj4j\BR+8fz%eR^2I`1t{ܚ~b`@s؄@SFmmtW 3لyܫv5[5rXjfs +&2xqJ5g,º Ad Bˉ}wnOfjp0?I7Wu h%+:K,$Y! yd.oĚ; vu>Vxx;5y1LZ@zf*[CCagڬ)nJf!k<;ӡx8b7Դ^QeS!|%L 蹯1qA&PϏ3 t;jr}sX-n]u-/rӪop6f%(ʩ usoN6`%)O.r5z )8~sgНgotR9efO-sO@eZ@dg@B'nԑ8ݞ85@|ܱv΅%#/\_q +oރ6a Ɣof&׈8lX)Q.T4/ŲRT߬IlmHik!+~6l70!#PJYŐȉ5Iִ[ %tt~qٙmwәtvtN۪[A G@ BB@ !!w@ B -(" ȯa|k 2]Q%TS)q:@ u~U0w@ +LPF}A*ޭ=) 4ofk$j21_.7bHD%iS$ƞX3!C=dCjlD$hF@:% SWOQ2dɹEB~_oXH$aӵ!Voj 'PjanD8hAA :퐃kVųJZrҤi٪|B}<=Ow=HQw5CTMg_v4P::h<-Ɗkخ!r׋ZZtArNV-2vf){َ 2p~  +8 +K9bh|l.7nIh^J>*T<HFTɒ02:GaR( 41|   :PI>Ws&u>PJL4/gY~U=WnG @}$ %"ҟI$q+BĝgȆKu9&j@4I9il@/Go ̷F5dБ 9l/O}"Z/9iRsMV_tP0$ $CmK @p l @JB KRa(+j\Ce|ՄNAT2$]ZuX4Fjbl(^`:`A2a侮j?]w\"g'cm%H؄7*bg,L& GEw%"+'NcX'gh ;|k}?1yZ=N&"gQQ4eFu2 } ^kk +ٝt@#dh:9h /T:l}Ώ!"G#;6B7v҅-錵 vg 4AcJϺOZܾzʶ2#2xuK9.u:P4chձ*Tqle܄ˏ2/\Vߵof'.^>wgٹ&wn6|KK|8? N(&0QxE$I}?[3U3Ő9h#.w]`غtkկ 6)<|^y><@FK§MEd"gZ%þN77}ߵwjǑ+RnD%Wr7݊Vܫ7G&̜7|CϢx(hRZB(\G>u̱,{貫KtŁKR3J|kvzuĒ; ^@PAPVB$T,3h!w >k'~mqх3B cbdK焴Kĝ˙W"\nmJQkk>՛UՀ*j0Tx%b-^u|б]=}zϯ VP28%1fGRخٝӧ&g9|7!:|u ǒHJx'>x^Ͻ ö|B-*f3oFmF{ܕr>ڽrOBz* +rK N&7) +0p<=NfobЎofῚ,`4{o/9Lp1(8VBN%Eq&i~`=kPݷWp| +K*FSJVz*"^pd&<7ocx5C!4P@٩PyVHwWE-e+xt0$]NIQ1lG5ب1Є4;%#Y)eڹE_N([7+hQ,3m9x)M4Jj^y2%_$ ET\ Zrȣ3bht`::IЀQC=j񆖀sЎaH H.[L|ZaiR6SިZ t i2d>C9ۢPP)S9NsF'pKh9Љa2u[gl57ZWJE*,2Glkh?Zvd@ƋjGMc0hD {5OB{@tc"@8NO2yO[stE&E{ԫS#˅VXUk/Fʬ:CEIo f"l@JB~*—uY -$8EiZ 2UШ/4\*& +lflP{p=tA? yi]J-;IwE7Ы1ZQ7ڨ"FJLơrQC7tIQYo Mjh>g@megJ\`<|NLbRx%}c,ZQc.%mܢ)6+fEհYa2{} ;بHbr!} >P?ɳk{K4\iaTtEQ!6iz .w541-MB69u^ϜӧTf0Jr]#AC԰ d:Lw2vO[e+M,.>fِȔkOk9M}m@\>aX[YlWsMǒw#KⲴ\IЄZPC3j> +;HK]L!.bq$1g.5|̀r#Y<܍R}[q&jؽL2^Sg]Ըkk.OzkxZ~=>G@qmMPt)؞vߝpWigp*R\V xefS=Y^* L6"Jf̓w 9 ߽Ezf8s%DwgMaN] @f~(,`OD. NgX&>sMxȘ2f!S7b$o?߾M+э_\yzrt>2 *Mv/*êyr:r-I1MR钯7hգIѩS:ۮ$hC A|m_7g?~xw_?{xt5ϸ_v4Č8vZq;c׭x, @B @@$$9@B HKDw+GD0AQ-y}yw74R_2MR@9u"D1NЅ?67tGb-鑺4q.zSPu`4Xx7vkn׻buuټCP-x^{ex'J$V'$KMŸ(Oט7CAV1yЖѩc];xu١彻IN/X9.`̢R=%zJ`)+O3g*DWTC;^ց/oRKPk(:sF /[aK /v_HC˃it$d+y/2vzp\ߡ=7_ǎU˽pB \`T܏ihKYQ(>ᵫ00dλ(h68pS0K@DQ"9S@/ {~uY`uR.`+B*XlQiS,*; x[.}C8"&&>+m }i68ݬpdW-X ' +S6N88I_b>ZB90VR|V]ӼiF/їa dnH3Mfw>7xcS } +aEdǀn8K,BZ*lȞ`wp^w^8@:$uU"*h3!H--3S6੆g>z7E{#K{=O{٧ާm5HCҐ4XY eCSj)ytci<~pQ⨺SJrƋ̞ƖFVO6FS]fOF @J@%w3c|ЗgѴr*nYR`!Sc+ ̢fytuKSF[sݬF(kLyH? "P|Ԟv.ˍ&BtS~R26}DFKwjZs8:[RY֦άb7):]mrNW[UfO {w >ǡ}c{zo%'jEK],InfT9֪ +NťrN}{]s]l/v^,^oPpd1yo xQף{ײ88bAB:!@B1( % Ju(4I0"XU0AAΞ=h}xm<>rDVIyMeUٱ3G\W(2$͊tR.V)2]v]Ӑ4dE[c:~G?0lߵ3'Nϻ<):X'n7qEZ"4J隂tX%t%뻒]) +8EHU@*Ґ4dB/pd6FV2_v{َT^ܾ6HE#/68"bIsgruLzT*^T(j/}褚Nfӭow~וրFAVYmhQ~J^WKayЂ +uHa۵|JP2J] i@쌠s}?-~G +kP'T2_=u!.2J **MR rTKJEP3䂪3nedA]Pig҄3p3{|G; x |3_|J[Oz1..w%=.=-jK`fASԭ@:B.~5v?|iu5{emc;;W1xs8u@Y_kkSd4)K|U]u= @&Ґ4nznta8Ťk)_6)Md +osOVBռFOk`1[{!/ɂFvD؋qg8sS<]7;@mhND+-O:A&۩A@`ma#@\8 lA0"WgdXKk%ȬF4 +'y2><ϼ4=48hKDHC84[px+R}w{(?D68*RbH!i9j v&tΣkkWo˙ښv^LSR=_j5*ejGx}( +("( r + ((X'呷ece5~? /2%جƻBPNٛPIPM+eUj(g9f30;|} s3r;:[ t? 9XD*R4=[e4*^i=A[yѝ1eewu̖g}N<@ru9Ёv<)PȐ%w$*W~/E 2p>"xΟKɿt?:NcoUd8D]8:B= z#y}9* y^-XYil|x&A#NJjO%OLnbDqS_&%mCt {t;xGTx^ MBOJ3hyH93d +r,_5KRқV@Z?}\ڃ^e159@K@n0=˃νV*QKҴ>N yoXكU+2ꕝ6AE+~Tќ3l$(#Jg@> }UoA>ϫQh|U|,?5k$6H% $Le[&_}5K׫m65Wm! IC:HmZ:n4.P $^ȇ׺+:ԹE-yO3 +N;,iΥ BDDԡjyZ5yP(T@tO :4j X651y2KWs TjiszMPM6T2 ~䓁ZgKP0W ^qm]g 'YC\+1 s*4\eU1VXȬ/ \.l0;̬^s>ЁTwמFľͷ4}ϰ%kŴjI% +/P +!'Io`0Mt04Q[ +ݍ4FL/78 + :p`; +^#<]Ҿ{'.<Ќ +0G'7%ڴ"*'ʑq::bڈfBi-mtY \f%CB- [ b] f>?vЉfs|ΈtrAu)%hy Y| 5U4Ś&n3=Y3tm*v!Ynqٿ9~>8h?5U4Q}*ϐ4xMhJReMI2EclITt7`TD(rYCkombc'ntS_ Ie +"Yh^Rw$+MERw({$:. OTE2.l;X.hi.{kEݍϺiV ̙DsegO0c(vh l4Yty /L!SzA|k:<Ϳ<0-puoZ`_,m_3 +'YW|Ƛ;.{|QJ_8@L!?z@ͅO? KEu r|W-F޻tpbڏ?n^3Xok/lAOWϽQg> i|q1OϒPOgAE be΢>0Lgtz:ֵAEa HBBH ;T@A nXEq_uwT`P, +XQBM@^z.>7=y9; fd [Oh6 %37DiDý/B\X jG]Un-uuҎxDx#"户, +bAu#v`g9AD%s^&+d AԼJcB̙n*,^*wV X> +Λ=k.p r{+.;∐7I5-o"/i2W +|ec޲|XfX9a+lܜaxl"b`:͂`HX21]r<_op!`E1]$DJ|  #!߮"U:F! +wJ~ѐgl߸IxDG|QlBSTJ@5MHg&O䟃Ze/dN+f'2Bx.b.R\ # +q\' AI5?~Tۧh:Ov)AʱV M>K#kSќ#l[ |Hs4# &Q0 :?z2`3Z3xX3tB=|^~C)j85Cd[kKewl=Wݧ2珆Es&wpjȝe?$  +*Szn8F7zL;_ڏa44G0=qvvWӔЧ5dlH ĶVP;:_BB!d}N?SQJ #+c @+c}x]D}ۨEӽa>ĽԶq- ݺF^Abw9H=ɋf#j)6+llO' x3C&Ҙ*rG{zb겺Y2n;8Ox]'un&cd`l\% #s#[YU,{q5_e]9܎XSN[\M΋ pnqy_s$rCБw%s: fBk[/DwMY1`a{LJ?,NJU$->UTf(Z~TVj:"c:8j:8kQ1Oo2U5Irs?PhLTS[Pкak"(Uav&r*J <TQzP[/rZuR}jzI\rLӰ( ِe1|WTv?KŁ@AmKE,C@{$0!aeʖ=&,% pJXׁ(Tks զZbI}׳n_N*n=g59}h*SZ.,̪?om.ngyu^M:gW5neε6Y4$iAѮoDh:MS 㾎S <&}%*>>[\\-Kk,bʭ=*, 9yӂ'j;'w' KUDWM4k)Ҏw}+݁1!#t{ xK\V{CbIKUjMMYVkYq~{QA(QW( 9E㢜)Qn0/F dHR jh 𭷬tc5t|0!g.IH]a}ˆ7:5!puzKAy SܙVRӝv%JK/t&q&:SK&EBY SMҵ7alaQigQ'#!X~I8ď+:XYܘڜUٞXSEwLekwtIqlŤ(|C/ Yڛr&8fRIŮlz~Q0]2@ 8A?p'"V_&mKjLnIE7EG-∦aD aZpF6Ȗ6joڝg]F/Y(ML\]"bQ\qCb&VH"مǣcl>_ho3< qw-e+ 䨭B:}{Tј/8|;4鶷wo|ƨ:P<(I8U)IhfrZC$-!}Wj 5Tk(ӥrPOބ*1]m~7fa[(^5\Ű/' W :^O;[\8P8Q0:X06Spv?_# 䫮JM%mozx~]&sk4pmwoy+AR'GMaa%,H)?QX7UW7-PgJ|g.kag:Z\n+ɹ5rC>v<"5=tOt-X$.YѿRww;yIy>ws) lol,{^$[(SQc*79&й_ע +KM%/q/ \bO=}z= K#?&YFҋdKQii(q߫C @z?D͝GhOv^+;eGb2| |KY&F{.{y$Hp{>+,wcq(k6nKCyE^C.hT,Z؛jejZk/63IHgtF$b# #JXPDz>N3dDhfW꺯E|vo-Ý`l6,0C+/ROBx9w=AX DѬ f@ ALWO!tBCu#Z Ձb9hmȃ4@W'v2@Fv0v{]]=l ^@y bȦB6 +Pe1ZRLp0{ M16@xF_u7U2ukʛ%!_![UxH(/m'8۟DF )SWV`,i@j &81p<^yjP8 +QqT**"{oV& OHBHR@*R@q^ \(({-V.9ܷwIX E,we 0_(K3o^ܾm@;8|= +>j?GXaUx}֧}2mm6:8B f(Ofi"f=s Co@PK޷v9f .vX@H~)Y_kƯ5_œ 8Ü<=t1z,:1zADLG?aewbg :۲"o轖?ۀpN~`A@aȄ)t c<8:H 匄hc^V -gaӈaV3ӉBQoc=!vHy/8- += pe'((I E : yV #&/0 !qSm84k "7V3[! s)N|>DSHLF퍒D)1Z~ȿſwȯ(>k!j:`X XVa7wlT> GF ϻC%˓~%2 b:IxtCx-l6F#g/S>(uZfi r~ںkVnZ{7?7^ë5gnxxJ)?`W5۲CkמXy[W_KQNmLPc> _Cg4HF^ ';!@*J A:=Q-JhW&<>^AQ!Xm,sHٲ;W.i͟3~Usx~Uo;>O8D4UTf/rҳs2RT)BF& +Ka/Oߞ"ACuBBC zJCږܹ|x*/-h3ѲruCpR|T(*`+lDd T"*4%촚Vbfo,QڣM-283#o^;~__=k&7y|Rp]Y(.#u8Y!3%Uɑ*4YJTRU%dYs1IvWGvk =0` +m +۾|WW xںKVl=/n{TYV.“sNQb3JD [B(y AQSpyZl~S6׫ Yt$__s|>|agX|ymW[\[Kw5ufq@\㾁,JMKB&7II@EEZ`t +ETHG?R(2 +RȢ(xzy~^eKҍ뎭ر} 67l?`,o8t߆C1zck(X3M #8tMC85NCWF]Z~%ҽ[TxI)ȫҐcǮL;|jiF|i.Cl}ɏOdJѕۭ=.YGX㿃S?l>2=97 +ݯ_o1Z4 k"u8wo )ϼ1_'T.lHVݩض:o;Uy$S]y6Cu~BVuy[U2H7NGNۡ*;t0?]l˚|o &mFh\t W55K6jVo&lLDJW֝٠MS?[y&:Ƣ"|y.<4;?󉀹X$%6*L{2AB4,NU[*i ޸{5 ET,}XR +kn*k kMG-zx +[U6UݳCeƠvڙ3^oy Z7uT+lU/[K//LKv$`cKKګb%6޴mȵAOsj{yd:r'euZ:R=O%EcQԥ1 L&~Fc䇬|=D47m-sƚBzKoC?M1~Ӏ| {% , +2ٚ(K&)"oHNq,*GT}IW $C _LTCš]Z"TF)#,0wj*w^^&/Dl10`@.e% IX|/ B-BF9Bt7l~q#a} +8MNg'̝/'aLGR/s!؞!2#Ͳ}>AhO+B>!0jd2>&O 9K +sW, @`O, `:`A $;::IwPZ.42l0zNDLu +sakһy^ t ! W`3A  F@0n3!n dңJ#Kѕa +F~VBN!ހCSX2, Jc0 + :ۋqA@$ +mPBh&h% vV ߔqE۴ +༖s z,. 1"oWW\1)A +$I`ev@U.!}A *-mA~,WfQ~( Qt9 wAz:Ȩ0e HOUw ,Z[H _"O-eՐՠizA:^QT!Uۀ3\A̘JzwгNjy$uRǓ L 7j-!tZ?TU]>OUOP)bPl3&yN? bB|7!FJ}QĒ +Ye|`%_dUNV^~W!yд+4YTe7bPsv~.<" c U~U.੆.,_xVQdx<'QN_wT-ѭ]/o5nq7 (:Πu ;ք0`5w%Yҗ[2Nǽ"ǽ$^'M-TkN8g(PH ܥr+ΆU#7⛑:!2N;cGE~ M7 eސ 7,)}(vC6)r$ +?S5XN,g]"ԳmY1I}m㞦kL8l/z&$zÛbB&C78H~"eDV.y>r)R6]s˂IAUhg*Oz#z@^S/e{ ?ZwOslx:>{Ǣ3n$Ux)%mLҊKZ&ƠĞtK|!M~-J~-`&x@"Xӂk?~|yΞe-WΎrM(r_D>ϰdLfg .MBY-h=C+؏ѓi%l@] EKݡ"x>ԯvO +v-~urvܞLRdW:xFaم"q-E8 ++XrmJX1o+=P*qYAB.ҥ* FENx)>x-?bE nWޞIOlX̚\,CmBLQ,) *T/U TDYXef>VOf I> |5˪ +׻=mwlǂqcCΙZL& +JP1j\Jm&Q >Ջ[tY:N+jŏ4#FABqisa֗.ty[qF׉ʭ-~LUtͷ*rsTOtZNed' JYA!6`1C~6&{I|} + sa v~}k穪5Nk6wΥuW{ӁƆM1KG 6:CU9i1L2dM'Ds`0&Z{~Z`|h48^ Tvp vvҶ/5lÉkC!S ƒ3y*r4+@/0g Od%5k 4 ySڄ)L fx8O6ܩZP۳ʩg낆K+=[P]s1HQYjZNWU̸ + +wʦU6*b+1ϰXۓ \̠j?YDnwt\rnW9_Is{ö黢e'rO*?)مhK=d@5mnE7J[n_I^ɢk_:C\0r tq4ѵ>LJgnR % +!qnBrlDu +""^DO';:u;A<pY:huU7<[+q|g`бW~@F#& QH0q9<)P®t]N:t%1t3K3Cd1c\<@O3(t֩ 'w~Gw}>Gua?؊1 $Ե5Bl߽w޴]I*JpL7`)Àp1Ff34$ #@(FK,?`7ۙ3,|H5*$jM=xjshW,Q7nf2M7-ʦ_VÁlowp;B!YB_!dcΆqdk}o׶OZў-3l -\hխfRMz=r~_KuP7*Nƛ8Dl N^&`-!ԏ![lX١e1$kUL(>##DE``>\ mPp˸әNЙZ*s[M>B.Wr!6![c?S| "´T n &rKN8%$hS`IG^JJSf`ar V&Ec}R$%FbWϰ=XCȞ:Bճo$d3B>#c+0n|||4??h"zzfF&#!*̄8&hb"a+0v` +֪Ho=&!;lOgOl&tu0c>c?ixXr0$Pƒ@u?̡~p0^ALJ8 ( Цg#-BzIiJ~uDSKd^#^ 1x/E#>0X@0$O7ea<HPY +dO!c/idluJFMaa#ދ @ h6/*aq Kh4H-\R-F_u2 8:N +#jXtI$iO^#W4(o ?2Ph3VBiΣ )Cլ ;1|,dt#+kꔁCެ `3XP90ba'Cgq9#T#]~']]>>W^O*]ʛ=E'"PuTE  + stl FN% K1dS̀rWD׭XRlҾQ~}th^_ v5Ui5+뺘:I }=82N Sa +kv02"P 5J̶{LN据LJCfMUЬۡV骦tWܬy`5<;&r# Y@0LTd!?P6Z!,Q&uyŭ{a\`zf\fybW#6S}{#i/Y5;[o-VZ6j>_h>%}1/n +*S-Dt/Ž,ץ7٤O +4mswmͶdmVg;hݰ__گ:kr:CswZ6GA$̍OfL]߿ڹjYN|2PR/5ʭt:]wq^ulr^鼜cnRż\ 6iWAkXPQUWOEvdi;2qr̀UgU-wҵenOEss.ɵkKYv]S' +?/]|EqUaOɡ{񟈊1X?smG3~YiJ[\}RE OV GWQoCG*8P\[boɛ9K*#9`YS|7Lxt{8`nj#tA.ZK !3̘ 3F342.CY\JnIWNw<J-v={|~o݌k}a+8PƱ^ +%᧔̔r;JRO'˩ NjC M2NS<եJ}K:!Z(gˊƚwx^jqՔ7Gùúm4zJ3MmHi46Qʨ&2F%yYA~Q^30')3TAenBOb#RSrsJ;{2C;.CD6NLjJ}Ffz Ǭ +*RV9UFmbRYREv >^$_Ez:Q PUXt*2yiYqg0>OI,z*Kb^"z'OD x,O+VE`]HF x$2T_Xmu{W8xPl-ro( kI2VfferB0!3O1[9~>90`Y.<\䩂V#@MjeP fJsL)mVJc uʼn(fXlDbU 2Y& ="g;`-YrUA} +_7Tٺ0`7,W]t>[k,[]1'NEi|-etn-+"T^(w07U{*H9+s  >K|%(W puƅ5M^;TT[C..%JSRy +)l!)?()E x0`Np?W7JZث4h La7JNUmP48ȕQG$,N=Adlj +cŅaM@,'GKĢ~lj(EK V}+`ZwZaU0m;m嶱פ-Fv:MH';^WTasP]FbRZk*"Ҁ' +l{bJ7=~: [tynr{B2]щ Idrx[zzh7=8-]N hL;q;5c>5m +^< 0څm?lv\YQ3uҫ .{]$f QB Ia1}}TRP_6)Ot,21`h@8#xGU `B 0p,@yۖo9onx9'xŌD]F<4MFFep0k7B}fC|FC~Pe^0]eЂep۟?A}<<ԇGG{ײ:Kvۑ4y6 Pa"&wp#dd){J=}qxz1Ob= \h ǃ:ȝ3g͛$>uN|j:?;4k.spczdz6WC.->wv]E:kXz.apb +^e.m"/M\0^kd>k%7{7>N߿ tv}]e2bGߪksx-[Q%}\ P: x B2>iawQM6ܵqvO;>9Y|~gok/v_ímYleg=UZX&s cn.V`P89 ` @{Ñ>Ӊ@k}_dd̶ۜ=7A.VcCi"D$3nۍQFtj*~ł("-EMr$@Zh IĄQDQdP]`È ϮOT:Î>( ~}>?WlBʻR܂9^!Hjb0*llaXꌁ/W?6ݽs,t;ĸzgXHpPbo";Rߊ w?X/*ZaTXۡ04ܝ=a`>G` N6h @k?f<"~nb@4x_)2o#nHp5(գ^r#(H@yK}Ǿa;_?H2xM|7@LT9~ , +˨_L=$Ȁ]E~& 2GR/Pss]: oW`g;Xb`= + |PWhUa@ۅҪQz-u~ ;2l Y~v7D{8g6Y@2xt6."BY4x28IЁed,e|gnb Ӈ郜)Z?{{HIt +(؟<}$:m3B}@B@<}c rx쯼rV WE+'0sIFwF_N}GQ;}P'F4@2_ 28RN " d] +sHcA)>a'0-,u +s?*vp y\~r6.󕤍&d>pGyOC@8<b{i>@!B m>p7lTx' nCp%82$zLtРNj{J8SNy`wDh3E/F>(>D>><$/ޓ]ݑ5nE݌(6DCe3ח8ځ` 5gꨁ4@'t fUK}ەqVyq!A"ɝ赒GKnl6ތވ^=+mk^{(m $ 7q>"OAvJ#"y +ݭ!z(gmO.ul.=C4-}5'B7W+Mˊ]]K,;u:=>;DpD=fbl@4LnVj gd|Ck^,Zu!27rYY3S*y}.ɤIuc:#gCɟKP}~]_oX5lAY5u +Nv`51JcZ7@o@-o5H<ή"_ϭ)YRݝcTmIl\42l23V* {eڌu%縮^c`XC%M czJ2{F"Ҽ4;bY?~Y#g(TY޶XL-3\n*5g*M;טdNf2].4=)]9ԓ3('aȷ-t"mi︆Jٍe>qJюȪiK?/1/ )\a0[6m\C.`0fȥ%各"Jn$9{vkHK;>~yίuޜŋϚ7wyZo0=_V.ϓU6R+W.˳e2Ҧ2e3ٲ/dsT[S/Dm2-Frn6pՆ霩ZS-v8T8JXU,/1fWNjr^<-GQ-ϨVg(';CkvY,㹜Ș õL[SfJ`R-F}O 7]|X]y[xuSH}[Cwmޙ=)[P( +TF6E*^1S(cȉW<ޖ=59FkhbւZk`A n6/V6l㢞&?fK}`mKeUϞqaY|DNqRBZQjZb~"./OWw07jg*reD9yOT_eͅA}WXn7Sam8΄՚mzm>QT~p׮Qܪ0[Kҳ"U9[Kaŵ9a% +i@[%2ED|*5[)jHq`s! t‰nŽ.e͝ƵBNacIcgSD@v}Lhjm|L|urrDeZtRDZY!<.업T\5*bG0&`b/up'W'+*t +:$n9G|eQ№xi,YҠL n(I n<]x$I؟ts[Pda&AT*QT*i.n2*;MΓSH׃3 e}F)dк㒍I[6 + 눏 iO jW}۾;VQUq:*zĦ·H}R<,#38p``t3[ Ctk_p-:a8+tHrmHDMYa"*4Uؿo<ȯX!DY2׿ +7fG!GHBkFPvR躃+5㪧YKBo=C}"C ~C +|}{|W|*L{? :zdC=I!&ߢQm(Qc<1G&1x$Ix;vvk$wם4{w;qw?u!CWjnR g O졙z GC3-h|oGω(Gd 'KVuw%~T3r#NLazNYeT[7sz]LiΚzKǙ.Ë,wX/ۿ|:5rtz_NwD$=QW_QBfil5r^M\^;ҝ޸0xٿ7{lf>Ĵ`>йhV;L9L8n#\$9.&_qG/f"H=uH uݑalrWڡ 5梛 -0ИWcJ&SX`Dd`y r̯(jjm%KQo#H7B!ֈkLh + (20-˗c.Ks#/Lp?d_x +5,؈As RPCK-q2s\@ MW!Sњd:-AWE譫ej(]JoSy0D, +D M@Cf"t&LdULd dgE-tO︟Lpf>Z`fAEK +D1r]ih@j9Zb9uDZ!͐{ܳL 3Xb|1?K wkd΅tC`QgFEJ3 mL&)lVWD>Ѧ_=-t#tqR26͆i3vlvgEn]uq*su;#{t +}ܯ?ޏ>> _P-Qms?t;qe xcV8[d (?/g"93Wⷠ^ 3{P,N'SGCRǃ!!Ҥ q.  @YBm~] 06L:Nǐ\4W\Q~L0AdHd-~Tp_QDD ϣ$_G%(}'o?c (w/~ `9.\W?m>p068(O,߿)h5fcRv`nTab0iSoQޤ [6> +uxЋC Tf ـH9W,5 AY1rd AG0g\"f& eޤCh25.zW>\/w9b|O y}|7u'©8@삝$c Abk]ī:iۂWJ2$;$Ys= s 5&Yf+4tytyt5q5ɚ:X; DKA{I6}7}˼V#jXUR"#%ekN]lC1vUQv]t'%'N;0${r;}ʝ~ͼ".V@Sg^oq2{0nXqMCqp]c|%313p~c{b!2Z[nZ+v?O+I#x(g4@܅ [l{1j9N&s|-彛ݥb%RAQ}p3EWXGX(cKY/<̬e +jì]7E3DU vB X0@2Г\[^Vŕ< ۢOo!f(1{eJF$ ֱZq)gx7wxJ|[)╋J/ay;_ot@dee[CorA#VНP_墐ltؚЪm؛.4dy*Zū˥%2iTڐd&}/=T,(,JG[@%-̇dRoY@A;j)T1ɡcn_o؜DɐU*etAUX,O. CH5uTzS +^DvYMc/eՙFT}iffG !1j.P(1 +DdFAe5,g>*#xܺu{s&HY-kURܼ=yekխ^wcU\Ì_: f~FϠ!9Jj2D~QW}=!_sToE)q)+ +2Ss22b)8]pcEtA[JT~oJĮ;GSuLЛC?prTVAYDITz_VfgAYϻm9E9(:^y:ii]:6?fiHxMzXhuvfk 46&8jPPBtyK2 Dvqs5ߑz~~u[m0'皻IUo+Z8uX}OH}_P:} lP ho_.YOPr`[n͂Y}GێFiiI;mcrac*2W[kT~66ti*vi>\jeiRxޜT3FzW +KzhOR<I=xt^G G/DmbUDdU:@ۛ>)a 3Cnzv +:C/cdK*Ksӫ$G{{d*^dd({md_Al~D? x@h7 Y:2]Yov$p:fx=zd;j&JG/InJ?Ilj_#ف;] @@T@9'L '\D1%5Smhiw%,PK38p)XBc61fa5u9G$$3'3A};6( SЂbVCt|}3 '$"l rtZG6L(Yհ%$FB: tWѐ_GCy +h~:-zB MGDh:lfCB\ y3Ș(RQA`"6 +SX(bpa ={(:H('T2Т1->K_OZޤOJƤtlPK["CwYR@KK&Zٳʝ@.J(YA6J6rӒ])ikB5!+e);zoU9f7c1Km?1dAkkd8b:JtQNCaB~\gcL0|qAqˠ *0HDICv$ {N%$ +@T\^ю9vuwnj"ppPawE]Жqf I15rbEJ2ݚ.Vg +զ|E`V&AaK_}J"2FTQg.x +N +Z%̫(za{>qe=VkFUdH %Jz.cJ1r5bRKj%4]sIy"MӾi%kEiLPptǹCZ\0TxtZBQH__V+ 2\C2ט*H͒ufyT)Rt +_P)ԺWrgi" *n`FA1 ~g˽`j[Ž2ҷ,ni\bM92qL0ȓ9JXm*Y%sJRB+d)LPp'Sw aJ߯v}v[ $T11%^x^0&;_J2VJFNˌFؘBS%0(ƳH; +[ȿ䉙 f*Dm 0~)8ҸPv~յU5rL+3Tj4O'2ɬ*١ei)<.a_JXI +G|5r?T:Qhvvghcm1jQlr"+S!ϲW̱$lKeiJbYLiA6aK&ip&<[3\ 3h`:`s֭#}KK̇(Gm JQ/! tMfdjL[asN6̤n1h5 J&jED3y {2;; @[v7`Ttb\K:>p!icvʉ,ptFsQN;$QD@lzCo/9- |`+tnjPzB۱Q4o>?B<\к2>wU$Z\PUV:2Yt;+2)9!IEi kBl٪UE I=܍P BN!4B*Zexpx_U#"Bм)(7rݥPF#9eo6-ؖiTt6ΤZߧ#-G-"֊L°RAhG'iNT~wokރ}\6B[3ßE ] dH vs=]'kmo>W*GV=!B+ o s[J@52zx+8a W?'FH4_=j#|_3yұy\f|1#~Mo`U|ߎg <% 7=PG8L w ,`js|+@.\ +Hp! 9쩐B7^vy"3ϸ|Zp ͸!Y: +ASBFzˁŒ&A恒-̸MwqqszwL 4@Z 1 2+ aȭ\~u;q.Х+9o+q&gTfC cyIm@A_  0,&G" ^!f  H6 Ncyc>Gy}y3ewPqӯxU pzcruˁj10FT) Τw>~1 F#U?_Đ1w;Mk.^hZyO4ND>9ĠVP@%(Y:2%}y](~B iW /[)Ao\Ot?!z]$a\x?AŔ~ԇmAn|8 oP;!w!-_CE Ivϔv8VpG 3<F:fUaC +)y AIiYREZMk6ڤ]a-fxI\xvxzz9Hp[8R }S3Hp7 7sf ~Η2\ϧ<ոo21ȢHmOLoI00兌rSD>^Y+2JrIqT \N" _ >ByƟrIp u9c {[+HQZFe*xFq"JQS1)YnV,T1.V[[l+Q?BB!yJr phLy;C̋t[2#-钀M"ZaNF٥*#XeFUg\j0.O5UgPޏ73~TBE Y@7_JXQ E[{[s=qjʠeP &L;ae?XAYw;\'5H% +F>2Ӳ:MH1M8E#VkFIYJgR\^Ҽ$iB9wȻMwvp =aZ*wԗrTa +Ĕ tAeƧfEt2/"RR|f?'jF궀 ^j[^Q*,re4QՊ P,jebE$"а">ElBh*t,oWo O@O;X}OR76Dl5ձ<򪄾& US*QqE /…BX- +;p~Q| p~3~<7xekD 0۶:;@KvVkiK΂&F옶^LI'T)qs*3eMFgǙLq\e.׼[5]*#^q:*>@7vs߂ݠM)Fc'`ݧkTȉRISy lnibqbb؍HV㣈#FE)z PSAO4!pJ~(8s[t])=q݂SAWbH\:<֢g- βtZiѝB-(ˣ`fjDЈ֗4[v%"͟EeE E+FB]?ig8mT|K1~[2;֤heͧ0@% :i$GXaX?f? }J}o=,̣Ϡ;T!0LnK!풷c$e}Dx1v/g^>>6~0mCc^AχG_;َz@{G78 P6= ]IsA1wN6F8o6l3{9> ΨCfQgKRg4{aW썝#`]Wmut)4>4ͮB ft(n!\\N-c/yZ +@_.1/qQDo XN\ojߊŕ2wegF/7[aх箶@r?sͮCn$/!A併@?r Xs&Rj28iS(!@:H0Aİ%V[\=]*(ذV֊um 6EA of?^{>g/z8L0MP9Q_9W([.B1 +墐Ԥ_7`|9^\k3G:0qkQY@]MP΍GH +ұ9lj$z+=}y\gos%VB߈ J ܯCȷ!M#B +@ )K]5~46l +b_Z)=@y@@H0!Uh"<@?r-C 4P.O_r3s3O.5i%ژnVzHA.' l b&3^|gp1dz/-gA>-(½'!Kt] ;D7vQ5*'>[w";$Q t_ }d*,( w 8 !!=ټqŜOVrdN&CnTբ8F5+Q{e%٨#+G;]L#p^:7Pྒྷ# J ,Xp /#EvN?\r[T˹ͪ՜;I]4w1oJ7nG3+tC{UV\sX,B|+bFF<ɵ"}QG%αEd/D=cF5NGu)ʢ@y2N>ގ?-F~ tIi_.g$3Fv#v"yK_D^>p1KqθYqָMqڸ[┱LyxUy|PFp=`> C ɁDEN4U/xQU !;&#[R\sysq]Mk|թN/STV1JM;TL\7.1S\ԣ)2g A88C-"T$C#Н@hɅO'p=i~8ܦ-kSle+,Z~mX}7ײ7RRady?b_oa_#arhKEfB:{cit}Oe$?ZlK*JNoOouuVV뼀[K7Y37Z7f[ Zg=z9xuRuHfRcʤO+ tE("*'wkL"ХЙ^ǦrL(-?eh6?=Ր66ps ٶ١Yakm22mYWr +ϰ/O)X bIJC_R /H "T;!t;?MNРC bLNwʛ8Ty\ou&N.bș+Fe-ZdҴ2 kADA-X@AY$}A@"@$,ְM,BTj\ѱjS;L]PxB/ۙ*93ܿ}y}{Ň(QJOԉԊ_E׊!f%ff6c +*o𝭲b8Q8*n0޹?+O%K mːGP%%1MIcFZ'Hi$'hU q813M-yK-,7MOb/ŮQj p|-p[}1m%mwЧ#7%5;-IU[+UҶIU:ze} %b +S񐩔07to$.fp՘Az\G֐T.ث..eY&mo͈gS[RY XVRɚJY'PQ <Nlu##{̕,}` |?G50T ꭎ`MO;ҶLZ_%'H NiOmk \6P9Xv>vjގHh> l.+8'{=h췅7'Y+.c8>I7ut0 +gt;Ct H0Cwq=]UPѺ^S;mfN#׏o |phܡH۬%iL|}b?>+ A8M?K_XM/%48s?qC%G /72G S쒎9 + +8CՐk(1Ԯ1{F[I1uλEnFkġÇޮ -fs76 c;u c<,`%lȅb4VD.0V[{Cn0u 1^s9!xtfiЩ7NO}gGoI'cy@yE2pLN2ɟL3XE(6xP>Ĕ8x<}<( f]q6O x>xn_,e/\/V/| 뉅/ XL +g@x/,^%{ cM&p A"[?@cNIhΆs \JޮAB*[ .tOs=p았K)@w ,`;1$35Yx ~H>Xz9m~sTjt>LTf5ѨIt W%DJEBTz7"bk/"dx\^g~~3<7> gJQjGG/.&)$#GC +$l">Vl']0 0=wo,B? x "GMWO\C 0 בXE (2%('x;؋s#8uￊC|yO'"C iCl[LE"DZ=h39?(5w7dwxMVd QGdC1}z؈A_yrwdjGs p"s_.r>X,^E3ͥ<l +J)O6`_AH5#lvx  +w̟,(-Ѻ-'KDY Yr;(Gq0g:o1zE)'VhYXPSSlWQ~wmgm/ݶw+vϨ0ȚCb&9sY݂k͑fW[B;zdR]ub]}"ݱ ]gB!pn_kJ=H=ͥ@;͕6Ϗ,O &(HT5kt ҕ3SӃ3eYp1i!dd=a_Gὀ$qIO;*3ÿ m( +R3R +T$TX@AA LXXk\hƬbI,ѻgx̽ywO~}<\^ c-{ cמZ3ǶM}urY3-VeDd,sZ6=yiwbjj”))sR(f4(RZ)1)71ɃA1ɯc?& }kpȗuRl/4CUbZINA^њб#rbR2&\5obtyl*ELZQptfETnA靁"""# +#%p-,#iO؇KPUbR+LQ),[`U8cyv_=$e9AY_go +>Y>!/}B2 F*kp.w;Mw\TV裴~+&KJ̓gY/s]85 3"wX~Oh~!_7}F!'=+׾3h0Bb >Fg|dľJce+]VTyk/dhcق +blq +/OZmFY{p:7EWEYy 砲+N%CE\nf}by}=yϯ`U12wXagɒOiRFm%&DpB Wf:) ʝvʃ6U'U]4d׆Ov\a Ζ'os?[;k:}z,i=WyZqzv3.2n~+Iߺ>u;,k=fU5kg/̧Ud9i(݇w}<]^K~`Q +6c^D7;#hɛf7Fik՘d6qgchQM<5^4tkԽ]|4,ѓ̿-zMf{ѭlvk;Imjmm +p]8}օmK躴˦mqnۧvD˱o4'<ղmt95FPq@oF+kp; +Ojc4:0Qܡ:vDH:㥓;I;WuvnTԹKպEeb_T&tvKƟ|by⍪wj>Dn欤.=";j?o 0 .LM)1Ply1\<ŢDf]ݵ ]M0:î08 `phoo6I߰qЛ$bKU`܏bR=;Vu;A{:$dB*=50ɞS?7s0tc+N;OB- "H!y`Qߚ@ <A7G\8яY< ѝEw2|SoO]$5gĜwaE 07#Z8߫XT8yGk7`` ҫG1 ~B7KWyOމ1"ɚ|aQXLaJ 7@fX-0Y*SM@Xe"9QJ./ф! x3x,] )|JoA7cl UQacX"L{]LoUu;]c'8~+O=~Ex3QڂĈ111Le !+~Ţ?Bko!no+];M>[046x e K5}MALCО NꂪI8$QL&z*I>~`PRI'/=7g׸/?INknWp<,@}mO$σ'f6OܔݵE྇ ܣׁVpdz w 1p¼%e;~.mAp";$ak)[ <yiȗ<L% o7`3rр3Ns+rه1w#X#,ku +9Ǻ`3^9~hs/Iٸ?P3 F$SSGDI$͇)I´B2lx5iH涐rgȧS!I8y7cww(8%x/)c<d/]x8 _N$WP{p/ld^ $ ?,ts8%,r8)p8!qnr8&lu8"RECAQWKEO ~s#zO#ė|@?%OH ؂hDD؝)щK'ӜuNKM1q-uTlS?oKC{%L.|Kry@ĥOC+]G ėPI,O̟ per0OJ#.#ҜR=mHjVvKi&NitktutԭW:M:#Eأ[ ?0p(LUѤpbmOAYNY._VH!+̞d=Vϭ-e^ݲaNٴwOgM!#3!>P +f`=فt0DFCSdzoҫ'IEY^%˭~mNy|JJ|*Q> [`uW,SބX'6 +"pɃQKw(cW%һ +T[JN@ lFKhemjD[Эu =F'U%V%zeBbU3+PY3y"_V)嶠tUZl-eF18έ 5lL *)99j:/WDJ)*M۸f+JJNP Q09ߑhyPs +([W@UWLkUHiEe ^F4 8iWn+zQ<*YWEratd@V = +^e>,@?gkaH_5|-zoP_""Hk(5uxmeڤ`(CRKxF X`>~qtz)^Wj|ȕ‹-z ?W8= @7}bL([K$N8WuC.% c%UkBכ8s Wjn wƚ3Or֙1?dK*qĦW! +w]Wy +#dg;k m0P:dmZGukEڜԔ f2,yXK {cieJ, e$Hlee<3 9* m&jnzy(r((}八fbZwg_?><ߊiGz$~UٽJw kPϚ!sb%@&dˁG~/f&eĨ'2ڎ]9C]_Ok7/;pi~C}ӠEI5I~]Fa+K[_E]:5XU& dQҁlfaߙžksCJr"1^[;۫ٯ 垜5+)k1kWB,jG|V{B}3]f^v]}Ő-fU{9{|^j-[d(5}z`B{"{.ESQ4(^~0Y\Cbv+xǩo4؂TGCAZݢ  vGE"h>,áKY*r̻ZXy|\L޳T#Y0Ih)k1FGj#way6&Ēmus[=6?%5]f[BnNΖ4m#{R e0r0i|*GDU H!'&KäRkd&Z? Ekk,x[&xVނgcׯbμE\\<$][n >iWxg} <0 Ґнq6M5lmh! 3Vry%3/`YU}c0[4G)6M\n7fd^|AKe6EE\AqK/̵̼9{}098 f+@{.hUCȇ@(5׆·u^m<۸nGCqඦ\d'{3Of1<(oέ_TWjn-zh#;ɽ|Ax)60* N%{*c̉=.0eؒ)$RMHݥ~ɲzOg)@|ʺRUaFZA`` ~lY XFJA&99,E>Y,K)-g;&qsN.bΣgQÙ8Lg8k'_"*QbV}U6cA'D00WqYLE84㬴_IRFj=T82㔪'p\>K8bێF)WP;FqUKM]iM 4uӎpiN8-q8꜉#ι8RFw݉:8v 5nюjnNU%ʼn|/AO 6מ='}F P` \,2TU A +9\K,?=T_)A[.^6_\EsPpgp(xX{Xg_Ž!{B!ZCU]5RyXTQf,aU9^֢~C)1(L)6]R!*!'n4i t&zj]1Wc,[g,622 jaX;!b_@ !B dMl QO"8nxqicם:v4Ӥ[bil̸xF9wyrx-byF϶6|G8f1 +q&KĜ"c$6}7}f~})1@>GuMX<&cUpLk7vU+>yq k +$.A->TےVx$E!MRjl"[*~-z|ɒV},%!W <-\Ex&kTs5ԙn}/ m0rqQvLǑʆ84G,[Tɶ88"-P[ P,E$^ zCMԾ>Z1o9lZ m0ʴפtlo.oQhT Xy)U(RĊ&Ne]Gn ΐ.[N+NZY.{SZw?T9/6YkKyowpow`DNڷgg0 +vlwQ5hISub!9BuSҦRxZjWmTVvFJ׬Ǭ"SVQKĶ]؃+G0sqd3wBw0t@GO;˵뀷*, "EڪZfik#iekzR4cB2Ws2PsYX88I4dM=>{p r^" @7HՃ_I/HSV]( \&@׍qn#Н9}@w/*QtnǓ9=~=Č, ヨ?pWQ/h X]DZv4U2Bx!aX^Y"-Q]<|D~# +Ʊ];=^DQq$f) L4fY u`󠴑{5j@Pwj@G {r) P_]<螿X䕷P擽P嗵 43~CY4:cxғ='ϔٯY3){\zۈ 4>n]hXA}Ce7@faNs]vڿwO_zpe&ۤH1 Lnɦ5$s;'=t_Kʷq+^qـ~ԝǻ:nhXc(:Y f@68ilKCi!-UNS1cw,3,[[؅oݱԎ~oa8vy52*z=<58~y khkDYS!Һ­vt+i[ !Jj!hWco_(n} >y.4̮OCu|qu~v:םs9Nαai)ItoQ [clmfvw/|ޟ~9?Q&[85{9v=aӬu(@yDH n^&G1L#w!RU@ ^XgyIy/0`Fr>H+8t8Qlz!_)6/>mx񠷭u? W_ +^j$Jr-@r5Уq 2g*.l8B/D ^MAqSٗ 9T3wPpNO$8-)4|Z)8fV8ly8(~E)hT֡Au{UgQo}{7rP(`+ +H'x\E +g|%yeo폓&wQq82\gbk"m)ܖc{sQ{z&qMqu1⪰Iaa maIa)2uCux:GR ٬.lRWI +{%ǥ꛲|yjAU V/<}gk oaw0qu~6EV!+ՌmLk7kȋ4 %tzm@N-~dQ֞WPfiQejVjJsw:_Ŝzl0l B[p4\oU>DQVn*SMQfU2jJU.W^h^nfEAOm?fLn]NxlW<:ߜ&lIP9[#E%޲A:E@u65vvvYv+Vۥ/gۧ;,ӗ:,W;.7;.֟qZ)Y)yS׺|MYcl Q饒qDM}9FͪḦa醱N ӜR K S ΋ . y.Ɇb$C<>D)9N'n u? ?wDTb(GXXe}f6$rbxIy)t9c,G^3ӍS|w㍏^*<6+ߜl[X +xbML(sxoYTQS,F$sGy\S,SLSrnSپ S~{L-LT# &š-cX-Mn 9\(J\.haQ^3,#|Y[&MlgY8ђ h,h6x;Gc߹H2 3 +l2 DAvG`aU6dWѸhmh&F5f['O㾆k{}9咟7N7XK\[#dP0'Mtse8)].m~<Ш"9ĬX9 Qb`/wʒfΔK˅i:W5E+JE2!Q#QBg q]~ @X |8r+1uC%h܂$tnȽ|}9vqDC{!Àш>F̡;2G]uQƒxDBxLxG#;܄w7fU\s*Ԁr/s0}@oG $w +|6ecEˇ(\Ɣ?1g>sB^@6l 1Kw8<΢3IWy6qUq Nc+/` D3s}6܀loif3r> ~E?6Ib99zCO^;zԟ1>/ɿ-r#Yl6٘=uyDs= Lt50 & _dqR-ď(3 -x=0P.1ɺſn)}C4݌11+n.^"(z̠OI_ }U6:x ^zezF2m,#\㪮[40` :1X2YJ̈0|8:Sˡ +j詧XKO==\\|}y\dDx꧴ h10}1/ķbLWȤOIO =܆05p{g=j/=\QIi! +"@AAMY*PQPTKTL3-5Ki6u.Դ]LsfͶ{mjgne?>x<jL- sqa`d/Q>0dĜFaPW>fuQu>B|\q8hupw,8_ۀ@?7WfLԩD7Gfi 󘓳?1g`}NWkpc>O 8џ{KSa?GbzKS<ʏ p?Zp\dlX,s$9V8ñ*8Q G"` +f"a:rDN~LN +a) ?%% +KM<;,w1+Ap/DIc1J8phY)L/\Y=Ly`2 u޸>=q{a4iwQoӷG-%">Y!I$&;U*Z,P.KB&޷ϡ-`LX +bwJiߠTE$fZF*Ӻ$UNImC됴K{ۤ;7J[s ҅z@A-c?QOQըG :QD°-bPLٖBݚ%ˡo:dEJmi47Ehzd]z١Z!.B7:ͻė{kzAη?24v0%}YlFBAQ[!kC嵡EG[ǬVYN|XrCI]0_ȏ5r/q@8V!bp=q٩%À BܮjR"![Rԇ(,r)aUJWS^lc;=lrS)G(/Fؔ֬G֬9֬,n3N &sze5ADMyz]z:2:Grj"]]QvruuKMųhxŚ ^(߬7/P/P3@kRy(8ðGQeVs\h1ǑLI>u+ncéW8ԬVej6oQGcEg?*LrWyw(ywKkL"dslg#kAP"dwSj_E-^`*WJ%\϶ڄY֊Lkm- +3l#tۡ( ?zjjyO-~O-.q }>_{D^dJ1*8P^ % Dq״6* +[*~ki~c+/ձ;21Õ"$ ʞE*r_q>,2lGq og k|:ֽMʯKJ5tպLw3mOssR\vԵ#qm`vuv +[ftfo?]3Vr7I:< }fmN޹ |qkN$4'hRGuGE]q;p"*\Df'rknf7D (0(" eVڶ{ilw˲mMr{?y#Mٳ"Dޒ. +gfKBӗ~ñrc՞oEU%ң1 +Ԅhhl~qGȼ;oͻ'8+obkjL=]9!`1p}_ H]A_^ JY~=:xh* +OKh4Pؤ1%aN3eo1QLV{0dF@j\ېl[JkRI%2<9]#y`wk~гs nJ|σ=c4s4fUiSfe={+ՓeJn$y6{7y=ExjS\e_W}+W/)-l\1eWL1^=sc*؋8ieDƲ +Ws;|3+)f4tKCI񌈽- +TB} +*To|dM7S&ތf@0xCu鶯<]JOZ/-'zp7Ii;>-R)Bc E1h7e".{9p)vLhvЌ^Z΢/ˉw!^N~ȨgVr.g 9 . %!X4ĥ@'b$,~_7~U-H >'|_³YGJxs\q _nЛ-tQb}Ρ 6(ie.5yfp +we_̹n1s1@D:J4^?h2g~˜2.e% J9sg?UOUdCW3q~#l>Y/t uBك=(> +w.xR-N. .p TcmU˺v !;>DMu{zG7J1p;ci!lV\A +maUc+%ҌVJ*%XK7!~4ہQAGXe60#*&''V)nalk->ϑ:Spҡkg'/~;6}™ g'qr8 ы09$ j`]z^=vQMmdkїe4A8[|EmJ WMK5mN2m1(0gn<ľ(k.^l^0;j.GyceeMr?9+eQ_ۈGhǿw;{ VͰr&*Fsy9Z|Z8l`LkǭyXW;XW9WV8 mf۲\QMw $#R-($IH@"p5\EejZZvkzyug[w?ekמk%{f${)8*_ɿzz,8[ +}-jyBE E +с,tQaԔ$zRUWZcZ_;lVzy>ސr7o@5WTG=n 1^;ʻ qm>/Ӱ@'PKukY4ь +DE))ja? b|FAMУtb;5c^|\d|f5YУ-lRŻxwq8=hݨ:XV,c +7h\FX2gߧ7zt]8ߡu;:E7* MC ;+.ݚة^q:p~ W%8f|GI4Zeb\^no1TSZZ#ݖ@Tk`sUmѕj~EKilYQk5bOT*%XԠMtSR$$c$| ήmCQ7.0& Lj3DD3AȞGc|$$RbhB$ )(.%AL(24AOAav:&?s:{}ANlE<&R%!{.'$.񈽜H%MFd&hYp,Y^FsKDOagq! +cK`>cМp&Anhb X"J}("0+|l"#:CzFpdu| à+EnP?ѳakgȇ)k " .&ʄ"D1/"Gx `80/'!]):paaS_W0?;Dy}:w=9<ל"*WUD9Ls( +Qt1B!?faN%9ysz&[07!rc7.;BB8uY p "( ! +'^ +Zj6 usZݴ+:Ugk;i7{Y>*k|=|y}؟JL1}ɔ[dN=9XZu:O]rQK:+Ӏ,_edva_㓁9FDSTWдBmqJ#_>g%y?qE Wԟ"m-w8( }1J;FQ(>:YOʙW̙Sµx|CEs&?9 q]-l̺dyS!Q_Ιp<&Dgsk7w3ps}䔒 Y/XF +ZKFa;x/.Er0}ܳwp-#{-'U!d.P74NoWSOf7?C8q;ƌc>~ccJ }/#mOQHF) C9u,a[/Czrx|pg_Sz cWEo,9Ym6Eḍ ȩaԓՌW}^lc 0/VvV6V6ҟ|Z~ra,02K +;9yܹ>!!gÈefFv#IX齂oGy}7O d{zpP>Q1蜁])\lcZ\҄-e,F:lcl7Ɏ`iv-t~R8?o\S%8(W/`#;=]~ }آ&U6JЫ*ScVk 5n^CǸaoas_Qny,[<^z$70~µ Oy|.85؇4Zr}:ViJ4`ʹ(%+Lc:htVaDVqXfA2Y2FO/==o}2 +3Ψ~+%vUKLw1Lj<o'MX2xh̙({ +wl)u4fҨVz5M!9r.L%**c~VaEynXmY=gDأҐRb=R&EB*Qt=@Pbit7u0nf#X &J-c.<>v:rΫIRr)Y)nXX́Z5\jt#TpkIkX' Bkeut[kpv͆=5`^K u١Z +,osƮj"ı8vr#:.$|r4z= ֳh<ӈKt]Bz 57}X9b0#vHuk'~~.:sr8 79߬h(ܞ' +Bzh~qx4V6pn1o1ǼU+^k__{}~@7:>Efh~PTxŕ3"89xKZ 2Tws8OtRtخLT/Z3ܒ`ej{jqA3XȪ#_kb-W_RUO}gqV:豎B|Su&^x{8qp&Ȅa1 F.qLqYg5u]ئFbSj z.up]E|ޞ3^ 0`x#`Icq%FCGzZP-]Qkgz*=DͪF2-wRpȱIJBxCጆ3<F՞ 'NY/ N뿡Mzu ~qքv|7g[sUʐ8['i]P N+,C%aT6Sie" ܥZEK#vkIZmCqu^Q>m`%0 # $@ ]#cK`lu2m:'Iڦm:dLvI;iڸnijy ߽O߽74̻OyY؝F뿉s+/" %vҪRE+Or8hA-(S#1:\>:g{&ivCkz nC7?nw'X0Z)_(b(lL6ʊF ,='FOqx#)3K)K We,:Nc'u.sEaj̝OfQqrN\4[^,oH>R3+ߔi8Bj!1IJX$KhОKv5xwfl~[jְ$dmm=f۰,`kdޚUYSe溼{rr_WrwuV/cQg 2!ܟBl8 +.uYW´m*~ifglyM8q IZd\K +:p;X㿬ÞeoFKCr-zǠtågu4QZ=e4X^Cn6zw+[T +{|ݽiXQVX^RToПXK?/܋߃ucq1 "8½_Fm\ +T0~9o4juz۽aPXjߘW}'Y"[{Q^#34ݕd ,{k``y` 8.\ǂDZ;'oup Z5(rS0& ++CrcZU.H+B/HCߑ?wĺRmL_Yp΃sh>@P I `NBqpے jKd;JHQytI#/ihu7%;:9Q%25&DeI{RQv~<ǰ9p:F `}}DI"lE;&%cT2V@{STғ:e"UA)姂LS^v&(7αM&yv ~B9S2ᷰ!{< 9FLDE3<ʟeIEyiJRnK[hgv}=Fl:AI$=EK$yӷ7KO|H$O hq; vؑaNX iYxCD;f,$53e $Xq7B L~t0 ``#Vr=}-`gP9"a""X\;2Cx(QOq澂Mg)$wI\9,6-,FPߡ) 0< l/U^&uh"9 k<0a{J !uı8hֱlc@r73xe|1 hSzu7Zv3\5Wn{C6GG?f?{]P(`D4}R}Lj=ݭwLokdN +S_)xf^!A/o^WQO1/3?Uv1:T:֣wRk'׏pCm,qMM凓 gBb(sJ85TA=&8mpVa^A>afr_*+qq?kyL!pG僕m0iP5kiVԠvR4ky[jR!XݖKj%ϵvUkzuHa\cv6 &[6؝t$jMdS>0_+i;6pZVk٠EjԬvWjܥE!UB^т!vW;ԧFq}pptm[x7r 2Hk~~:FaZ>|ZlxZFy,5%#0RC>t.ׂkU3rGRUc*."=ͻ_{ Yǣzi?vpoAz׎Q65\"2کj !G^<;iuYcCd(- ʫTUGT5MQ"ܨ2Cy|CYBCit$P8;f;bN b.gżmiV}avim&u梿],?@uP8oUөJga3PL79g88;v(Td*[iќ? 'ZŽe96h/$~u&r<$JǗZMUpm(uJ\dSkЕc.pg,,3Ֆ܄AS$k3m8j x=6kGl5~`g4Z>@ur +" + h7dEeE妨t jL66&4I1jk$Dicl{㼊˿9}B˓3+))F-hu"5gi`nM~:4:w5k})lgO3۳LcE8{w}w}hs^N{JhNiZw3MQK ^52,I!ʆ&Y,欐g9H4)3JJpL2uL3q1:z8zrd(7tFd2Ddhx]a+~;ay s̵Z 7cȖ8c4ڙhE9gisF8m +wPө2 u)ԹSC($,+_Sp Y?%+d=4fCa[9ғX$'B)ȤHWF*8 sMTkRJr*@W]+nCE/˧--s=p=0\)哳v*Ey6 {4Xú,B+| p4/dg=O>%vgfn|ffy-4Ħc Ȓ Fnj] w%Nm=HK]Rᆭ¡QÅ_ReSˡR&5Y0; +q4=mjj] +zgN {69'qk0b06ͼao}b<\<]M C6݇^`a#y&ɍ_f%P"ZGKGa[yi +&iD ~tB<ˏ!y# `GYG1zrd`GK3 f KgB~"a4Ġ gfuz%:.ӓn&n]:عn 9;)goژQa1}l~(x{*1Lvqw{ӣ};q_CF&LgZ'*ҧ*чT7qOQ] 6]eüK~zE_;_up/AUW Ȥ*X_hh0R-E|ܚ ZFJ"WؠprWXG7n Wv &NP'?GoO;`5@(c>xZǼtPJ"~+_M[6BBк@?Jϲu.:?@AMQPf šK0RYsقw%ˈ_ɖ;غt +{Z29zw~}ۗ{tE?TDKpf™O|+ݵ?T.^Rk`T6Wx'?RG=:vExr + +0f!mķsTd?S0JaT¨QOmګV:h=Me^k35ӟa^ OR /\baM3/!20r9 `x#ଅQB%GYi#QANn=B=w~H+BNicg&a$g`,Is)Sc=ycomdXZ ovD޿uYO^p0(xa%I8,lr@\ kp*UtΪ*'2E_ou9cv/kyGM`j0iq꽦iy/P)EզTUkO%o*|kTjsg/͝*2wi߇*.2 *JeͿM۸v<?TuT3p.`*jM"U <ȮҠLZE*\U* ޢf9-g9\Kr,ʶ|/ +W!szǴ^ +/WUｻ{ӆ+ͻvw&Gwd7MdC6&ImhhB)BbN BA?# 8((2< u?=s~{4©\ږLVM^ѦR9I4hF+NJq~UC4|Rq4@6`Xtn_lu֖bMTjSOzm,\6viOECJkxZx>Q&`}+]U'Uy#U!,Q76q|>6K_җ\L[[I_ W\a F3F_|)ft1*'fjnk-}hk-6ܻD7}~XQD7VUjkUUfOU]ivUö-Z3ck>`_voqho)/#¼ [~x7ڎ{~mdjгBz]f'hzB6O鱯{!GowqqGwj=f^׬-+y}b]Z~y'6. mw~l@Cg׿DlDcG^14Zߵqk8JQ踶]jwZ$owVu&VX*bFYt֙n$6h͢،Qس(5c_3~Vy]/+wF^ǻf^G{`( $3;?;\Ol T9Tyr tRq *p9ʍ*'VvVek=Z>pI}/ihYߴ 킗fa&P_#6jK]EËU̒3YK9I~i򑈖ꆑ䜮KޡI-`Zp㯵p/@NQvv"HȻ)BF8e 4W T4 @dka7$Q8oBʝNZ:9eK;e9XҼPӼlMi0MKoFG!jlyn9o1! ;1'd&)s}< q!69:c:@OI7?k/K7%AԻvv1kFʇb`bxrpsҙgSyj1}y@Wҭok'lQv/6؍T-Egj1o.X s( A(8ʋ= #Ggq,)4J`w5v5x~m6`d1zB8 +z8N9;MqOi:|9xg~yJHut~TxKa>cRJf`\BW5 {v쵰o%{%0.^<oAP8zXnzҳ0c^`m|9yqtU +x^|RLQK螇[pc%{=z?Ӫ箅%!Lk;~N?~;< id8}ջ& ̣0|7B @/dL&6d,6Y!8I DDTP(TT˩VOjTkuhW[պ)GSlx/_f{}Cw6L_Bo:Iw5]kt;B%E:癰Y~>)?SJg?> wNJȪ'թ۽q@/ q8f7`r{3g1-  F5ch 0ǘ8I7໕S{+f.cXK&:Nm}WGmgx)r~daN jSn$5|k;#FFl%{c63OVst}űv戵q3W o XNp4%Y85O㽕Hv"f3u)rb-|-cܜI(;BpG!J>=(W60LxvU{=iөί`"VÙUZmT8U7@ǵ|W1bg:5઻rh?Uh7ϗr׎mRՌHWjnN6!>;s+8UOܨؼY?oƒjyaEhY1&52wg6z.Rmfʂ4=?]S +4Ԛ +N邅MZ]㋺[<G4S4B-Meh(n#_rL}iOЗzpsۉkf=LdyZdO/T,L+2*5QhFevj4W#`V\ަޜ+ԓ_ݹ*uWGuf2k)}v;) ZtתOY[j*V7jUz6o[ES*rWkU>j/Z޿Xl.epԐ(NBQJbA۪\X Y^*_uˍ[hUtX>6b+]es[wU;d|Gfaꓶ['{dE ]'[-Ɵ*"yep5҆6c4XE+uqioko26m4oxe՟0OZ7 g ~ +4QI*RW$Ӛ*wk\v9*x@@X6dŌF^6#mv۾#l}Y-' +[aMZ+Q7̶Vz.JZZz9r+C|ٻUUPrCM PfhL hI +*.t=gMt[3]6 n5w?%Ҿ$)'CaÕZ+5ܮpJւ—i^xkn߃J{Zs{_Wb?4S] {g nue+]*F6P) -+9R"J(!Ҝy.*4?yA8 4AA@Q~98"P+xIs\d6Ҕ5a붩զn;n5ήl^w00||}U2_% 20ElEB ZFwj{%|uU++dwb+S+lҨ2 ss9ɐ;"'uemX1rf&Eg=xW3Y,CM7T +F&*ПUspp-bY8p05$eTd5BW`D$-Y<|@ȡa8ukż !V&Y@+B t;w,,0-F#&&r̒2`okq]|ԤAk-䢥 lWu.h'^$RPS# 21K:3,R41 ,yrZXc~lNMIr;h_sDz6u'jȆ{&.'s4Zw,Amp@;XӸpGlcA]Ǐ]c7Erwax7d>v98fQ5uvT^ɀ; &΁Vf^ZiPlk& h3VVB< A|7hCM.D~@=OUEmiԀkw];|..>G.=/.qb~_ѫ'M OӐڊÓe9uqg=rE0@>{ܜ|r9o@=nr9ȢzK_&ٗ }!;9QqInrw-~BXK -@!Vs 0FH7XX?ffAxAMз)#'D G@%ktėhhr/h;(?(>CGFdP>a?A}D@[}H򮓬h +:װ.^?V_i@U4|fO>68~\Ǐqu.{z[PI:s7@_?θ ;[8bd<.;ˋ~Ǐs(& PM|\F!ScX{R}?~n]Ww +$:Tgr.ĶVtb۵nrlBk~36> +$љ/\-hp +G,Ӱ?kv!mv`۵kqJ7^jMeNpW7tW^wq\!pE8xi1RVy〣J | +RNuRδD;qf5ȵ5r6l9[9N8 +! 424aܣT dSg֨k +))r=?W^u]۸nscYXkIjT {ʽcU Ol>3U2dphV(o" [l5UY~2.hupO|:ljZ|!0dQSU4S7"U9#f+{d,R(2G-TF22)ԩ}J3U鼦>Trxnb FVV4A%;y^ +/%4\;:L٣;&Fs+sLfYcJ VJPSRM3Ue%Ӕk)Ac$p"YyA5p_ +KCf_eM45tD0ORjHRBR5}\Bs5-ԦJ%5hUq͚lyA,GXY#&*kĄ>4 }lgꄿ|9"0"K6dl-#f T%LI(M Vbx'+>"݈?Ϙ<ؘYa<YoD2ڍQ{ Q/OG1Qֈ=b3\I.×LJjROS&%X͊FhuuE}^Q5"D""XY@E++ + +"ZQ FMR[hjNLFMMQ&ĤL8Q;m6f[XN9>w{ҕe)b#Ti$֘وKm&4bNIhӧxonLԀJPvm>oV̔L RZJ(%d2h4SsEF\#6mdDwQ雌]FDczI]ԴOnc$Ӄ4q# A9(uxm?%[&d QBFfd)6#Y1Eeڌ̹FDf1Zc[5ڮ0kB;5պ_!jJg|) +|clC4'B UJž˚n*fdEeOSdvgnKW-K6Jbs)ض\sVќ.$shЄ75~G +Jw2`dKf[bz9_?US#5`Yڭ +iX 5^q)x\^5:朓_uλܿj .72`!|oIsع#Bq +r+Xs$ic6v#Ǒfpn"D<6k??6[ ߂\l 3H"iZ1ڣи; #(pp'Cu"4 MQ(yWh=߅k)qVhGs@HCA#_8*\&.Abȸ8. +¨ ]jd5"S`B(-dc-A8=pՒ +0x39pʥNd`5F2jkѹu\ln^A@דzpFLrn\[Z-bl)Z[ˋ@9:@>Y4bN@Eo /ci`hro$+E=GЮfSlE/Wї-_h9|5_@mRjJ +oWOYYڰ QZGD/؀.k EQq8v=c'=IOm mc믵:W-&pm!&zoo.XY@.BNJ?ðh=powXJ\avG_`Oq17=C |3{E6Z+t-hZ!cӿ!xC+Th_RK$:?EDg x7VGg~@K|z{-JtYz ur]& +<~?Yx?^y_~<;:ŧ'>7 :&W<vQ0u9/A8 y5`ctt >K`jQ}cXѢwP2Wr\\خ25آP;Waq;K=C|.d0#LV`a.lboCVLM6N7OvIYc7tͷ.1]#؏ƾ k9Q.ဣ va@:u^7A6} p=Q;4G1N#O⺘ ,* G:_J/¶[j"-tZn!9Ď'\8M2PR(7*WYu-QƴڦuGVRi+lL&M>^KP99wHp-1,Rt'XX,nh}C(̂2?N 'C| mR=y(- Sqa + Sdo3+fL9E.nQV e/P}Bo`ViJw\tS)E_(HZb784; AAi̥Iq+ˑ#ê̲Re9^斡ܫ~SrMGNإ}/? s\S3%> +[8G}`r4Z>W{dwU9+#dJPFu YJu+Ydg.%:ە֌)fk)ҹG# +>𪫊"+Կ3 !xz͠T6[>8WXMoHV+S.b]6ŸUEnzL!. 5 Q)~J 3 肫 4PZmx/l;D QLSǠpOB 4Sxn|^3b} @ks jgT6YnjҰImHvrx9} >(G>~zx^LSx1B0({\yuTUj?;XJX7ZOg?P/~̤q~qz1(ݘ1|ypS=FpRo b›e2^ Yz1^ xØ!fb:R”ͺD l=-k{͠PsKj x%\,)Tc.O/rG(F{\a(2 x&1j>uځT]B,OxYZ1"8MMcuXBKc5y =N _z,T.L3썱Gs@+)0aN  +XI\09ֳu4rɯ{g* Jrm͢U "93&, rXJB +8%>7"6Gs 3۸w0c{u'IQ;)[J[X4xk*fb 1˾¹![w;)`VMO^fe]wxh^b/|_ft߾~ֺnpt~6Xc ߳A0/(4'AÈWqc,Qzq^Ϊ.۴^Jd|Ck|g\XNCA@H,0St9˺ca>0`瘋uBryR7{|<Ǿs*~ os2{ul\cߠ[Y787%:>揲3ư˳߇[ +6P:'{2>5.o%{d..ip[2`Vl;v+?YP(;* [eM +: al73[r]]v끏~'+˶('t?6Q*qE)ש M2sj}٪sT9}[Uf{i=ZfVu ?^cq*q{H&Vcx\JͷGz*|ST^ +?xivx5ӖZ9Jl;؀쇱ߡScqOs%K:+A9@U KTے>ۯV 5^cb88ʱ_up4~UX2~,E%Iڋ{jlα#fYYv>_[9s)Y#28Z-aicWtπ5Iγ"K#|;g U?ۍ?[kp2#G1F?ȸD]PU +5i')>&q4("qg PDr'Otqi'9J& fF +k\Up.\A"puA<#cVbdbu;*tv}¹1_f<fl2k҈ѬaCveϪSA}B1v(fUW.u&Ԟ3Hβr+{^ܛj}@ٿWw _%}\>x8?繁\7ϪXC]y.u{՞P$?…q +/ZVKq/[KSVqͧ*u$KA'UIsXŞ27\S +%See7V{26+724UƧ: +ElO#GqA=|qΈ\+$P,sCAr ڣఌe*VNV p}5B6?LIOb-h^s=pE2E*dؔ%(F1Ƌk(ste`"" ma4oymyxppuў!OT0)0a$FQHVzx1c Mcq*ǘ:IBX=q[cB O|v!vSKIG?4q7N@q^@ 34H)E TGN3A|@򽙫j솿ExA!anM`-Vw8@ĎQcQD(bi26OBCH I$*Paւt1kuv[w٫Skwukmf۵ǹiNn~vk[ݭwfؙ&o>|`|Pv:yyK!2 "L,KQMTy+sh?>dnL˿9fE=]T;ټ7ٸl9t)t opBp? }#-Pf-q]uY ;Lo.*~8g4~9xB9I~.e6A;ӣX<YO8>WO2gѺgibq +e}TDȇ?WK4410" udzXm?oShۜi +#\[rBʱv`۽1:V`{ (-VM:?Y7ҿI)LB5 +^J'T%uc7@)4w`YhQ^{viP;Vǣ4hG7f) '{*ph6-=2Nlz@-hv6 +{OZaaoIr(l}Y."]:A\q}2A̞ɖl+ڞiصaץm `;Ǝ'M%c{&e#}whXC5EM_ w),_y y1/Ou¿ixW22r,}`!~D9j21PhWRQ)@QjZTm< eD UQUf}BN!9_(f}?<[5$n(4?C\YT!6l!U4mPb1.cZv8gesqPk2";'tum8&[DYdC"t|׀?!O59 r,SyGβZ9#*-M%!Y+VRqM2gTޥʯxYFyJƲkz.FNz Znx@(w娴^鐭R֪YeTY(7B'or|)˩;WqJW*f4Q~flZ}?OV2UTPS~MPy5Q ` Cy-Cb,FNPi3kZ;\ZM 2'@ h>jx{;ϊkd +d dA! p0Cףˆ0&s1֝'|Ob{ Idbw1M\A-f<YqE<iIIbp0ލH Ar^4MDG2KG"Ѐެ#v'FF {/psļ VaZh.1|񶳩DqUc|h 8!ۘby8DiWV8r]Jq ,1Ui'h4.|3&zXFz؏!}7/ 9A>I8ư?ںhMm .=;,/CCH4b1H,$q%y)~$"ɤ7`b蟣 CuM1c} «})KxIR$XF>LSXQb1FyqX96f2F= CCxc-g}m7\]MW?I;qۉ\'!HJ +)6\` ZXml-viٴ1RvN h?mզMHo* ="<'1ϡ % ^gťMЦ.vXs&sG.rE]8 ="!Cl-ve]:ܞJ9ī VŻ3N@`Ʌc~Ǐ ÙlE{ctz겛F${)|0gr쥭GZhV%Ԃ ҥ~cs-Vzupbt l~EY5DMl.ρ ͩm."1;WS?ǹ(>cAj?vse5]YMzUkB@-q8D.XXSq|[3vZK!6&99̋"`VM[O`qk:wQqn7׸sX2xYJ0 '3q{gs?or?'M]w ~bd ,Rq 'GPBEI6JN^!ofenz%|^RY'jĻ׈bJ +4PRb . +Up-ЯizdyZ>'w?_hl`W]=û4ʯhu3OIUQWH؛$ r5aq_' oum;.{/wug|3_cc4c?~Q=GiM4h :~Z|C|D~W84$ςgɸEo'Sholϳѿ{ ˳(0MAϼD@>'959̯s_)"yFBvt)3|sT-p8ҳɲ}.v_*=sیQp+A٬F&8i1211N4%&GSSv:s3JQSbnEL&Q%I8 j9?Ïqnڅ7*+dq;4"@5OuF8TOmpL>8sM5NmAA.c'uK+\d۹PFQZ\P̯6{Rρg8`ώ=7' Jlϖ/PИ~s.LtE?Wj$C.W33apQ*5{Ŋ=Avll:&8}+6a.ɞ<555V5A](ra8bpᨀʬ^v[dj>*(Ut\yG#ш-\URRZ[`ƾ V)7'Fᩀ{ ̇c1]WIQͦjb0jo|'kp]XoYZgI'w6pv ڸ[9<: . LxWx)_3MZyM#T^!ӧiP(?VAVu++KU󹖕J))Z$aJ.qS\yRLa)k#xZH +80&MxSTԷer3y2B}w@:W콠y+{9W?v2$jIDK撰敐|LZZkmSܶ>qHN~ɶ8iqZnHl#;[ +؂tꔄsEBN4 şo[2,wffV>GrZheXgD˚4;eܔĿv#Q#@5(%X^__3r +; +'|7+`GE2imb*"$3JEК14EB1c7B喊C ܒGoB%Y\YfIEL1-Mgˢ ء˘n mG"FJP7뎬DG^M)s!< g|g%Ts C4@-gpTXUUUR5QƫFT#`j}B%z%Jw>}$ye)v{w%(UFuJEBX Aj-*Ԋt\GEm; aDe2Bޗ3{>bdEQφOC|njIVú8@p ȇT0Ei qƸxnit,18('mͰ> ~|>q5f5ll^ 3x ^A=Cl8l5cNi46@PO-Xp.I#~:} 9We&KLyroǎ8ug|KWrcb]OHrOĒPYkFW?]^2XqQZ!% [~,{Ơ/ѝ_Z6çSB팛 ߵd{.ψ Jwaݩ}EMDœOaW3- ҶxSD't#RRPĭ7O n+*F)j-$j1[omD8oQUqCC[^G9| VFU{V?pxWC*`e#ےсb~p̜_AMyAvmtjx*" +(UTKʡr ձ]u+'$@D!$ $! %vvf 3<೸{ߔi3hg7YG!€! +l/vyfchPIcs2W3ܽx l?`$*CtQ7B3 kK[Z3l } 3L==ztR%\p?';K;޴ 0m3zF@cJ/\5`w;AFjoz7[ < =x0Hb㮙DazNB?gu .a0@ K8e^}-Vq\+N +|9 wʅG; kX4OhӼ]&n{](sY8qEͣfq(OiI")k +KҢ&bxp:˪IїMH\75<:6?tsAB| Kؗǵjz2z]ڕѻG8Kܨiuߔ,qӷD*i-F +:o{nq{opJP{&F[R|֣'ؚ̙t/{#pr][8J!9BR)#EQL[(%9܈ONʿѣO7sTÁkqȡ60_B-lRg(ҁ+M !n]ukO>uᙶ# VKMz{c7o T fE^ǥt.v;CɈ0P8(pݿvR?z_`}~3g^Uϴ75^w?[3p6?>?>$(>?pϰZ z}@Y )T\1ט.j}l*Ri5%IM~pז +W6_ԍI̾4`ik*V4M4$%3pm)]f[ ,fسvehzu鲼)`D,JJb$){& N:4 csg<P`1Rrw631=6^,̣_Θ纪y7G(kqYi\FJ|7Ӟ> O yZCɟ-;+u{#g#xzvU})i%*Y+ɜ*$;uQAEFsQi&%/GεA1B(NYީJV.-7N:~2ؽCە/&?x-f{(-]r8%ȖAYP,R.;%.;NO.5ggqNin;ΎKTP! "r)G@@Hr\ÙH$hp)?ݙ#}}{>{}&=+];_a]@L> K?A*/LA$}.%lݬ!T>Sȋ^y9/^9/Ręd9j˜-v#xm dFXQPP(j3=n~r|e|>q {kS(u!W@P:Ն;4wE|p/>t :!fIM^vωq/ +YOU7&~`  P(rp,oaq^K_m:ld4)c:@Oʊ %e}TB0AU&SLZtݘ[7rWꓹrZxMb2W;7s%1 L``Da6z-zER}MhGG$CfI;EXd#ψ +[%hdn?߮S_oF%Ěb’Bb$t`;ES$]ξAiםa쎩QzkZ2CgTI%%J ƂTOc$&v/:E;g&!l1j.}C+VznCTyH,фHvN`;f܄haO6?\+ב54¢4LSxTǼijP%x-'w#2y2(X.Av QOPmn5?K</=ړL-T%2 8(iu%Nq]S9X+7RЛ/M wۺJ!>CS +ĥ1Yon#R!/քVTQLU( R(\iN/{i#_ђ=:[[;یc]:j?8iqc/uj}ik_;NgjtD*CB$}_ a B$EY\n={7^C*3taݷu=XBw.;},SV ֻ=~iOnl>A[Œ/U{7cX(?'N3HRe7AF<v' 'v\G'kQס};)8:J\*xayr4͟mN=GKpx3c?;ȉs"Hn5iM Cܯֿ]cy N"?p['zYt"iBW] a.oU/)ut^&#W`ahn2>DL O9|x|MG=끇_98~ GgĬD]鲐ؠK>KK.+BaJ1s>~:WrPHX"9۴'3E7  mQ,vCH\$s$NvfgiDkJFLqdDzU)u5{kfV{ 8 ǔmWE7X).~zk% +D']ԶYA}+'pXu@t-0E "a̴BK['qNy4Āk_I"KIcjHh$ +Js-J(w+MM\joaZM\K +k3hq'@ߋw_hAF\Mߑ=GʯSܐ9)yfEcOu휢y&kQZSC, [ZDn/mQ] ʤ;NUz'k=T>n$-.V}<Z{?1A Ґ-Eh0fWDSe4uEy4"R̙ +Y2iHv)MuT[SͭA4"?ײmEpҋ{kQ Ivs"0?G5^۞(lJk!76Rfv͝D >}_ +j^P`fAY8f"YjQg+ +%ΆGUvKdyqm,QJ,S)߽^1~ :J'5ꇜMsy,7(mA컦Di(U1c%1k@wwnD_~ $'ٙ#[ޞk=|8t9JX>_tILR!q$AB@ A 5B A4kseN8vmgg;юn[3WS/- +c;Aubcf=賓)[YC7s)U=ė]//{F5.o}xYEyٝi[;f lWv?{/l.vz1ճr3tܹ7JgåUϷ5ri9M/`_|~,xyI|{gW;B$Q%Xj޷K7[)ya)ElDlbk\ÄRɋ>[W=FQ%^%"KQb0{{#?mY:'5X p5N&x*mՄ縘r]L.8iE k0g`MjY;5%ÇșL8gu&[K'ˆNE=CX8p>}Ӽiމueu8iQ̣_aZ[)aKy:쳎oυAG +r#7=(1IӪmPa"3ʕqqiQ:6a1Rؾ- _a[73G=/q/{8s\eIXt\PDY(& pd[.>'u1<0gFR__R3+3eEr E)efr,n$#/D2"Cp6(gyA|+ 7!p A o8A}; X;Hs$@4I)q9!ZD+Jt: ]k+MEJRi +՚()jcxhbѢdS< d_C.2 C2nE,bZWb8p&)2Ld|Gm$ꌁEu QZSg ֪i ꑰf`N٬ "C2!CAF:!\x%/f'Q3 43Z2$Q=_5LWO('ZA;٤j>nvZl\d!CA C.a<%.3X8HMGG u/&yMEM!M4U(S8US0>͂6 y9𐁋 | H_/b- H \r ;r.7Fk&iiMCHQ&i S놢4XNݏkѡ5 r7 [A |dAkPD"CWt'9C01X嶍ӊ&Huk_>Aږjkfڴ( K6 QْTOѫQ +,Y) "C;8A5 &M^p +gBE&A4?R0^֥KuiRe](9J*{T*( ! +A;xG3lƛ\C\%/*nvʃDq*M+g{lI-Hvɺ, xP Pwn5;mUu+'o:R|wLN/Ҵ:iiUUUE^![SȖv,ࣟ7P P (k>+j"uQ{3b'a9m4T^ʬǶWrS ߩdV +2EOU_OMx`]jvjzr}p+'D@%!6rrJ9Í 0@@A仿죍@2iVRE!盝6 EW@TYB]o x4S g^}->-am9y1D^4X۩%Ci)w?4I(1օ*;8 NfWR{Μ P;:uY5OD bWP4Q<xfZ2]!ڐ$^TcgFB|C(iWNkj~ %67P`]`dEGT:S:Y:Ƚ[&Gr@6H.~7ٚ[m溝dDWxϾ7WĴIH4tvgsx˿-ϯSXVU^R_GeW 6NBPezp7lxkߜo"!aZ"̞Jݛ{^xI-ogV= |X|o!EB m +цݣ[VY[|jyQ6l}nTfa;/;\oP8q%/#&HaJC@?'libK౿UĿA]Yv"6OjB䭦_KN\7mWXWq] RGz( %-d;T!a=a  +yр Ҿ^͟^ g'¯w ޴:\CqkFJ(U+v˱Yš\9U2edTBV5mX~~-ޅ#v$0b) , At6z>֟ V[&,- eeg2£,-wޣM"H h @۰CiM#$8f 'm u xs! r,(`fv(G7} H*ut!#R;do#IcW4h|_} _O  3&eua @m2邙X_6/EP ; F}hDj AzB \|I O_sMPff*BTQp/SI\#5g(Irjg;Zo֣']OVφ4@b556 $ LjNzOF)vfڐ$e)T]ԜJ\r1OʘMyġ =6pAc KgL Out%JLy9+< +HBV(sV(-9r<ƫ+{ʧ7T%Gn C{!mC8fC1LVGoWst29WL)* z½5GG Yo`ٛ;כ; q{v !mԻ\S+q!n^`&VQejBr@&@ȩkEzhё?̟w^ v@<6pц+`jgH!❴)rZ\5Mo4;xDQQw.juUkP<@AGr  B prB"$!X֣2Ңɇ̵\r-R%F%q3jb?0wg?dp;l 6`C׀zT_4@@CE,B{qr[,hZ&1_uS·CakC|zw"l |A7 +Ԡ@5& P#eٸKub\eBLp!S gu3ƲM]A)gP1 +5h ?$@q>jΟ  dP@)}GLbZ2 9 ¹ƞ8~\Z47rD\COArZ6Æ +@ U߁g@7@+&0oiҌ<<4F$#HSHƳs^b뤚| *dp=:@%l {@Wq`l4/Ǿ|SܘHJ.e=—dR{ogBVʕZHVA"-/ʭP (69;VwWШ5~d+^lBG"aN{eydWZZ%/RjaZŇk>e`P A3DzaP(<|E; AR$7kMU|])ATI EVPJ-k#4-Z ;[@ TxzB$a%i9YL3YBCaǎ <D+(%sJ "C+Qnhk"BF֗4 4Ppۺ42jQ }~5.'t_Xnby&:YjdtRLnA:zRK'nG6Tr. p]/B|f)Cd}}XMeLA\˿r%uE$ +y@i1P#rT.3rC Y ` 6aC=`ݞG 8D-?7] nE nIZG+?[Lmו\ ci"tw\'X T*mzhpp]ڐx^S{?1kB;O +>{/fVpjTC稒XtQiW&ƮJX2F Ff̥ro`>uzE#aV'N~ 2E'C?^.#íJM/OSHj}?GM)tmjϮtt-6 _SzX{~bGFs{'ml7y)ʿyP,w*(q0Ӏʍo8r,KK#~Eq}:i7I[ lC[A]nMqfK)'w3ܝ˗!_`<Kş?_5ޅ}&(G>nE=b'LۦAaz@tLG4L4& ~=慦.dj!Mh܂][p͒q7_u\[8w2ᖜvX;9|ދ2W8AF3г \~5zLG *zAAA/*7m's"+_Tn_7p>Nf2p24efĿ;}s(dك^.~P%仔W\.%"W䫎M[b!OX b6n6ƿ?}-p5pr!'O<8Nc;z* ,ř'#A tDD>iĒO n?V`k<Ο aL81p 6NܸTN.o9m{#ߚc;-񉞖DaYm .&Q93|nK3x]"m +H C` 6a[ý@ (x3tC0+"^ԇq . {Q;NaYV[x||X)˶~7V{:/w8a+\vm-:ÏAMS._%H?#3a#1+ 8,E!/VxX lކU[tv'n8JY e v[ ?`\>grDnA,yа.By 3?_jC +h&;@E^v[> {H2i1kTb CƬ>ðg3HC? ,",A`! .U@fT%O]R"Wi6)ކ (^_Dݗ?FѬH|_ mlj"2^@`e ,Q4z9Cc]Q[&!hZ$ BҐD,e<ܑ+(p"+@DBg5ӴӴJfs߇n95ehͶD$/ZioqD}J@b>pK-EЬ!ES©悩 +ӯݗKԭ1PÜ; iȘ?l' A0J;Ajf +5S e$h2x2xR<vhquTˤc-7\8@{{/z"ҐF,hz)ۡ" bzdIq(#d"\7V[:֪`׽)y+۴a`Pp78,dA.8azkCdԋ:ǂd=ؔ4&u'4v%71^L1Oem=F(1%ւ#(Hd: +n_ҧ-8ؚ'3+[mEJegA'UWN)o-Sv*ԤAE䤡K蝾B۲ck~;As|pt9vu GŠq!OZ.د>ԩ՜(\(T_<]t0r6 mVWH d?s%-mv?Cw|tu\h`_{TܕQ^v|y</զ{Ku9ݜ"I*[f`ac3cd86;E"K bZJ)>z߹Ox|?;7JoJݼ)ycSM)RϪZi6LQ`fRcTgoⴟEw~ ͒:d#ԊʨEl-vC\ͺ2Ml~KsvĜSenH<ޘZ ҩT!je6 l~?B;O;|L:^l=+ +jh^S}"lKɱCq œ'=tClޙqΪk !jH1{&fp}/ܧvd̼u*ϣ09i!M=۳"%DL RևU5W;QZ*l[.*_;d"P3a^f6u+uq_b,>sד]W\qI*nLm ٢6*euƑ5AM kj:kmGE!KO;%ck z.ٌ|dOXN@^pC~Ypa.E[؁1miҎ2EZ._*"b6Ȧ?F衆E^/zhszl+ǢK3oݏ}B%uD^](vnJ~aQ@Wހ{WoJطzIZ6تP4Etޝ2!]w ޙ 54AwOע\WMަ59+{;y۶ .ߙ/ro.mC;A Xr>Ott,,v0;4=;:{7UV ~nO&}M:4T]A>!3VZi#W"mD/ i#Nf#.y#+RGV' B"C/Oޛy[>ʶp?myFΗɜ-I_=Wmw WOȕQiHǕڸ6湰O=;*8H([}E37oǷ!zxpjs`sP,s> %!eإKj0Y `i+,G3K+a'ch2r7x)YW2d \IGb6]"JL Z! iMHcBJ0Aod&΍<+%Vc#>}1~L2&xV8fb̵a,L,fѱ9pL=<.K \LlVHhLHޥ?"$D/П㦬_gadʁLh0]3[, l/rGkpi8N d9թ6B$!yO 2@t%_@ AlLp#&ϱOsa/֘3 +Y|!-X%fgPa, s[3ZA>v BLd'^V:/`1X`0@O -W2h +AL钃OG=_|^> (g6p/ o! TkՐ"mjf_ +0`=|ث'3e{>ـ?/`k5TjAH[!Upku*PFQCQG +WU`>TQĈד^@@⥨_ѳr@#c0#CHfObl-!n=;"_j$B{C$QpE9 h0Q`\ۃGk@9 ! >D8GNDp:k$gH|}q028Ydoyaky>t<1G 2zNzN~f FG@s#$_7@8sp . 1ؿ/0ho3xIYo|Y.虿61_u0~ g,NgOh9`'fu?vݎ6 ,!ar26ž/XӸ ţ  q_K?Vs_],̇#Ƣcp;яyޝOklng຺@AHp[z@Ԉ_0)/P|;i(c6T8L1QʛFbfx}q2:0m әәә?R,-!i-Įwڽ Ady|N}Uz"3 @D'bԇ1t9ʄQC7}ž)a{¤%q"1i"n">y"'@gl368B vp}->  MQpQ9m +Agvņ8sM!nÎq1I~,RX.uLR:n,, 0Wց3HvyM}Eǜ$o:+5ML8D~mlVb9Vڈ#<"O ÅUFaiqDZN)0 x{[ L ڵ +mmk(]+C=" xm*%F*Wz]\kSR5^4( ť!Y e 8ΟANG(:mˊ;7;2Y1T +$ +q\2YXMV +jr|Et(K}J9_)+hR`:(7HK- 3HYxWd*(96-jOo}9?Vޫ n%zajfUPThB^]hU1+$r1,ѧʥ+rB +k Pbʯ_W[ssuNy~AxGia)z _."*1_*UvSݩ峻*nS.` }*Sll (Cf(rX~pKQSkgmk[w]]& +]Đ*e'$ :t C5)SKuiijSjl Yr7Yr?tl^\l8wf >(>:X'pKRKR6>+ԣ jjb:!P$& *.)@36Aom/kX>o<`1ݾoký[r|ՍHU$.6ŋh "VD+ҪR-LW,.Vu]Ln:>4/1e pu[rumfconuٲ;7ðHJ__SᔅUᗪamRdESFTхh˭ JWѯE7;!ƻ!כc@#(7g=lk}o t4W*ŏWg[}w+MFKBnCnrzp>3#%F #u#jg6 ʝEbgv`DW>VP)Oo(KGIbTKoPP_ +Nӄ2!?@vѪQq&йJňGU"6&4آހ=*:>U"7ѸRuR73k&` } beTuqC}F,:QHgG ; fv(Y!Ģa3 .}ws N%PIȶ>C0{^bx.KI d/8tBXx$ֆ#&b  dE@S +Fܥor4tP݄T 7=A)Yߍ aZ`*A -CJR! XK.w x!~`iH`LWB2leb0J[ Ȱ 1VJ /`")wL26=15,r .BzhƄ@WDS&XوQ@J~JrҨ&%. +p2pR yS2\jDO^BXJTO5` 5`Sթ{@䗪W ҙ9O(z&U]ꠠ:h[=bfiLӐ#&Nẽz>|HC#HN_i"f0{L+<FyP.[ !Auǭ(Bi% MH{4! &4i)0";$N3٨|خ3r i-̤_Lg}o}-1ft(G1ӡr涩G,-kv4m`7 Ɔ!/)$eP*0AXeѐ`Rp,Bx2,\m$m8iCv4lu? ΢\@\|ABuQ+%1PFFq:V>&ѬENWOJJN;_ /P.Svvk u/Z C%LCM9Ce/˯TB(5oa'ռ +qdJ2k6 im%*)wYޥ>UT{S\ڡ(m38 V|ovT^ k_ry0z/f7rjc{ L֊vEبX ߴ+kumojlګnX7]|WM~_}5g\&0.Bbl]:Y!SQ#;3m2MzYg-=yK=S}O9\xgjoZ6Y[j^?upc0CѩӢm"$%o5n,1ff`̂8"%D!u8Y,u[=N-|DƼLo}@xQGxqu 0JK n[!iLߧaΕ<_]><3u0NP\fod16^ױnEu:Y7cẌ́ꄅ̪ʄEj`44Dmփ);ta>]kb]hvxQe10c&iX6-V[m&TsZr5y^U<4Sqg!P6´:W +)^v܁y#0?;:NLj0kĜZb1 +:_E_&=䫒 +Di\9B4[]i=خ shC_ˊ?/;UsL== +LJg$gPiٕdv*Y T˄ +rrS()iAaL8e6_DCWcHdY۴`nɡuf^U4>iG(2OH jv)!Rsb1XR\:P(/Qa^ꔈ:-Sg + H~zH6Ԇ(إM~ґuҝ4V} += +[4b8&*V%4Q~:[KʳJ9^/gߑgeY )M{TȡM4P gM(ީ8\e~^g5Uoe0|i__egEs"4F*J8<ɐ3 +:SLc(RY] +*AYc1!gLJ2e?*\ Gam-PIgͯsM4osWG Q1W@гidmcFQ3F7\L6^j] TG9cӔ 9%)$TZP"SC- IhB?!NJ54!Yy((+ցh0ގ^S6[:lu0Y]2ѨobM0`Pui} TçJR{aq=Ю4[Towçzw ͻO ,lB&Bj y(E0@-d~? +4MAbDW࡝ gܩQ7/\h$x} +sG.IOtm $eWջ`*PKt9#uk {5+PUh^hgO#\|f=}fxhh'lۼ$Ym;a /Cf>F:}vHp}u S)~o?Pݚ·zv2?vFv_{ +^#;D@=;h@䓞Zg#4gFa#ʑs3gS>+֎+g8{ _ot ~TxZhߤ\|u9mU3rkmuCI +ł[0p> &>qhnm@8ANfC(w0*{x0= !>YHw35 TcixV'C=-ܼ! nwx +0gsVtwXWl!HHVH; P#K{:lźXJkUzjjE(T(twȃ\@G4cq?p]N܃?R^rST( 57Z R'QLak[:hp^ Og\\pu"WtW+X-&IҨk6iB&`"C$.ttr%eû2^\xq# s8..npAυ(GC0A8!`O t$\Me e`ـEs(D&Ⱥe<m |#Azoxa 5r!|&/G@ڙ9[kX`*ɺk#,}!D"l$?D$bZ!tR0M8D>"Mmm3hRHmpCy"b])^2j̰I>rJC'.'y?GM?z)z'̊^gſg܍F&#<+SDYBVH;#>3ɂAx:4vZ:ko-Vcᨡ҇1eҙe4T_F4FRc(LDPY1%K(%c"[auˆ1=q8jGx s\ދ=O7?-)qZq-i:JfӅt1^io<7S]'"ҤܑKin@L?N,U4vIܗqGdeWߕ7a@~'a΋fd#Ylj⛔w6$vꗤN.խ۪nXN}qfHՁȵC>w2Tk:*f:P.xZ Gӫ,HIȼIњۭؒw=eO#yWR]Nλ(MiջΌcGF H$I42FW~Xx!b>̡oMꄐ;ʚ.ecEe{yՎ%g2N^}2WݙR},{`HܑҽĞ&HAܒE0ABZ-@u4u"޵2͚TᵕY]E9gs+JNfYy"x抯sT9Vq$Bš[_彨؛?\];5A6̩ +[anڃ7xer-ұ%.Z6#Ly~VgIhaum5 +v|YpvO݅ݵEn/Z4XhzSPƢ5\[Ɇz(0Xj-4XΛjfVV߶1 lh]nI?Wu8\Y\jzꎒ[궕RrnSɕ u65z`Uk@&P )(֟UK|_s8p׺dp{;ړ'[ҥGW*Z^]q}ٮֲ-eW66kh*{V?4꽍=C,32YN0Dj0h>&k&)JVEQ='-R.%EzNyf^|//߬Ҭ)$MvUL%HhCX2bB}bt]8̮p51[rRHTmr}wDτ۹˶s_MMJ1rr \yXLVuܯ#m6[\ؿuJԵ;zmkm|xGrJmY:WXUXϫTꪳy-znVe=qs˳sd(h e)_~< u­ΥW]9g~@Q"vLLQ<[̭kuiڤ5IO+76 I49L|yHy]hִGtл[Z#qBklL(OȯI/e j˄u kbW8'JH(% +U$Dž`础FX%OPaUvI uc!wQ1OC{;v8!VДmLg-kyYYyTո0Z4.䔏ǖJdi%%0Qx­Tҫ ?aHWn?ܳz ⎘hޡ-܄}Ȧ҈}E͗ac=E5őUa,P+4S:2 +f2ulܛN׃®EƮjFkk%h.η 8|{?&, T 3 pAݤܑݏiP3+%P,~l6f7:ڵCBs"|Gx{?n |t6hff#<ͮd`d7 ;8K1hg4(ґb(rl4^M:ZM:LxLxNFLu6Uj=Vʩ+i$&w3'srſ)@ּ3FJi3⦭ §m+l]Vx}*x.+>pti^_9}}`O$. @0@@'9JW5oJoa,cY묽ʿ\bEm0m<[K\fZ` ֊_%F2K2t"G/6)MM@%(TU FͅkPWI5GKc[dJ3K`ПH3:& n(&M>qs?2+@2`sW_A*eס7.X +QSZd d2ZYOtu1HG9ښD Ա&MU<@2X{ISQoH!Ⱥ#(8|;-F%UQC55RsIqt^JH94ܤ&DE$IIK9v!;,GAPb!dl*(U5PUM-D5E4R!CMmTUʀ $Ay&hZfKuA <  L` QODL4h"ژhxFE&0!Mߙ#9!d 92Քњ@7DdZ ^M 4M9fhШk %DnK-ЬO1noYBYhy_+d)$;訣&ZѵЊl}d2B?Q]L$\BSN_7lfs33cٴflH.S%n)NW!%J?~ޟxޏ lR:`VX7 0Gp8ڃk{}ܜݜlN< , +j%cP<9]bv`;#Ob~uǫty?<02pF V J3pZXq +_D+ ۀ[$\.9_ݎaz\g/n|!t1<14N1"d <ȦK@P` THaxd10G"r/S-Ϟ{I 䋄 qgn#aoxIT ] [!$eff:y=gL/$OҤw{J5y̧Nz{׈_kCO=_y>&?ʽ5k>&F@&ja56J`x;"> <3'PR_6P_<yF;Fyr8:Q1Ꝑi4p&@56)/[ˍ ~$l<4fMeǒ_d0$Ahm཰aûn =菈A"GЧCkDe;'5?1D\R~ԇu_vn+Fu'lhߝH&=;ȂQ W"~gtF\fE__Eœba~><;<ĞcB 6XL2ӃtE қʴ5t^6$!z" +g $ +2.0)鍩bg5αvzbXgb{XX'dwpp:fvkX!Ɔ6Ѓԥ ]MvbވoL?@Iӕ4Ť GpSpS=={8{(2ww<#q7kM%} @X1Y:39tޫ*{TH\r+M<">OeMByN^%';(=359eR=#S)N64ŋ!y1:0ӞR~yg%c*ӫ{S<+#%fPd vm~]zM$8(.5 E5㢪镩4MT 5҆X8.B E:m+1FW,Eլպ^wbqĖ(lĨlaSzcZ!ΗKJ bqH|LV(Od*J6S%EUwU@(6 @yL!勐5 + {槫ydk˾Xj[!=/%ZV*E3PEZR̗T)s%JR.U$0lɈLT6S1ׇyj/@ *uȍȥf܂s'wWPKjU 4W&UdK2UQ%vgH{E;b`NƦa$u6d]G-?hh#n+ZvlwFm+jjPP.M(۔[*̋)ۙS~\,&g 2 wQA^}nfkvP *EM1*5EQPJ!PDѲ F˅5 r}n77}Ss ͹SֵXk ~aMV 澽Q9 +plZЏ>T[-q,QpZˋ?sִsMٳ˴kWٱ"5x)ז$i]}mR͖ :&[ +.PD5?ɇ;y'b5ʒM+Kӣ}xZVFIΜ R^\}ARɡyI%?Iŭ +_M5? vYs-}zpg3}jb:-5g|U'gV'L:9|ƴIJ k˿WQ4- *Z֛5H؃o㊺-> A13)_K[kϋUJ9\)lRdjmzbBMVZlͼI15cjE]w"%l}Rd]Kbë"?L,ժO{pz@m@%"!&t{S7~u^ε̆}j}l`+S#̎_ް)* 2jy0ՖtcY࿻. 2)/ eo3rG&&YM:{F EȻqưtl{KB6 ~P!SSo#Am PD=8] PVG3@]W6X} +? CgHFg(RZ -Ұ"%\КkilWh|;>PywV)_\S^t:PmC=sX@Kȿ5tz8lr7&[<>ەe~Ջ}ze^ rwS䚾o}ԣP+>)>т V F3HEFGS_[YͰxtl`8 K +'zTW` 's .sFXE&-8G3xg/ kȿ3 czG +qcq(`)C%K^cqdc<N8[NEXe7OYp 6uOO'\;@D D0xq8NȲ!߁R'tu~(4 D;k̴?pXv k `B@HX?/a#]F:q icvQ@^yU%8p&cP$e ߝB% yZgd9S3:ei!֛8Gsu %rsg{~6qpiMWY%0PD Ejgzsc&]5XI /|K=nx-61c׷DkURQRe7K 33!ӱ߇L>=Fy F BiI_Rr@Jo[AҶ?CW!~z6' DUgӴ4{d\ n"7FƍqӑÌۑQ'À1]0>phZ>P|FjO-~dnk/ _px!S,1naafAV9qUOd#{%N&rZ6a9InuD8sj=N)BS&zö#JDo~^0 }\^|fp#s˥ Κp:逞U.OHF[ek0 ++TbՂ +!(ؤ-,愅+AosF Yȵoa'g0c=lqtgOVDSIYUr5<ŘT*J6HZ!>$mۤQq*} H'H_$eK^%/w]h.R]w |kW)ϑK-Y-SBh}X3K5 +~R'3RrE^"ϑ;!Y~En[fK3dJ2dϰ dg kEN&@r;8Wo, Y|܆Jܔ +6'K'1Zڨ8TTtU&MUFҫ+ROdW3 E^[wnfp%/t`l{=haWq꣇b71+rE"ZneTH:AjjB۫ku2ZFS*O*3u^]׬ȹ +ؑs/*s8зN Y',t*ѨO1dņ"#f7&T^dxM?`9XX dtw= +sT . Z#>=LsyYܶ’ݖCDs^+"IRf)YDSg1p]megkN4)Y2Ɛ{j:>-UGCٛ>5Q6f3kJ>EVJ%Y|qQT%8fKy)-w^gOqbGbA1UȻP~//Gzw.]Jvti`rPCMBR5jQ\Mz2&?ZS%vckGy;\R|"╀l)$9h&̾h=(F`O{zm>9L=FڤL`Fp۸$FkP(rk.ZOjmŴݦ>jz$ԼMpf/N0ԂܳrК~^ oxaaV*6`/'A>&'{SH^З+'DFGDEzF=ݐujӕn$s9+jp֧fԏԗړ]g?%4 78绂/l?^ŕt8D(!wN2э#U-~qVpEJK.%85Za9 m1美[ztok#n>7hky:zg@[hv #O>OȘ)A:a#;?&vF(]ȮHmأr{: U='۸'AOzdn qm_@kyu Wl2C!SnBcX=Iu+bXj7*t߄l%/%d B=G_m>$n  / ra4"&J-Q I"W,FH } 5CMg2$! rRJHmBGxx/_ZB%T F P B7$ }* fS yˆL+h!^k$$GB\ Elω{ ]AS9o)} _Q[DAS@T@|!$/` _ ]"P&ġ8EQ!f d™R!H b $+$$] >1GΈ"Ǣ>_ 9Q/1%:4r ~VTJ(PQ&= Ň,`ZFfB#[)t'_%} O Bxtr rr0+``W7[C70Lk|PK+/y.꠼rQ,M> +e;-wCAC``J8*FPEjNQ TQ-Pd]z\4xI&UOvoݶZ声FEgX~xw'Wn 67l0  R礈 jD&`?{>Ac>[0b3S]GR݃i_تث1yNs٬nuvhGF A`QFѬrbXX$g1YGRcs^LN,S{\o-6ވ_η9akfSR Gx  T!tZ!FrB'NUgrNbUߚz R93˥-ߧ\Hp>mG@Csi'Ϧ7Lg=ZcIE~=oToK(QQj~Vbe: +#es]\sSFYŌ73B2ߵ͚c; T_e .:6gOxMNh9O'ѻܙAE ry|x5γajs8,CCAt^.ob~{q4^ /q,X_MނC1 *{W a3wC!F$B7Ώq=Rq}Lnv~@'ήsVΉfؓ:6 e^6 XPZ](Ui STzwX73DUrh%Y|$:;5/K$+$II56I|rD<*KV,J5N/I',0bsq\ͅsh!#[k2$"(}|kwyILt}qxυL`7Ρz?ԇ Ԝ(: y^RG- &-хmnf穖!#~>ÑapG=G[Ʊqڸ˭w^Xrz7vk3VNWebg1@y/Rqƍh@}?XI}hM}`no{aI[ ᥎O4qx/c}Gm|@#+>2H)?<@U ;!|&4cs -zN/^l]l?ƗaK6/Y:mE4瘡 \͛w$_Uc@@zW`c1ߠ +])+S n1v1Z=C5 2|6Il\\_YGG.~E+xQ6CG&Acֲ%F:kjRo%YoN6Giz:$LW#Jm Z@;@}FF̾ .)ΟQ@Y7 VV^Aẗ Yk3ɳM 2  0 a!("(-RW]WOZVlݫ.Jz<'9'뾟'9Dt:Xb' +XNG]yh@vb~W}eBԸۄD`ڟ2!D .L 4 3#{D!/(3KQoh>1_?EI`)Rq@j@1mٍZAQ7~ +}D;u8 <;l+E9Ը\- H1QsTutie (; +zTvQv]Fwz~h~#ZV~= +ჾt.s9@|}`,cDv 8{mCt.>o>ioy7|} 0W4Jb3>`j]` h<hA)Y5aod~6KIh`vovV|1xT 'b<`b!Q">Xek;'!X2\$ӨbVZgnbivm;1sSka}~{xAnځp80oNB..cbAn.|+x0qN5 470Ɨ'7p`mGܱwY`.?z?H6~1T^sw* n4nlK!Ao9 /Y/>`q,B|_|a\D#KO1WނaEUy&L-\c\ocHŐf zBzR|>l]Sa-Z +GC3;.\. !E8!u ^L{-cvx{{St'2KK7"Q~L?"1>$.![EkE!<σc$ԌݗP?vo& ;v%yH<ݒ-͉>M _>G=&Dbך@tޫ73uɯWcE<'3CiIN*9$Oݕ\#¿%y6`!`9Iy Qy4pB`^wAN D2܃TB 7E\Υ䛓nyAQ2թcO5=?hs̐MimH[&lmZ>mduZdUyImoW" $+RAR +aU:ܿAA(wk\ó~o!s )496EȴnkAJ&:`CFvIّUZutzC +jQUG/QZ.RA‰1>sx6yxΟ3No8Rf +7i&k*0%MdI&OZ3yFLuflyf|Y +̵E*3Zds\ysee[6 QpB +,:K7|^栳ԇshX 3]LMJ;IR5%'ziN|QV2<"kiRyV]RYVSRfoRhlMoRIbb&Ɇz {>S}us +;ތPAcibSmr\tUBMtE~^|ٔ(.L-]:3wC]SsI-ȹy4A٠@AUr ߃E٧c[@H[>ٷȚl_Iۼ0B*+wXQdNzpŬ iɴtmQzvJ_ӮU淨U.Ӡ(, ozETVE +*; H;(PAqDPhTPp#h .@M&qIJ$*ʢXj~< Ϲw{ҾM֣^f4]9á~dܡ>Dsfnh-)Y`mS]цIY4+3{AxT+fKN(HI$'e$'dθq/!>c0^)%.GUr#_^XTjt I/NU=ofvwvO6{kVmv7ç +=*kzԋר۷Q'^C٫AcaE3&Zmx4Ru$.pSHzr`B嬺 }}=|돺Է9uoG-NNAp~ 82 AG4? 2-.u$ o@b}N%j^F\h\i|ff?[|e38+x&ttWP ב[{28 Y6nc"]mn6o@mmjsn홊i̦WN8dh5r2|@> +s'_ @i+!Wv,0;N~ppxʁ )ckʎ-z'f/L^y}~_/_IrX@+cuk4SG)}_Yp!IM.iCoFz phMBGO#YD6H>3&P6M=H/)0r{]'o~FKǡ>yM +‘nD ytA>'.ʾZ{*wOVҺX9!K(0<_bzoL%AtQC (a'GV(EPJDQLB1a*j*8B'P)mUgO=y{9ZVrdQSo1BBՑ*DȤ:"a;jKԐh"Z ]a^kr z6(-GA ,R (TGձ(*T~dCN1C W73(^xIռ`y"C~$(fr44Tr+J?]:bƈOE.]5-NF{W j~Ot}%>˾_b{%7g{/'! G(x0 + P84T裙245 RF4fTL>\KAqwz1 {zw͟C;%vY޿,Q443})KV_e0@ ąŲ)DH $=!@Id kX ȾCAZV7ZZ:ں[vth7~)hJ.3ZB +ȷb,- `Le?}~ތ_ǭ\dhW]ܺȢ5 QkE;e9av9b:d;`M;Ͳ:cs>ʺì׮m ݧ@"b^ ,K>?p̯sm9ͳkO>町V6p_b=GaC^)}I#=ؿ&09zq(Sf` y+1r>)%G\]I+N +y.q3#LCm>ӂ>a3iRI+ذG4aBøhwLtwDtwn@>@DjDT!E8Z_P*CvkAL^G)-V51Yɖ:&NmK%O̞'d)&Ul})A0֔7&{(@k@~s?b1԰6u6[6Dq^e@}yudfjI +O]%NqqV\?(J O%ߋ |ȗXS^p eG׌ J힠kh VĬ14= +$~9ItuP! +RCDbh BQ_X>+(bbK!_ 1S~Q]@xe0m D/bGhhعѢ7tvUiN&6q]>&+ ꚹ~~2&~ū_bbϙw*cLyp)` yo7z"_Hf`ˢ>^cF7C%UvS417ED3ѹpc\ƴ?Z߅3aDT}=<߈v?4doP= aJF=~4"gfac.!:O8DssC8<8} R +"rz&Fgh.zgty"Gd"g}LwI!gq%ikǝm6bhM1Ԯ~}Sveq +IWk{5Ih{jH/v=ݮm74~ N\+B-5^mowU1gnFluIX5הPصйVsC&[*ڲw>`{@ k.wWiN|@02= ث.r^N55iY{h:v*v*6O١vwګrx#Єڶlm^Iw.39*-|=sBX#L4B&]]˹<7 w~|WxsaPMKXJ`vﻀw|ȡ;x ; M|`j ]SwhPwk6!kfAg"^b3%eC|s=tIuXx_m +Vq$ORH?—V>}s+a1M/>u0=!t;Os_W Cշs"^"F,=I //& MTJ~Pݏ } 5>y- +'A$ Yf$-2 +D H +d(S|" |Ffyk El<ƪ eşxm($+32C3g[#_%f S2& It֢x +`/(M+?6eIBb` :fp2=9&23̤*yy>7?a7?LC&EI#kg^F7B1C"c3-?LJ'/bԂi\BrzVӱMs u~ W*.(*h>a2Kx h'j5UX>[ ]-mkʕն}ʃ}vwa*؄2N* ^"x|IJYք@v|j\!&UuOuP#ԇ:AS0Es0K9}I{hw u%2]}c?UVO23$N^ADKZё{o7(@zݞ\IH QIՇe{ 9ܰ(䏍ۓ'R>7U0U.Oޖ%uwYۧ4ǝV1w]m'E¼*E]@F$Bi>e^z+P zK5 3į<]e ,͜WFLz|:GycرRfYr +Zh .p<Ҍ]ك^drwX +59!/^q&/h٘=ݺCJrƄZ3ٺ*gc-t. +[+p;K×9w/98zDnNKl,2Hnfߠ#f= e("XEv +a  H)Ȣd*u.*{֢S霞Nq9F>~znsi)ݧxS<O1;oWyy^Ca)/w?w/cOWN.q1$ׂO +lz㎛^K-̃dNE;I8â,߾\1`w@2 n +zCZ!Mj"^pZ8&gju ud*\CjV(BU^XpRd3^H2Ӕu3fv戃EV2YX(E賛h]!Zu4HHm|dE֗Y?4Y daH(B]5k)ǨX5P ̔nfTX#?ͧUQZ/)䨢t9U9Jq;\lbO0Kg*XS)[RRDD"k=y&瘃{{0x.%d.8#8v$*S AaG2zE^LZ*VǪb]$=.̵^esزYߙ2 -Q}`/<,cnUNJ;xNUa7_K`8i8΍FCH{7@o+h@NGSdƄ][fWOj0`G^HA1hC MฎA;Xóf F q jz͗8wpvB1= fT#Π%PmEClG`sT,/I6ǚ*YF?'44dn{0W/=iF;]" +}5O DQq}q Vȝt$5f˟`l枈wLbgČI\ccQ {F":>1ΰ.!ސ޿5gF&QjעvϠ3oqTp-DK-´g9o)4sSYf.jE:QB̳o8ݖ_O)b{">E=$I-ZC @Y y @RְT+6ؚhhlX(ֶ֪![_e_l#<%6ak g1ޓQ`aͿiH uo8=sCH dt낔wAMڳPOrY4v/Nع3iXgb*cM㝀n6n%*]]`].}v`%زD%l$F `|/[^q~"#jv%1f&{ 6@G}`5-c'|]6\ + +q9š~|\<{Yԟ9qwv Ƭ˜[w"P_c'_6?*+w + MaMHcԡ " +" QDAE(+ .F#ڢ$h YK4cy99s38sw}޻D?[=v!z s l/e@0?p5 畘"|G ߓUo :}1x1~+׶DoDp }&P|  e>шZK^.杊yG=s/G +5Ut>K? yaL 0\JX)u`dLBF֪\TM1 +0](K@l;j8Ko7+>^_x10DB 1 .#%bH+g)^V}^?h.GX # H1"1b0C  1LF ! pU RZeX݄Zn,U=(C&^|"0iïA ƈ1!)sL3B8J02_I?#}ŏ#+=z<t~;<^d&|L΄jj*d*&0Pe<+@7 %˂g>UIe=' UͥB.,ketETIEkh=]Tk~8B47#ni3:s\q1׺勘g<331зpiO[!t]CRA}g8:gRAgMY2k-tbIF9l{-%d*Le%Sn3߆̎8oƨPhn¹m4zR+$) n]!} C9*a5N Cͼ%_HNKHTwI^ vJpZZ0(r<;Zh%[K:0{jD~sQî\3_t//w_.+]-#6ڤE;AcOfON;|Z}hVhmU*0bl&#7ΏlծЩeZ&^; ~tw/.`k=3K]ώ!篹/td_6dV 6,PP>N>`~]Nڀ5g { V?7hʏȌ*&2!s0#k8^ÉNMEKM6`WAkL90P90`z.Љ=\ԢpV1^sc$0PYMh⨪t/BXV[ ))ZZi,duYH=6!lJ/, ~lSfA. +bVaXFr$z Bj5-q~CzO\dEDi+^1,G?{Y4/h>PgDs"G&DLS ORNQ KPMH}@"`{s޻2V=͹\5(1Dq ֭)_/k"{ղqiYIn 2g1; eij%IE wŧׇƥ mP'Ai"0v]>~W;Wߣy|kj=6k +][#[Xek8|NNGJ,+&d-ZU2)kspl&d|\Feeoys'9| +&BXuBKLH[aZ4jx.SS<'kyOҤeM+)9i\3uyץѭRi^mƣ{5)J6R?YO2}}p}YO:L(q,q8z_jw!ah{P Ğ.9{? 00{P?lOM`fX7GxX5e!,ZaR-5RUsM:F!өHz8{v +lf]Ɛu[/HzxHxÅݳ"> o8^fwϕo`]D& pz}7z " ^< yque〛<{r"Ő7[I/7t\Mwi  p?O3k@z~g^3=<C? >j$?/c)F}N?d^{7[w>wP|r<ЈKp{򜗴y0xOaW3<}W3=+߃N+yLE/+k@x^XE2,xr  +6|:e:F*&3dR@62B%}Z/gzЈ%~"zYP`,Y#kd !O'9zVҡoXGFtU1z ]9Oq-i`kNEت!y։?DJI?k0e Fv5hfMs]ɤ#OPH+k ~a/ً ǧ\&M..o7.m#wA}Pk>X[8ҳGCOF =驢c؏pn7qUuAHAF?cpMOaӘk=idғCO=Z~Bvc +2>×8 ?Ϯ}観tBF!dXf N K8:1zV+43q9|PoB!yfbt{4e"OE<\P$݃riZ!Z3+EY%̫qb/Z-ٲMm89)Y %G5D*>uo-\;J P e3?BM"}65N;.E˰hr)8\1]Am]WB/f5`@H@ 0?B$"@,b0,`ldn/cq8I{z6͌L3Mn&mƎדj?~#w9}7g%t5q mS7%ECySwh8$A} .D2?Abc{$&Iny\OhxJ´/Ycl{x}A:~t*&i#zOcWU6}{0_ ׾}CCODwt !Sz] +3Fia;p{]4}B4}\&rY]Y,)oANf<E&[ރ߻|[.eex>G{R;!6k怣΀UI_d$pY2$tJV$A7IH> ? rp23YC@Fe!d> |v?ţ-)sCׅb%+60VÉ5.by@66f3Szv1b1}1#~f0wFWbH}-`oؽ #E1h]FrZf5GOzevd̨l1fXc+8;Xp+alobkcyxt, +2/a^Ղl)h]iR<y󥒠0Gq΃Xrר>~DoSt% *vJhb-ڢt]O&*b)B<ͷpB #𗰞uxwLu4‚5 +(4E*u`_ZCUiʶ$'K9ܡNnS.XRKSK@o({TOtW%}3ug -BT='*3d;rZW!CSڦiNAFziV;&:N}iTcV>gVK*O<9rܷ݅ ;zֳ~h.M1cB[Mvp_U~ՠk׫i.i֚&mN1jjW~+- [[S*48͗2t=Asy?xl3|X2kFdߟa3 @k4Vj*Od긕ZxVN?ge|9ZY-{\liz3Qluž);_&f6* C`b^#yF@q +gyB1_4hDY0ņu6#%BzĶ=]Y͘ݶљODw +_X^/C۰k691"dt@A3Ѩl&f8LrtTAp$LFf9v;2ݑ"=\X 8N'oM~1,;"4} cnއ߆^#tp`;Aq0gR0*\CKE|3SwVe8́\g0q/n20I;_,Oݼu΂Q`OA Z@D|!9D5rLWĤtWUpizTW5%%hkDڇDʱ?{$3~[n{ XA׶PhWG*9tMX[D_; ϗ# $QA[ +IՈ [QhQQQAE)""TD"QQZU]muluU}@h;;3 {~U=k ,Co$ye Os"<̙p7yU'Zy C\DI1ֵT>AƠ*B+]50(gK_8XE {r Ma42 +H- 4ҁ|sQ75ת%7%;r?&7b7`-G)Qͮ7 -CclXxs-<P~^wjw)5@<15 0}I@ +6괌E8!Y$炁 E&"{\8Q;Ucfvy䦓ƒ;#@p On/S9SKe*mȡPŁvu"wh]^8ѱN372d/?zD ?u#ׁ^!FE1\gSg!ǃgz,D/3(^G1_uj ~=L1amOM2h>wI'T!FZt ͢bYE`1bŊNp㾫jn:]TMQ T23`=^#l!~eě xx Ӭ+(vakȷHh#m y BE7XDR#/|E<{;~FCR}.1T?S%2|.Ii6 nAχӿQhDz*Y1d#+d]yV!݊;mT4Zpm7SA7D>saE;Ћ6*Oއk&YsZH2rVL^spJ>*uhEO:h#I61.[x~q^OȚGb2gdd[ q;%8#zAd3` @3 +}g uPf5ĒORHH#g-99-< GQ(!~sˌ6H5P]e]|[,oO=@?+ie18.ġEGI8"K!Y:ZeaulFM),hE$]F=8IDe*DTiO>|o;M)kף! pe&)&XK+nisn\zc=PRu;UP#J^ +۽Da(xnu_)Yj, +u%Z]6jn.צiA9AAvYvvڛvOWi#iԇm +#[8:c:ڳKk*JFXo֍u}c>!GzB,}:*L}c>1]_F_锦orZkuN}眬{zaKHIaycuvq:G=fdf湮1$R\WEa"PLS\6rkţV.Fp%v{@q&~5k9WЮ-.(W>*;,.3tg\W#S{V'=UKY&"c*~nq-q!=

*pH5#N +iD"e=)8~_C ~vd/lVB#T?+A 2*%vʯL;bi>je9!ɥEaIeCK&6N(]P#(o{%901oϔLh#D*WȜwȬZm^mLoMxՓܦ-꙲0'iL€üx"~ mc 1i*YM#2vHm'!-!}@B}׸1sGWy?77&Nݣ_]w홚#UʀUjF|[ ױpWCmZn'-2%@D$D%sHX>yT8_Qc,q626}:Ҹψe/ _vyXs.MkDY9s׋ԁD%ZZӒ"K'n +q,>6qiawqzGqFG1pjs5,11DJ62fzOxc-"*=q=`/]nb5DlĦ..]\Bp@Γ-{(=I弮ɹSd)Eq@$䠈+"J_{X? \s ;?x't'j`5ȱ|].I_C. +ߖ6le?]W7\ӻD&9B qߋ84؈u9<Ӌ\.rr!|** +_K? k'uyKX8qY^pހ?[v7&0AH7qtn1ѷI7uG׈L)9H%=Op>OR[!"_Dab-q|D>>Ž.Ё{]|35 ߴsî>~r>Pfa[x@,h~Q*Spۃ"\y7},`2!P4O,d<| Qa.N7]R!ȯ/_?"},b`"̕3I9#-SI*R7؛{Kٿ)sG>eʾ?n?~bM vOb@YFOSqf,|sG5S@vKqPk-cSmWy29r$D>`t+OP='1"ۗ#qL™INy3GXiƱ{\)krsm%<""Eùm9x{ PrEn 8)ġ,ۣ-Y *mrQ6xn9FNkDt:Ɍp >s ̽9IU|ɸ#b _Ɋ+eu$@HBlFY&,K@Bb @lFHYl 68vܺn6IdI=4kL&vNI]0{sGsϻa8 +y'[p 71'^ټ&7vFȟ{ޅ]A]1 w==kWBQtDuD?=͂;TM^-F \g`y q; YGkÆ& ka%[8H‰@QOx캏P,O;p+ rZpRX \osm p; +kI8͝U2*xc(9_s<呔 ?,5&cً}.,q8ۡɇD-X%Z|]]rx$'qDx^"fSfP\)¯S N$]$ұ C&ة[X7p1! b%)r"IM]J.K1RRiGRZiNڜNhDөS=&D7<t{|9>L҇$m b{;zv+rY3KQ2{g*=g3Kŕt5-nzE5)vfZZg _e 3ŏ}ff~ 0ӷ +csP1>/l\NI,J`^H=,{NKsjƄT|Z1Y;,ec4.[`{]ҟm?k%mV juo/Ensv +-19RS<c,O;"װ~r]'{C]@|>]d_jɽd}?1iPC?Ŀ^Sl`.bz)Kяst8ɢxS-)0 +>Ua@4[Yܩ4t(-mJǪ(rӨ\W\U3?3!:yd\-'<| ylW[Ĺa\`BN],1\ѯ3z59be`{&ZT֬67"zu/V=5qK\C9=n L2V$9H/pG*lu=Jo\\ |:*`R{^r)˪l.U6hK#J\So,i2hz͐R3%(,tm E}+VHxq6`nd YgP5 F1n5H|uS&P^ί,3F5tZ]Fw0Xw$F[)mEJ(J?(Z(!#2c܇#3%d9j=>LJ𽯖uQO֥x4f19Ep(ܠibzk\@JUbr+ˮ H7_ܬ9"ug#:<-1؜HdҍMR_}C^0TST+Tfst%&#79s̳l)|'5)1}yDVYڀW-l{"BއZZ4C];L46 Ԛ.nQ4k8 +KER˱4en2oXVY69Yf6}<$д:VCVrBFv7j` }o$S=bzQgufB6#GbkdٺBŶL J`Z@ZS;~'j{2 Lj&ܼkpYFfۺho FAnB5Fsr־RL?fKEv+~7~'~co3.IݼՆudFz0݂n ޹Fzt2! O$$ )Lw*Rc$:::8'±˞ coxď=ō|;3HzG 7зه#B:bph? @\ rC+Ht){\9T_<.:9` ]tԱ4L%%2[3[Q 24vm2ˢCu=Hzo^<}~Q2W2|KI{DwHԗo$ ່c7C`}ᣅ C%Խ$~ߝcP ;| ]@jޏnz??#:H@9 /ZPRw= c0:BG ._{?Q}@w)FQtDZu#vQ4SЋ +t>N[nJoG~x*\^;E.tp_&i<Ѯu +N!/b\~ <үaPgCyܰ V<׏7A0,l{UuY*A5 /X7poZ1͐hNBg:g-^^STN X>ŕaP3D1+~)G;Y{!hrE}hM@#Cuk zwui,ИFϠڳNolOS&Fc3JF Tr= +udZux ~)s|,YR0g~JenJev~KN䳾3~}7K|bp3xG Əz"WU+E8-P״,$-ݒk>o}BdLys ggˬ5FkŚZiiwHTO<)^zgPƏtz׫1lEE;)PwÒA}O:.t89Y801ccb@## njssNwNs +pl + a+!熰Cvr8=0у~ x r|`?(ZU`+; +%+X Gk_.(+ & jPE4DDa(01UMms4$͢M$M,IkCHN[9p~NZ9ͯ1cv+=eh5#ƚ+*Li i̥iⴭ´}GyͶyͶl)׍P[|MyVA,ko-P,joX7շ>71&gЪlkHEvɑe7f:"3 -̞ȜYGfdaM*jfydMR +u-U@IJk_KP4P_4٧0Ҟ4`^pI~0// Ēk}D>*ikJmf3"%%䜳"d] O3=aK?p&=plbi54G F-pܤj$~ف%sslم {y^joN7HYnLm?cU9191cN5tvH^lV-eKu؄᪬RyU2Χ2?bNPNyZH4GADaIvXn+[lIrF#bcWxP̲㦄K4_1yL +x~D~>a54Vj-Pqbrˮ5 &e̐dg)Yjta3M ΝӝW>aS+6JX'z rt_pIE _dTnHe7N0d4y.J4!9 e >UkcrJ-Cec,֐2'%oFs|sv@\sa'7bW RAIM[˃F7xsݰaڍhW57"Y'IJt(b5ٝs;w7=wggLzѭۼoj=5jUW#y|,-~X,$\7>]v9UR߷Վ&tԸYkaTW!Umt-Qdg;{qTB^RhGZX + +]Mޥh笓歗ֱ^= +5-Sx{*w{S57WA[+4g|{vg6_{Ut{~jnu]AMRvuR]q/ݡꋒ_7x`cSQ><(8Fr}!mcv~n $7%ԻS*!lla25~4q4jWU9C~F68H-A-,;93=Aȴ^Lİ{`=hvnEO&мyN*Aa`Y#xG A8a{MvHw+pM;YІn%A 7nqJHKK')o" c`t2A:źGrgI,q>V/o9Is/4=iiO:/K0!: FWzy>hC;=9^>JY,E/Mp&P&A4tXn G31^9C&'?Ƌ[;sC@s5;g?0h u]U׽{ /ַڄW۪hZ,\sw}ʓ>}xy !0 +ba(ѩI +D l@g :(nw!n=]'|LA';@Z1h&W +yJ^SգehFc-,FWY 5T/PcNiQ&8}$2*랓hc+ +h.Ztگ8@~z$ :ʍ>'5&`4G9fM" S|\tO~];Y>9uqNby+v}_c|BUx)8ORA Z_E=ZOQYtXHY~=Qdp%vsQyI +r茢NX鄲+X\;^ZJфQ:ͩViVN3kVݥ)[4zƷ}JcX:B*ẏ DHCѠx6zNoE'vhXwJZLfOvl4Mgi"t(,RH"ߠ!/'́8dLb9\h1(q/!wCmtF7vHx&( RI}$5yN["iɜEc35euBi.*mӱ֫eeb-ec̥1[>W-lfVkpc`LUFl_áZu;vǑphDP].sTUv{[_n[c8~EiØBb ++>WB[PX8xpe4Jݴڝ{l^SSAD]Q\PmTT)q'/v⌎9eؽ1E<y^?yU vV}{ S`{/О +-mЦ8ZUB[9Bfv*L.WlSY5FcYE<ϵ)9HHr~/n,:e=A:<`m!0h;k:yT/j=TIc*=\>Y,4QhIVvݽ2{$Z>,uq_gw(/ԴN8JsT+<۰'2|3 ANDqm쉢ܓɘzx"W﵋tq]eDiƻ-H~?"ԝ0͊r)pL:n7.W17H`*smP |MNlS +79pMnL}fg߹;zX+ePq0 "g/ܭpكDf\ Db +œ&2BҞP!*eԡjNR034l]":ŏܤQ{)LlX \I2?ƒNrhwXBN Ru0mp9)un'C$ /x vFE}^q7 3,`QXe ʨ@W" AM FlR66m6ƚZIr1q9>;}{oqE'dYg}y?עhZ#ew +$#JERdZ*`2}|S>:#eqL9I' r6y < r keHKM8% +)\ +c\ dDR#uxQgIa>lh8(6!ߝl& +o0xlXu ĸx?x+ApJA i_Baf-ر&dmȚnŸ73nbȀE.0P.*cF4J`vّ1պ6 +z5[ hwҔ`G .].6ul<7M}fs>1y( +;[D44;h7zuS  +1""G9QlG]a|Uz>"S7I~0=6Y@:#ˠE`NА!GΑq!Rpu q2z8 I;EQ0CHOa2)t A{09G݃FDnҨ}tܸNoqE2bǾfi|=nQɎo=avfm㴶ͺ>BeH{]wϷ-ia} +>E?hAo0iY7z4zbH4l:3Y2cbf&r}+'j)$Ml5%~JC!f_`= n1~4Y0Xc0*pZW0MLg%a>"hy[Yݭ^?6Ĝ#sw3Wk"?[ )_2c^T>J|akm$5-4.7A>//a?a 1D֟i"0J`T} 1qBVvI)Kۆ}XF|k^$X8fű0&Y)04F^ƎJ9=D,6rluX~4a=VG"Z9v'''pxXqpc<f:je-Hn:Xc;QCռ.}u7UIU.ocGIe-a%y8O* UcXjcRUVҴVm*3 + .㚖YY75n\God5k֛{:(ZnU>EU!K~UW+T_bF-YKw+MŽwg]"AͼB+i+F?o漢NʧU%Ae]GkE-HVq@e<-)V%ZlB[~\qvA/nhvs2tYC\\sMa"u񵁴;6lO{OWIO0h +*?hS88] drC +RaYc +l e>f!-af 15erS҆6žV-!~*]46,`X6ژd jO5>87<ה^`/5 +5dJ iv4-=sr/S1O uyLy>{"Jz}=>jD5|*Ŷ~̞}}?@"B4?1>Ȕmjβ0gzd'y̶xgyEf[R#,#[E$[wX'Z'D&j{~.븾(emytպ աh|_>ЪQT֠0lGG#:1:Ñ5͑X5Q5QX=ޣNx;qmHw9iui6ZTA VBQ-/7ڬ'+͎}Ƙk7ψl339f1>b&.)z\11K}GGWnw C][.ށ\>/^ڞ@jT +n1,ɈRzREY&xMO7wl\R;K?<3 7H;RE,*dQ`XCP +AYq%**(`eܠZ"S9k[w˨ڱ3gTghmi3p{~3} I |j%NLᝐءxROS㜚8t @\g͖"2ijO,CebzK^z*'M`Hզ|R "]B`7,3<kr@;:&: M;qNmTJtj"tF Ir ;g4~N{fĬޒ=XrCYY#]'dqKLLH$edx'tcuzc.hc\mlFD_i<1gDmT&܀Rh4daB4X<1$'Fs"b5./=4^7MĘrMѦRmJ3T5Ԩ0m {}x?e8^ӖM/eD&勘m/1I*//U$G[<# rF6T ;XD;oH"@"O-qe/3xqxqrrjZv!^=W-3..l9P%5" ") w _*BJ+35o6ȣ`y4q5qֱDҍۆE`"/e^\d,~/m&Qpa{6x>!i&Dcylf=0G .V[+J݌x^d74=NYC5h*f {I{F ife+yPr=Ev=CA6ٓv{жُ]w +4ֱRS7n&zfm"jJP=r2 _@;CKM:dr?1)qW.X)RAͅo ho2..йk%Q0aaLnL3OF\}ġx <Ϣ/_zrv=t?9t>@#+f +K<%)&~5̒ǻvV5: ʵ\Mg||l''r!w v\\NsunIHB@nJ-v6UueĺJ6mZM6iNl|;Gw<9aǙq?m߻lIDkzYk}Y5ӂS +N*XVyq\ǒ؉cb M1La^ǜt `JSLH!{qO!K +58MI}N$plS%`1 [Z1̤!naS#L[DY]Ø5l`]D D8?N` =ekE\-y9Gˌxf$2Ոd:tc:ˋCY~Lfwb"rb8HγA8*r^`wП?BolYz_ [E>OmY$YءlV+T~T!VXF(jhQzH.> O ŋB)St[*zS=WtK^ +]rnX({>WvQ[y2FLb#B"&bU s2dP+{̓.2h^QU*[VӏU-%Uޝ ]AIUIW= y0)O+0VK"baZڕ!kڨ궶u+aYzBk=/z/]r_[]OmྍH)JbgK|F*0d߆~{&Eݦ;[l7kvf^m=m6״ڪk+$9+?O$G*K,#Nz5'hc<'Stt"XS許vVjn6;[uMΠٯw;Gu)}3w:q^v~MWx_km:]٪duPqТy snAw*7 eJo}vJ z׺:]IW$ik2:T:鬮7{ڿk˪?ӕ9'_!z=mF1ND=Dt*<|͛ݎo<^kUhjGWylpRgBo,vyV%umMIoĝ ?nYktɺ7}|r܎ڥҰH + +QG^ԄhrNdGa[(ң0DHހ~gErHFr,Ls["_~&܍Тi-Xb0L:QZl")PbEc4i?eC("Cq\iKob.uE(PNkRL}HAI8 L1r(,6q^8/R/3óI&=4} xd\" "1N0uH= `W&Eh3A`O  Zɜ&$"/4 4sGL8=~|(1{x{a>7cޏvQ}"kbkre 6ScMfoC]BV8vnr>2 %Òyb=65W&q+_%sqq#$fxuN[Z^!+yɹ\ tT7,B2ed$dM2!@$@E@6AieX"XA?0Qp/N|a&rR|z'oeyyȥctSM'fzX-cSa9?c+HH>>H:.wpuu 4dAr??F` `2(EUh҆6씿e/?A)usJC(֟H8wo^q;,xٯy; /љ$Inn1 8ߎ.B]Ъ+-D^D߽2{{xdW /8>| nαF|2 K?NUq?N~~&z|\sC4=_#m\p%ÕWvvYC#IF>*q*60N##d#TyoqGi<W +\YG zNG;Cw,~rq\DO5pWsVýS_8>T>a#A-#Y6ӧdbW<)*xji3Z鄧_c .$ r71_*8]p)@䔑Q<&=2x\Lץv+FDjHe=X<[λ>|Y:*P2ɢEH*']1-Ai .-Ylj٦y`Z"3M 5=*5Rm:&UAoTӧR|{#Y f7p5^gg+ɂ2α*b}bKsh-rV%3.YjJMxTRTR^WJBn+U3sJO-wON~4JZ#)2J2+.Nv)3KfRmQ̍Ts1/TW(eCÚW5M^mm^w:$& DoV( q&$8ؔjKʒj=r4muڦu[Ee:.ײMHN.3ߺ0³tkF?+r _A}Af$PJ6+][fsJm.V*[ekOuslKN[>ӶYk5-iHMMzMMI$|Oz7lw :88tf5K-Z6Z< RRESi j#W(2:* َ, \ñ`w6m~O'_U֔6!!k< + zyқE@+@-,8MR.ٱ˙ul}, HsV؝ )Ύdg!ѹʐܠd=ePc3[zk0y ;gϐ%+e94z0gHRwNЌ\U#rwMb$O$xb$(q&Ɠj#= MEe}gQE]aYDDFVHpv\A0PD״QcDMt14wu5%q4vlTin?kN{3 5"xd"k@2\9<ۭ7`ZેXgK2Q5x@c5;HP4rh.HKޮ +:ޙW +IWsZb-3dTN,ⷣr^ySQR3NQ2~JɕS +v.RP*7) o復n9*qM{2f{p5kM*9Y$JcT}JdrV{zWhuwTF)*C)%J W*F%5]_KλR ;wB> y4HdDddᲯ᢭ba0j|VgUJDc©E7[\} .Wb N{ +ўV+XӀ\Ȣ=׈mRiib5qК(n#f @՟"0$^-k8@ +~J)^ &$ḵ0242m3|K$C.VjYkPRVr:gԣe#"$\/ZJt=H:)ށ og`x<VG~Ə5= P Eܶkк?ۛ^MZJk8oT $,d+.uSRx`7:8l[HVrс/uJbvJz} 5 Jg\8 /efeRrUc? I>8oϩKsi#9 U`_` +#?-#,JGbwR A'NC|.*h2HkEv8C2 L N?o ",}r^.."wHIpNe;\c3=|qi&~߂}p1K>K\W&׹ kwC"@x\ߣ%CEBD_@)T7f¹ {FL|RED>ׇ>}ԅWs}6.:F7QѺ(+Q/U[>Ï ~|"B~~i>{~޷@'8?>ߪ1'x r9&y/~_EoC^l)AxN6гqp~mp\TOb g0<#ᙠz%ku9PG0j5AjrCƽ|뻩.an,b9\o4x5 KOqfsWНfkUh'tzs ܏pEn +"D3KᙈSᘁ};󴖺?Vӧmj*i3x*%Sg>?{CbM69M\k*SN +kSFFLf:> +١އ8 (V +լ-ʎ+uoJYTdUy*/|rç)'bʎR%_R,J,V9ͶWefDSbYM`fjCXφxVN~WZV/ES,gYQV &{heY'(:EDbԘJ)֬j͌YcVjz CSG5;%D_6$D1$ Cl3Ŭ>_onQ0e TF\lCG*m8 7et}(BnrMm#mJ۔Ph-,R@PBk (B(yȔL M(l,{Bs?53֧%M[©1g~f:%?O2\HdE)!R:X*Sc˜,e Ԙڍ68\+2UjLc-rMslR-ӸZj/jioƔUcw)ɧ > N]d{m7T#e Rs͉Rl1),Yj%O˳C-2:(Ri-stdyBK5oђ/hIjb - FOӊ4YLBL@-p#߇gRh"6kYS\YͱZ,knʰV[STl=ٺX7XWi j|56-%&S%:mf> ϣ9H!+R Y0 5`$1T$[/_ɵ [dْ-MͰekihتdK7&k YZET U/د ?*yHjxO -8Kt$PI> +"[AH.qVI1I=R b{dS%jRUc jQ/T"+dp&XOТ?KX5 8;\dpM ;sԂlJ+HR`IxG:2$a(G(! wLA2@B+ڥF|+{S+oKHO@=LYRrOXk@%({#=Hd'5"ᵺC{뎒A%m"vՅr!\ZDXDIi-mkV9; >7m-2݁T _Tâ0Ca=9Ap + ާnI\r<UnYcEnh/L5%b7coC xz8apX<8OQSx +s/|O<{4vb&^y ~`_ׯ7ax#R Fh:>#_Ы9.2EɕWz4`B-hTAu\EA|˕ : +* +K< }$rNNX:xD[@[]G\EK\E|," ɧ1~Ï ~fxN24'w@5Pc$(-߄k[:KLc>i3b# Fb-:wbE= Fn +ձ ؃7s*up-:݁Kovћ;~8 GlBD)+N?c uYc8zw5Y'+BѴS6: :0FGo>H_X,a#"8F1v=&rt4LrYDW.f_qYg5'HbHO6Q/euz7 r(#0311p rȱ +Fu5nS][n鱶vm?zMH4Mvlz2O}SO3mpXwkYZҜQE~]y-:c,/},Oc_B#‰)xR"|x{<5䃣Ȼ 1iOj(_jHnU1x8/{H%d<$#oq3Gc;fc34Ɨ;J] LlV{bԚ4"_Ҵʛt\IU>lp?#Ք(o6f6PU\FcTښ (  Ķa;j8lBkF^[Fn9UX"1f*p̙GLFs~,'Kal䭚$`Y:x|_k5UodK2TQnp: T38[MySsĔ5YF|VҊUjoRUk?S92 ɻ@+h + WJ+"UJP,۪Bwņ2rܻfa#=mlsVR\WuKIUBXw%>2O}2|{x+j|Ɏ4!K Ѳ4$*k6UixKX-J);XxU".)LuߔQSv}pϿfU^o 쇯4אZ4e6=|JnU?Y m*P\~>E(uTF+ub&R_}.5q?^no{H~2+JQm)*S 4 +``x.[fЁkG-"P'\${]NKÝ?&)!d/AW +P?AUpFǼ QI쟤Oc}w > +lb-K膟%Hwt02࢛OT141h4r < =۝&àmൊK9W o5b ~BC,p} i Ce!3vsx|O=fV3i>TO.:ɒ x {n6L;h3DX` v},d"/%8L=9L"qcه%Q:sE̎QN +[\SŐ+kG(K| +1q=]݀yC'#ipH~B?dOˇ6wc?Yؾ xc۫ƑK)9~?Ci چz;>9z4F"ӱ|"XaM.c'~Gc;~l?BadO6CވD,) ֡4)-ODJnbء,w)je?6XO~4~a 7#@[ +pRXN> ;P NV7>ӱ=]Y+?G>`קSt.u#WN _8|Ueb`d)'QwhY}b +v%"ٝeT5#zG>D_а9tg,qZ#i}b@qe\E`U:X! +oyT%DgNvh?mҏhݖ@;tZf9˩/ ^kë`mchVCꌚjZ$j5G y )tQ솻ke5UZUZTe,e8!奿!=Gଁ8ȿ;Q7;h?| dՐ,r +TcWRN[*PinJrg8wl+UIydTv~UY7QH{Y\2Vc2A3_>!WA ,Pea Tj+SFvPdk5l=tCm@Vre6*ӶKd.846ݔ9/LjFl7`f11@Ԋ|J{ re/VqI9*tT)`une;)1OoXԒJ)yRIP|R EX% iua^x\tԎQ#m 9QY9^AE*4)ҢKcwS^e|Rbq| _Z q;FrB;-Rpt SBdB`5uY,h]`/KC<pwT|5乂=Ĝ˩;W"8ڦN>/4gN!V.>T}|l-FP#&2b@.G[ ^ap|bVgG Ar!v>} I>@`Vgt/x""5s5.!ĜHG|}bǷ{\}\`XNK1zy̍s;@.0z^U5.ƅ: c׼шe7~jgq .hσi@*9y?`n\&9PoRKaY.;ܳ2FL;8;jqXHYӷ^75HO^g]c_?J 6 AE?a~ZSt jST8sXӴ؂B^eCz6+ =%}ɋ^Եo||>9:ghO#>R>d;x?Nu?.qH_/и)l/ל):S4=x[5'`jF8Ē O!>;߰ќÏlYg؂NI/t_ [c|EJzW^܆ ^5FW48ZM˕bqXCK61bb&x86{w~]`e))XGavggAwc3hYR'c7~ďLw0@&mrlb[x7zpF6~=b7}]q%c-/dbGUحgЎ.p?#tT/VQR^?+ {1#"#9H~>0x Gu؝{XxrZ%tA'좫;N#>8d嵜^rJNfa?ʻ1 د#N[3 Oc̶i YoNu1}ܾ1͸_ +]ϱp$a=l2_d-ܶ-G3oyPfT_G?#E.L3 +xl8I'$JUKQ%ʧx֏! M7ykw"v/[Ffg=YGMjI Qqp5Z 4*RW BM%RQTPbzT>εCHlB#jiN@|!YT\q0%N\YƃR&z9φHN' +x>=Gq"%j[ D@~4:\[?A{H"5=iM LV y$h&yTdJojSiƛzmڦ̠:*Wy]\ hqoA`(A1{>MCL ֔2Z%(wX&e0@3)| gn˼\iJ1)ɼ_Ǖ[9B*>s p_,n5` <%YO}A-Ej1 2nPs9x&36PaJTj]c,u(Q\1-rtX%K#߫q{^aW>1^m!l/I^JA(9= @*;)1)BcSө1 ٝy9')9]Ut6+¹XÝ= +snVHn Kਃ\ PN88Dz䎏<=@E16F JhcIMjkڔmdB6hgҦNFљdj\N<>pT#A13&d=O)0IFKM/zcǫaaaf>ΐlTcu#'-c%p"^yfszH2WKKN#\E=ìnE#?j> m= я2QluG>xu~Rk+)'y1V%%G.3[vm v V+Xd[7A S  v1. +^bNa=o Kڅ0{4Z/C@=x MMtS'D,w;jxA-"`!fƌ.1VPfAq h=#187t)CWi9\u}?51H] TH;\ G+ف۹@HфOyTE!2VcvImLvPPbt;Fۨ,h)-Փg/14P<IkʹlTވ*8G!Q$, "{81t?&4(A^mM]!I+8c;1go2q*k*<{*ƕe0r=&U1>h7!x p_+4)H)~x}޶k.7!uP8WcSVE8c&(D,!>J%WB]Y,,q?.rPoS3o/Nʅ;cNOkRhipZRs @ze#%Q> ʹ\6W W Va BgA B)e} zc#CObũ |m,΀S"}Kŗ)EO\e;*(1>dX?>aǏQe-9~%gU~u*1pT._gpYb}G.c>5~Ǐǯ5%~J>NӸl/4I + ^c|gS`_d|jmvG} دj(_F9L:i%>) /JD.KKFo oC__@~ ̀iPn/bÝ5E ^a5HF$PMi vFݾi0 LzBI9],jPQlcZ? :UOq.N:GXmgj4ي//iwgGCn b8Z -th3?xV%mkWzV\b6o1@Z5v\B):G̅rbvskv<bnm$6kPr(wm˝1@$ .~fT?Cb9_,sP.3G4![b:tfc .ahO'#S.XzgXCs^LIu;r6{}O}r:wae6VZgQ-_?7odx+3w`&Ynzc:(i:sD ; e_@NXS#67(6'qU|]؞ዧyL:xh= w0sMjWS Lޣ!hʙ?<WMM5I:o y^ec7| F@a[\}o +=v]@'%u߫eK</4p''8?׿DC;m'mϯۙQIJP4%Yz\ '%.#me1˽]i6> ^%x-q/^p˼:x =0tu=#q>9,Gq$Gһ Si*НhA1_ˏMd=Ow2Wj)ݶ<,.pe=*Vue{%ghIŭ1|XGv٭dwhf)_-׳m Z޸Ndn%{)ˬ}xw.Nz2Md(r'ĵ8Dkq*wՕrd?=.>׍.3,&[nIߚ6.m vxy $t2B!]EvUC 9Xgshpflb Du^i_+'  Bȇ+#*uq9RWNn1vٍ8|Y{qw_ IֺzFU2TM8(&X%OϢ +z,nqd K!sU| Rܒ@ʟ Lgl/|=xY\Jan3y-ƵgE;ϵhJl&Q3wYj;Y6س:uB@LrC;ťU/ew3},uePxԨjF%u|%N8zr&,ӻ%+\BEk sGUk2r\b|ZW"15Uzh*WESd}6EoAѶ*b~my3}/\686epD%Z|quExLUUM1K3*HW+2 +ţPnٻq>Ū\X`Զymzg5>79C*gDTᛀoRLIuLi9FQ򘐳u+DK*6'x]8Ν8uGU_a$dwIvͽwwsV·5a!O;٘goWo$h2Kh_CFQLqeIYRhiTLk%L{ŚqT,b(T-k#~J ˊ +|dJ5]k-9JTVZ%ɵvXl+dmmѶW2G%rR Y$5sZ  `0wg45 B +KAI^8Rg|Cɳ{%^!6GXM_2Hc:+ a 9 9luEp1P S(%wInQ؜buISYr19Òl6Iu!)NE'ñw y !<:sوa8zśc m>2HVYlpK%+)J%?`9Uv7 AN$*e8t%?}jXJJe<+Tg3f5G"V ` 6><]K7蠰o릌?>r15 Ľ(8]W7ܤKά,0 3tU;`y! @]䖬ƮAz=PGxx憳s;K~L5TиhbavZ*C83ʇu4uģ#,M,5,*5a0:T2Aȿ ]nd- +Ssp3 p0S"4:vhPXQNse׬g2gQad$!#|އ]m^ >tq"xf1"65 + jiPiɵdXyс/:uptpghaQlj~QMИAE~3թaA8={;Ϭצ$yASNpĤ> C2g2)tuĢ9:U5.nZ<(5"l]ߏ豄e,З/#C%1SE8+E>l5x>Hܡr&0<# +=Nƈ4aQ~bލ (=b)(ʯ6z8k"gތn;gpbÜ6PE1Њ'ODs3A݄/6bⱎ>vl3ܻ:A>Ow6U3F}۪NxMLv؝$cx<2JNl%/|&95|\fyWƹASmp7@|r8;@lG8POB>AG<&?vr+F-YSC{6-CVJ- /JPO($qWg%Xtm:|25fI x]U]~KEjrOcUx!G~'+ϲ[ !6)8OǓ O~&:? .i*h`;aݣU ik M%d e=2ܣńlE‡5ȍ95RFx i#p QZj|m<9ܠ xKrޖ6%[kW;($ɼjda\( rWRdD=^#E݌+8O{ڋ"Bk|HL߬+ɩѩ L蟎L8r(@~ ː 3+!" o&K:h}Iz"3XOh_ۯ6:6S+h&&q$.<8ʑUG=5+pT!*+HO+%Ul|0;9:6c.݉y%&Qr#JߨVj/p 7]3Zu^2C}(TB+tT( v6REBq?4, +gduatX\qD$ \1#MѪScVciS5.uZS[MҴq[5uS퓏yf?sy{Ϲi >kpЃFVxى bf`FvQ)vm4ߪ j:pxxeOJ[ڃ3hZ4(3i7DJ2!^"Rk] .$ӧQm'i>[qpXX\ݰ`Y2@HM,gNƈ8Ab5?6h(cDntݘ.6[ ]$D'V@ 2CsĤ{p xd*KY@@F`|A +h_bA4ϣ#~n9DjX$Ȝ),3ɯ@|ޏQd`n _{dc?a0d@cgnK(!b 2KPP-~D1YRג!>Nb_JY8ug(w|M&O~6v  R@">6r + 55GC|?$A#[mNۓDgdz٩(;&N:6< +#9+1/"~>1` Xt;%$(6)W~bâ#4TAA;(jL@᳝![2ߓX4qPC$ HK:q< +:⨾Xn9Dsc;Αѝ$?İd$KXN,)Z'X[_8z񒘭sM5Duȉn{_JYob=>48yM><+93C<9hb̘M"IP:_Lg?c:?sВL8$rH&yng$ qpyP3#C'Tshnrpݜ 77{H+ a'/"|;isyX>a 3޸\$ -:EgKg3ijH4/e1[eq&8&]!M$Lfɼd4 C\;ςxfjJv#R+g#[5z +=Cy%\0ۓ3 ]{κ@Yhky8V0ehg{2]ݵKQV@>џ=H#&@pOL6z1"{R9&bqcUڴ>3WvLD6yS) ødJٓR>󣡸bnB곀!Ap="N&G馐OlkٯqkfniFH3|T3c!Nl'hQƢe7yxh\Hj ݐ$fsNT{WT1K4USp ]ž#<6vZBqi`kyΙpNap{(2Vf15|Mʀ(CuH` "m@b_RKٓň^>GF'ۜOX髸y(ps+;(,m@c}|=V#:Dd8ڞNд8*]@RC5(Aqy'f9DO?N=JDl]$RS%v]i=I;CrbփR?,J^h=XVa9 NZ\'\|[\A=]~j<3}~A֐0{xD#:&и+9%iZz2Z۴mסc]>x=sd~ ISK 6tӣnj7aeS=;_sΫ|i _YoK._Uj 7}_fع={Cg<'?/_Sq^~ۛsk#+ƾr- ֑v$ż|{> $(@"%`dt()~3?SjG+=^S,FeJw&kWJȲYU 1|٭ُ8WS}P (.( 5-%ӽ#˕O{0?rD #455B"Qh(,0J4<"W镯JJ*T2d؈ƌ8Ͻ,\ڛ,[r5B$Kh0*\Ϝx Ɨ\W]oo޼u6ܽ{1Oug]+SƳW}ɰʫ;F-s;&|U;eG}T3~EC 94АCC 94АúGrؐܯW|gWQ=C*+]~Slb߸}v?vʗ[=Wis&䰉o}eWT^:2lũφ?qQ{w:趺'^د4㨝=gztN;A;HDa $,aMT6u\lk @ le kH$@ bلgpIny+k_V+?m0 VM0-o`L)E`Է:7T4vPk=Ӫcd (@2\Xc\jl;׃Z?0v:ZKkۭY(Ϙmh[_f.tH澣訾QlnU/C!85h rԺgz +e [Aɯ3tufy7ޘ MG$ eѹE]Wmv|Sk$ۥ;5 1\aꜛo -EF}o"' +1<,-ǡ)Wxѩ=ޭ[ր +B@WCYI7Jcx͛7j[0 [&Pm0y.{FXCm` VM֠1!"ej7ifƗ9=ѧ,b3G_% ْcjD8 p`y9۹A?ZbhrBׯx/Ι1{rY!P şkK"*kEvٽ^Ah@D״zÊE9k)&qqtRej*[`P<},fjϗ*T3~Yzh.7~0$IT,y:m2وKrKS4)ktA0A-j/q{͚x)m[γxڧnYU7†RJR=x>)mO yZP`Z̈́-.%C-FߎnuE(;'lyzDm1E,~22Yn@,`8qPSiW+ɳΗ[ L&$LG?6Đzh¾ab2e<Ƌݽv:Fkf_:G[/~PPNOMC6bB dPǏz :͝%|76\!6>ñܒvIvD02V&J'kRhk4>b48a.# +:UΜZb]0,X 1 lĐ-h~Gޥb1aXb;eS?I+Ssquq͎-݁,7?+ +Id1Đg5]U^34.iFGWڦPv{K8[ M6zbOnR9!1*~*Ǘfگ^g;X +ǬICg<=_[q 6<[ܛH"<ݐU^81֧{/Cu7/̙FŖOӢa\;=2N*GfsAѝ@ }˕Mim`DKc*/_K'c"A[|;S܋+!{}(GwMs(:>!_HDS*]Lfs&SAIG,S=DV$gmp9XS]vxeǽo://da<:svf,((JoRB I&CE&H ЂD MRB(BJ" |3gū=hQMiy &hǯ躇/#iח L8N|AHŏ05vԧ=2S}9r9%2P>gfI쿢21i,:8c{}M|mŭlA];m]ӌ +;pH*TePPPAݚNN:WmWI&>Vh_% ?|-}<%+Sr`s>2X8v|PY%`-{KsĀ9;d dP Gwni8ؿᨊ״P65 Ա&3m h&$@qw`}!IIR ]U !H#eA YNƿ aMGDOO.W>VRE"Wƙ_'m_ _ _ _ φmp10 +@Y56IM bOEGǔ=J ` +7Y1~~02đQ*ɹO p[_'6 #&b#YyVc}a8.'pYi!EIՃ}ݡ:BJfo{6in8{ڧE=[1l>|쀒4?13*Gr#u2=fgxgwsڥ X% B +b {ZHJ,$J}B[kG8ϷYnVx[󝨞;%C_Vɐ Bb(1ԅG.l…>- s_zrʄ9Pȫ_Ra %%njE'F ` J۟ J;!1i*Vh3-4aɳbTMhͭQ^W.t1soENMX[CJbVKt'>l|RJeù, =Yܰ0sԏJg JgC EY(PݷVy|Y1'1\Ɔ ='m%ڼ&r Σ#ZO+= d r>Y} 6b((Poл0+Lh8.Y4H--ka495lj\i5^~>/Afg1[zD @/Wݳ\Y䠑+c׾tHӤUR3BV~7l~lRo[^MFt]ctPDviLA ~ϫމ4U75ri}geofx RcǔJKCĹ1^xWꀳc=dmbBEv!SzfECgq 9e& rov  WȱŭALً#.cC}h3:'Ty\r;OKFԜHER<`uJm: l=! r{e'gʉg.Y2);}9Z:6Xap\۾K>{#Km[¦c?HUU^L7McUJܒ_[pY yn,h:}ԽFE9ͣHӖ1)|իK-_9ܶxu"u VsD'/|+\8e)%:(kD) ԉHCv`etJ\4 -bA ;`;`}1 %۷Ȇ{AA! +Ղᔞ7w+C8z֪QQZnh(PDM D CF !@ B F$`,D=ǧ΅^svt?=&b2|:d䊺- +2ɧ +wm]Rt ! \,~M; q0KMLlXgCu1{nT=ܬ \fS ;Sb4WҲ_u-@ԍ26As t1zo cqQ]!wux'L@Dv"YAdW"_d-^K.fᨥ8f,˙ ʧ-+J4}4|4|41d#tĐqHȏC5-H_z@Y $EdgHPztj*qp}FAgÝ6 y>; Ce? Tl,~bh‹xSBjddIxpnnߚF/Asw]= !1d"|u%(XFRK\λ,3d*1?A8~6x 꽸=վJA3&߷up[e + ke=VJ0"sd;F=Q4I$GҊH1'} M@` ",@U c +'_ fg=4נ5(+B!b(A \PeY{r _&?+NFpG e񝢤Ik\9..1%2jGLDhZ7CbU EjTϯ՘c +_ +\jSfC+2}؎DImR@uuFs{Dr{1MG(> UVk1fo)BQ>+-vżv +QHaȉ<#T~#FӺj?@ mUbel{DOPrq%z{uA4'q0#sY<~>H` &!1wS{j%wM&/ۭܞw:৻]S: 4rv.#7Š 6C9oF-zg fؐq$Ɉ3E0[Ȫ4yD A05pݏ&کo{vJRYޓǦ8MBǸ#vĵ-4u-W7EZSdti@ ~@9G&(@ E+`Ugvjv%f+j*)";M@|=7 P9{yzja mn[Pϗ&˘h%MEX8[OBpbx,lJN{[ӻ76>$8ϱ3NX;U[*"#@M=$@@! !%aHHpDQGiժHeQos{\[ZAkO5:z٠kg`x) L"5;;څ(5hUw܅U/?a5gIiBxUW~ƃC[kn +=Z'plX/\c0v+_G;pж?$ttKEE>Qe`*mmw;@@ֈp -@ ۃ-:YE],ܐ<>q[T:fS ؒv$}X {]g0pƶszp -Y X<>)(m!Ukd\Sm(5|7{p  bR3F^GЊVkv2FP-b$e!RQL\#P? / $Đ?CaC j~^ťd+XRëKYp~bx7fyHluƴX儏lPm#b o4Đ !P\ C1OXKN^!dQqEDV05//ºPqtQ;$W6 #Đ5dhAY;Be(Ƽ'EWri R =)Zu0;.ĒRPB?'ڨ*S E1"~6,u߷Y庺/lJ|ք%VTOӈ-T8-[ܝT$JfJ;q\i+ cDʆ uA`[gg6v%q |W5Ɉo$wud򯷤8鍲dƵ :z (1"b͝ Fc&8o?qBDUq艝r +;{."ɪWdd"[O (GUhFCZ-N5[vry70P2%M1͢ڵQz.i4%u#;5HjR dPOmگE6 ^p4M`S9f Qra֍<USXը )e*b}ni jOPv+}6&/NO]]N 2D,oGe$^*IF!LVN]-lPY\15ӻ{U␵[Wf<2qP9 91W̤ #G,W+&qlWlP_CVM:;?kreyq#(shz8VՓKx99\6̖19aee[7  +b`j| :;: ;lJYۏe]f^>1F05⁅-|6g]q< iR*j2 c2&3rS,@-j=!=X󏎯4.L/t0sT ē8ԜoZ,26$w63=O#lv5t%wծY6`K1`!A`.h?/@b!,<6NQ GUB{2bhx9BehW6lD'&p, ;X:=8ق-xۀrV⦪:ԋa +lژ[4@kW؏CϦpL,mล[YX8[w%/}Jh͐vpDkCU)2O@Zb$M8Z`YSI\'-a.bEs)z:K} UwmHW6dևb !l|f$C"WDZ-,b؛yoA0~{{!T+7Іܣ{nuΦ@ a3$&KB k.p6x)s|otuOѷc#%wBGJ 4͵l244"ou`DG-&ffљٜҙ ӉӉ]oOcxUO*9Ro ?t4hLtR8GmQ<,n6@.pl*+~ռ.MՍE+oG(.D D o eYgx[RGmT7-JHaH97xF \qB4ID4-{Q ؛UlXeU+kb?;v;w!"r:UJyM<˦2ư+ՒߒDєΖ -])W|%n^p] +`~ylPfxG_>#ޗޔP& +qrNhM|WzW.N^OkmDy(EX4Xiv( Vu^ӵo1IǜY5|/+tt!MK)b>_ +`) 4#mJPcSTCHQT E]94i;᜼Pْ%7g2O9?\-nR))'tבZymti 8YPl`jP.iLgQhg0jT2&!ߩM(*W,b[-'xd^_$+8+c::.*j`(zH.i/4yThDvOMjUk9AnbJ~L) +hW+NJ\o ,eCFiȏPos^l{`OgObﴣIq^NW k.f +X4#xQLr`&'ѡ +(&Bs˝L^ x8<ᏺNiaNN8mxmVlʊj;DŽ=cqߌ+5dC_TRʆMϣo]mTʸkEI729=ބB^_|Q}oT;Yљm !h!7fmạ-3VƂ.C}A;[/*՜SnK%uGeF )mm knDC̗ xߠFyUmm{8N.z^ fy ܆Q1=!էzk.todV4N +DhJጢ.*o\l`} !qQV}K^9z|JڙZ/'CCR;XJYL~ F]k+I(\BDV +p'6o_K 21n){AҜ>ƥ[,>=ё,jjnNkɧ]h%EQ$#2Y X+IV|1qx`o֍S E 2\9#g<똃!׼|pehB}c\Q{uo-+^[s_٦M9N8" ~kN}+Yg풾VgcEYIa 㙳3nosqyoSsؿ;{n>[}-_7~Kz/N;Ώ$VUdj#g&F0c-sIvs$۹$Dx0p+bi ҽbοkZUŏ2<(J:4C< 0QW;`dLY ^a_ #VV R)FN" ~AzԴc}-I_a6BfĀ96N0pVP-i7c&y!j)Nxc2!B%5-Ri1vH`TA8Ba7(:@݄msK[)(&acc G#)`B1B"uHu_Q,%9;[@^5{ GLih ]#CLևYd]P:'kX B!< IQ|q !RX:a<CN +*F8vJzPԁ6t4C-u` +K-PDIqIK!|V0܃P5yDQB1mDڛ fP* в@+ 2K!i +OG(w@ [y7M>QʔC:31 h!Rq'Uwi&H!ŝx?*VBXىSOK_gg͚a eO xޣ +24p1Ι f2>0 +30b+ІJR)INYZB4$m݀X!^qTv᤮<(:`]M,VW(']& [|c'2_3~ept%[ ÍPo#A6{6?C#Z"Ӕ rZJU%/w_#\Ziy=$S.&g FՁ+_!p7Ď\=oNݭ|>~1u[[Pәln &z(jI9-)-Kz%DUO󵁨j e.m:NzhRfTq'bhbKic0j2[/JHDIaaXĐxҜif^oo6A.:@zڷ[ͷ, + % OzM†p<72ZkĊRF U^ҟZv]]L.Ek(2\5Fuh ݧv|mgGoC}]s2f)ST.\UA?[$KvK)8 :_lY dõ@7ZCk? +m#vL9sw %t]awGЄv,МܑҘq=üfuD0#rQduj(T5Huu]7wj6Lۚ(+CË)(jAWLc ==EՖh17D üUuVi\5X k-z#=b|/'&flL?nf ̬ -Rn^]j$v`$zaRfGL*j  M@J(V5P VA4?vk |з,F^d˚FERsƃ(кHe8"%D|9N='hL8d 6HWJU %zN_xV.H4Xqwyy֜.^?13p(BcҨGhjFhtF=I1˵]}0IVʵ5 :#/ȽySmقiNվv(sq-6gz,*9 +lUT+br9V\g)jgwe7i@F[db; {ӵs2*o{)G/||y y$-5k9ܢ;^Z ]&| +ߣ)Z6YY>O_>~lq#1!ˮ%$ԧs.c:Hv:#H8 H[I=-2m)gw fp +N1[gwk{wgd N$:YA%`, U+s:)%ŒJ$BBQZS>13f1f u2#X"#"-*=I=.O7]y?>s>?|!(` 02 -UXeVú-?F׽y.pپ=|6vo7ps)2  $C:5f(0Yq ua`6{8:lgv.N.py.E@fk"F{@R4.BCpRgA"BPzaMw!Paw)w[C·Hk :XAV; pۀxt7 0^c LFp࿠Ө71xȗ"' c<[nDi P\l!{rVn{H ZLTPEр@i&bH;~4f2~M RLCߑ&4D! 1W^g+0@H"1L"3,&~D+cD}:/a;E1^1CGoO4bu%0s==2hL&)3|tD1Ww_\w +> +sn]}edtsc Ym +nY ea,8Cɉqb!^)x/Kצ_ģ!l/Ԁ Rp;ixHC@^kL; 8Y$fR'>pɄ&m,#Äb+|UA6kz$w1:OmK+>h4ˌvpA= NԱ=&Eq.>L +Hbs,)AP&Y+DlF.P~PJxuTKԀ1j0E,a!ĭY +Iv@d@/yGwOeHÏn75S{Ǫ<?ѠzTQ9"K9 +Jxr ',WUUW~R:*嬎|Vwi.Gú_5-A v0b5ޖ۳~D{u@{|snu$F!ۜGO c˫%ɢ3I$EMF. k29!:5RsP AhilA`j%Vپp~p~mXPG>ب184aE^|VrV\Hj8VKE@Ҽkf)Ɛml2l5}_e>ְ{`Gvݮ lnDJbS+ <*/_!jSSeԪzAگ\QNr{ Wة +k[A(7Tb2Yl䢯k^>tCl&25d]dqE2.ѱ2#C_kOk;5 ?iX.|PhU6m=҉͍(B]>:&"TN)PrɹH-Ց.4r[cNՒ2:*r}@h6F?^r_G]vnz?{8\JW'(DFȠqaoa%Bӑ6-ZNRZHqԱsJ:ՅtuU.TVy?p>_v%\Tj煮 ;N&)K+M?Yxdo#+:zZU|FuT؂*l#}6C݉ ++ݾZ[ݮzGVV;u + 9U/,CrݵO'ϪJ.I5d*]U_+5ѕ 'oG9]\ 6Q 9TC.|~J;mmjw3LK-I^vbSŞM):<62S ǥgKUwH+Ziz:bBc3ivVW y14i?9;|+ۙ%9‚zmaFMɦԦݪe>HRXܰHx?  +/^x rߡx$T"wHsVcԋ5v/ R D B?xI! CDn\yrA=6B +?񇄃>;?ʣp}* A*P8Bx6kMB!8,I&Ւosq5tT&}oeυ#g `*CD5D[́ I˭xbˁ4M8!Z/EDW(FgÒ!ɍ/1$ToDU/ѠxX  C5͍4A<-@R˱8g\,*Q1,U}UJ Қ>^YC'ݕdϓoRzR?%ޗ5ˆ j"F1җAB!+k"GWE U_ƤO> +Sˎ*W]Fv5[v;S֑T6یه[ޕM`mYH1Y&v5rc~ʒI?&{b֥uGC7}lfCȑsq1cs`f`f3r5UMzPv?=Km{|}{%G3g#6Tde6AxI\셽D-c:W(  vn[ux+hgi=o9!+_0(<1 dOyX6o41# nyW.c(s8$l]6 -,] ݎ/r^aB6GLD>GcH"Ueb89` 'Yi +1Gm_jlZfkǶvUSoAYx1&ez; |NWӑ'%Fs& 9Ic ʹ\=vk=pO&a%RjCέ,b˘Yjz:d9a)D@!s)gLAƁlg +L`Ǫ#f']lnw|}>ȣK& U|t "znJa()5Y9U @#T4̧%@Zm),73lL}aw.ךpdQ!BQ%6!0I2<-6=LIRZT^":,ESF>o06 o1H4|9g +(_.:/:1_^<{'g8b;!|7-`27 '0JaBy{ps73ү.y-4=߅:Jzt[Յ:G +:wN6w'o"|]>\r +[r OR`,k99 +)[V;1sx啥mdt@CPT×&`;$8]?} +r.r3h킿G׺_zh1a>RB/On~ +rs:5+k>|YTW?sD@D@ }C' l,A NDQqߩ˸TCt,V¸pZZwQDE@73xcF{ ny(uqBwB%AT<1tXt8IpHK*NV㰑}8ez :Lw n& ޏ_m #kl +^Y&"@Gb| RO<>y([ca VZ&J.ę];A4 1\;8:dUwO6)#0(D/F\x(Rax 2QM/P&:38{ Z~%}a! f3J7\̲asppMܼ"j0|H?*b/|_wȨnPdїw.>^X Ɇb3Al63lSyps(a?\ܩXo|)QNq3< c>N%F|;${CB3 +:#ɢ$E#U 4$! h0H$u/AjH#Q`OFM5A/ ,? _W)`-"5%tAH^XwƂq Sul'uĀ  짤4pFhӜI$qҧ/lH'R<^;ң|vz$Y1`%QfC"R%՜QRk"8!]L&n'L'Ly c<$ >#dX[8 O'!w$@s#͌KvM +^H;I:M}:6}28 c?O2` F$Sim-y9AŞȈ,<9Wu* l6pəN?șJ?ΙLq| +_s? + '/E`=i +X@H6!G3=pq1!N 'k[cf_YѰhH%?Iފ$/c AtP +)&C6TTT'CB#)E6s\VHFīC⦌AC%-wɅ~ɍ7ҞWWʧAe쓢GY~W>%)ȱ dv_h2hC\&%hG+d ?dTeV(^K6U==?^Q?+镾(푿/1ߕ9sC1y5kJf +dlrU vB$ܨ}(_:WQ\R.Q>ʭ*}hXv[Ew+k;+UsΏʛGNe?ն}(=7j7y T +u^֨6F:}ZnMjpA6JsG)ίYv35zμ3  tGnln6zOVGGƧtQLfm^_9P_ɩȼS_J]-(go1?gE1Nzfˊ`!!Sܦ%sYq'\H:PZCⒺK[utZUeRZyS1Am.k.Ⱦ՜O[ng=g>+ͣnq R++QӡI|ThsH⠳L%#}52l:14Zmcֲr:YaV&+#!+#w^A<'.Ib/#U05WCZc$.vwbϵ4Sk *YM m *),vr ;? E +NoD0UB eX+W|/qKfG8#~}]Qg˸/ԥS+3KsJJ:bK:be{m%M̵`<7C0K `>—.ywóIYx4)p)1#g:|#zbRsy٭%)iuu٭̶ƶְɖІк2^0QT|/[d`W +6iaXQ#4L[ _u68qk߻v8$d02ψLojig4;z:'j:+Z6n2y$n98W;83^+)\?Y}M~ fLgV_!M>~WW$5Mce+'\=|o{GD&|M;=5OU9MX~{1}e)ӿ%|_jֻܾ7`{"\ =Bdm4SfnXQRלbV\{F{/{,G$=NNr['V%uŻ0缾xɋXv"ybVG_\"U"\|#z)\,|k|8)Y+>/\_x s~$Mkۡ@w߯۽g_^~X{`v +s?G"nW降2udrJ|41`nb飻vשO?T|pt3˺#/<=e\н0T%'P(.K 55>kfK`CA[K =QjctVY! >i3}Wn\ i|G%_<P` jF-ӳC#C +[ S79n&܂v Oaqb#26ǀ#,ppzP@tG pG*6yuMk$C4'Z$]$p˚Fd i#SK kr*[=}!( vE$]QBX>S6?G{X!ܖCZml&yB@h[kAD;N'.'?EC|A C%6 ;M Zi.PzDy5B0 xb 3\\Ҍ9'njcFCoaFBcC1_1ac#H4.!WB$OM$&YcE::ܷ}VPxku 6q 4l7_Slex!|<9@|`8@r``FDOPFHa$}&m ' Dj!~$% '_!o"ސ?G AS*=AC` +d?(v4g 큏^ +5Poq1~4vHd%;7uSꢻ(PZc^Q~}I@'.Y+Gѣ1q'oF,f@ -֐$b_aA*/!+zM_D%<,a>a>ֳKma=c=>;&n3[5K :Y(KS Z{S&]fsAf?8 ǯF384惘,ν_1۱;xbx7譼qqxWx= Ӊ '$ AHC%WZc1!7pUW&㹌{(Hʼοz9^+Ux>al~ģS3̗ۢΤcIm!xA]Ym9pM@TKAts}O1v Qvr-xr:)SK#=*M֑W>$;>.;|U֖D(i +Cw^SFfbm +9^2W n0+G{Sۓ44 "!.9͑q\ w_kWWW6˨O3e ?JbM DVs n6.p@]akBafG;&&A~V4{`>A;jg)Ujj}OiA`0EE 2@0srO5k jQ&O|mV]:#tbTѧ4_͍mf閳 v.qF_꙯] ogmӥjʦAǴLA ݐ*SJ5gj |#Cȴ & \4q~r#~$Th[xa6WRLeYBYW.W(e(fF*^K2%,}45%&jl~vʃ7n2?x#ѥm7կAUbTWr%Bqn:]+QUU:JӤKroTsU/ Y]̷9@g[Nh:iᔻG]is7=u(`Q{K}={am"_*dZIPYhUUI :ValWXY;(EJ!$T#U)ǎ aUlbY,Xб8Vڊeul˨ 2θ*` s>_=oAjfqf٭ AX:Fѳf܌VHG\,9u*LPrX}2.8S֗>`Q2rm-ӊ +6'M[1~r/}e?2 Ըw)5̘1ڒR=rE+埏O\{*q)sM[R:MBɒ%rJcKfŖRv}US~x"&XolG!CDN-~W:uoZzC>j5 6D2wSOOK=P>{YE1Yy+/:{fi乺őEgD0?aXF&[^՗fݯuwwͨȝwU6[h]oz>9hqI gTJZQfAx'מmҙeȨ '] \Ct1ԛgЭOe9OԎ`ͬ #:[S!uӂ_&?r/.~=gwp(эsDDgo=0}Oh+kNCr^yg3}4i01**qzL91Mˣ7F5l1\Rmu=,/4 dwPiuDlDf$;|Em"mR +q{2NԦibS;2t5Z͇m~h>T\GKeng`;Owv<#mb=tYgcT-Sףizu +u[-ۻ/[їտF՟'K2x\$CAwX*.U CvDV15ZrD2ļc}\ᢆL T <<. ; t Pw'W\5+WN OT(ha 1r"c \Oxܠvrdq\r1Uvb-Rye:,~!vD(L@fQ0!` +-e'x!'і;.8lXVm`X>nVT2P2e`/Fbd64L )(O 0t,܊+k;Xۀ3 +*\>Pv; L[ CfP9>r.PD(|;V +QEAyPu |9C}yeL.$E:τ3LbB+8̅sp _9}n ҆,~_偈w8SIYvOR5BR#\}6,9b>`w2')9ږ +'S!@| }5+f}Y;m7aعI햊HR{9b9vfj7+#ɶ!vTJ3LD8V-34sgR/4] y>P9yc󾠻y1ew f$쑤iDuiyb*aQx:kz7a=RR\ +Ev-\o^ <>{.ZdCf!#,Fdwf +,=E$A£g^rlSN*ݮU*%RY*ɴH +fMS iKGk kYP/NwA.2x@CsQ xc T/#unkC9Wan1'E;Lj}:T+Y2|Fcreymv%G'?_(4W*|J){'tRSe6TAA1dd/4RkD9%qgy:`Z;`|;–tqZI匨Ē,B-ϒi5F&$iLS&v 5":D3dN]I>>Pޘix\=&Op[߲}V}صMkkhᶊdh,FY $:!ØsYiK67 ϳXLVFKxX-n`wnh|pUCa{Z˯fӲRGxAH)TyfK\k`-}94H6R8Z0<`&3Geܳp8c!sgЀȕ5-ͤc4l#sjDV!P&:zYvv͒`Q4>5b$Z1NIַ"W x,XxP0=/ݯ>]:gvu-ub7ZNBmHm #Nv LOBk))Y*rEEr*H6'?:"!:&$4T3%;vNp/p?S߷ͷgQkMgcv;)1V;Mk㦓Z%V0,s tᝓ|G6'+0`pA#\_^*lZiʬ1޸ 8ڹ]QMiѩCBBH I,@a ""KtXc[[;j設N]c((:V*(ygI?]b.&S l Zϩ , dqxWC^Mdg Zm !*q2>N1<gtsqCKC+_5ûeRHD=FzZB@ȆS|x Yx~{+A7 $\3#bE:"40Kb*Q"G*r,ɰB(Z_I/A#Gf4' Q̹IHc2/ˁo:6CQCS!&L0ZDH ᅡ<f>L&2QC3fB>>GۭToREHϤ$37@`%BB0$0EPZf( 3ꇲ_TOx+BoӳC_~ %>Q2J=ăLԀLV0_ L!0Mg78੐OBtxER AjA6П`To  9Qrb4 + q##BD9} + <ȶp!UkؐeCq6&o1ǀ1i3:y`A%@# .,&1Li0+_Q0.UbZ-6}99r0qIe~iCe}KPcteN2Db\J. H`͉~j3l}bY3`YȺJWFm{;}}^!ݔfeOJNm-COSy2oHa"`xՅm83)/KYu;u+uvfi;tҪ7r6;[ Ο tm#Kn/s>Jo5#baJ!(ְG +Eez=L7_OZx͵*ӵ&JFsG6s{ns>nyܒyr&פS# ͹04BאGS zpo0EfΎ ퟕ-Ko䨯$tfWX۳[\Zhq6{L&ǩ펓9UZGcnsj}ywGm|0NG 14._0/2&I'd2^y&Wyft{tr\ggQFgYFgDcGmq]7mx恂Kw28b$-5$~SP7/L+^O|br¸p~!m=M4sDqEƑ9uKr.ϫ)\W]]ї}E_{WyFMDg":vFcd[Tgdk7QÑMя + :3 Q@< 3 R3^Lb*I^LU#)>*"\cot[J72MFVYzvkiv_t-{(=]yŨ-Q1TC C?΁V +SheR5[ swi>e05='撚"ڙӼv Wͩs\=w[sOqu ~(⣰B>"--f5<_F#Wi=7^7-ܩ= +UB)\3% A$)7#|H7_f~:ev+%nk{ msCs"OԤG%s(EV.dK I,M/OTUFy\!'H%c%DD6$)MsYK>~*1rS +z{㫻Nmo) +9XGqT3uܔ,H * qDy\BW;"uP>'W&Dq CP2$O*#V\pFMpvYo핾֍}d|OI2Rb*LT(b*PSTs*JKy/|#&sc At -%tR)X%/ą*daf d@Z2*$L JqI,R$Gycçn6e-.;[Bg)^z0IưR>ZZTCjZxĚKQvp X G#V~d@9LT> p{X#V}2z|w)v?N"rh!-etPSlmPZG#NP)X ncG?@=ހ׭@7hk{"ڱIW=.폹tI F +N&JC}G}^,\@~t7V a@77] Vpw7A=IÎd߹lNm_{P[$4ߛ<_[Lo/FOϡG<^pt}+JC߆twGA5a _KM8aw2|mwИXa1Q148sD׉.  v \`=bf yG;ވf9uj* 'lzz|۔^)ݱg4cv{Nk>:4Ӿȋ_~gl0p!b^7WX^1!kYCs;afc?/~rہw[8ef6-.l065ap W:j"Ȗ}#!E($! ["HDq_jUZR9*ڊZ;(U;j]ں`U(Àsf~{: %HT1a`pDHa#OB@|9Vr#-,)Hq='?pɯ%WO +)*r01k dC +H +r桘 f*LT3PKg4F2I:#_J'ge\@kAyF;^~` `H e +drd"AC<&Odab%PzϾdRz_~c2wPTK%r&5AyAW?.i,0H?\/4OhLIrHd^r bA<iB|<1Yp z[ [& Cr4HA/RHO}uU*a|HcLAbAlBWR_B?7#BİJGb=qQbaRITMr+Ao;׍WLP]6Aq)) +z~d"G?lL+ݨ0e>6z4~FȻ呷M_D4m=6zk5WR[5^v;BZGԹ?mFhS2C Aɷx#b +߷%a]1g6aE}ǜ=9z+Kc/gTj/fTi6hϛiϙwkZtg,ͺ6KԄkǵf:8% QDzy4Xdy'eo>Q[k956' ?ZW'K895.=C٭˾xJ0o\h#)B +H;fp-vh9Ny<3Uzq0dnxc9s>3~t8gPӁܝMܣ);7FʞƆEcwC7|}5\nQw2j) v8ҭ ֯@PNZ,3#)Wz05KZ"ʐ֊ӥ-b8M:$J'ĩOSENe.D#Cy9|S;WR;Bl^uVw~k>ƪu]D%SH%99Jibv4![s!=6'I o<<xXF3IaR#]ѽf U5($(-) C'IeeQ#NiDioPd>̀zM򏜠ʄN9~9vgmmcMH51ʄ)yzjDIxI$A&僩1ahL2t>>LV^L=DYa4^v~rrsNv}qEUqKiK(Ԇи䨈I":/%ZRӐ\ӑT3T;X;T3/Y\a4_h?VLnw vS: ~F٤pǪ:/?黡3>$jL8 hN +7b1M QM}3aM!A0p9o2~. _={tl謃kK.Ct׺.AG9 ;[X<ݐ S oqͷwwػL횬5yb;6:߹it籥kKޭ%+޷(# ?MTA06m8m;1ekt:;~NYǛ]˛)5um4>{h+O|?࡯TCp@5x~D>SxYJ{z7nqo0h% "Ly~ :,q/s{E5X[ˀ~j !8tPȯbk_J͞jIOHzo%=ewC>GH|FHWIw|'nnvo4*2?..@B!BO b!Rk" 4{~|_3-XNTX bu+pտX]9hz< WoZ_ ~js1˳r/ꇣk \2$ql5_ǹ=c= +]ͳg;Ĩr ktx9ln}‡΄8F\s!Ɉi_2{& G2@Ԅ%UUV" E3B+Ntl?cXcQ|KtyZ3ROEmq?qKŞ+<5.GELx$>us)?i꿏#=SNo:Y \^ +u2׽D26^l]((.;"cΎuܟ]-M%J H kDlG "[-͂f~f`(j\T`"^2^9^A"G&@Ye(s.n*`WLrgc:Fu&xvf&C$&QIL:AW'j ˪ E#J vJJ 0*-1"0Y1.\7ѿv!/s1V B*C>[ð({lÆ7oR 0 V\PNQ*Ked'gfdg53 ӳziYCBiE$AJjĴEbB(c4?zF iBY l%fZmXYSWV"+(Hȗ效ya^$E%%ɲsblRϟ ~ [ +L6=,ưWQsͨ(sb}[,}[(J>:[CM6mgUr*Cde4('TP%M,,p + gDEw E˛;y]Ng-ںx3?ɘpv殌Ĭ4cV|cv[jbV_rb,4&eb»:a y4veP\)($+ |?nsQنU{RBNȘ<9)TcNVjBήr̋=67.iN܎>c\7,R{(WK;h!Pp؅_P"`YW$'K6o˜e  +g2*,-)l)l)苊cORG6"}A]U_VQ-5vƇY=Y*|ue#qI)_LI*O+[:3l]TLYVTtٮȨQ3χGO, <0Y!c; MTaG*5OiS'(8RxlaVMjPT5!37̨ ^S4ؤj ӎ«+񿸑E~%e@ ]z28M~ןe`m-l~h/8w&BglriHOGgׯZwjCbІjІs! Sw>=t +=r52CȽ9g6."rhgzH[5QӬ#ÚB;7/snԲqr>I-UvZj;M}pq6ԃ Pu{e=wȼvŴ\$8-;Ə0CMApDSmE@"5Zl_GڷJ/ iUx^<F5yiiLj6Rl?R `lͅ{*Vh wRп[6ȼ=s=dnJl>,<Gf,DsHR }%e 06@}"Ṛx:2nbǗA%PBׅp_3 w#O8C_A=hH/f" r,0+NءK`4(1D((!s`(0H4&ʈ(Kȿ)U0ep} `?,kAU Ą補! -Fnb*T-#67+QD +.*xmP"+rt)*Rm!lcv |D5YuD̐m"~ xFoQ?YZ{%S*POg W"?A4rVHQ"4c[(D^ȯ8s\dZ˿F^3y͌rwAheCO[:z5*C(UPYbPA~!˅8"@1Ugy/F?qշC3-ɯTm*y*H3h12P52~&EmQ]7{E#0VVGO/l ~?]?utG7!P5!FrtVnjt Ԣc퍚FV(^m"t!}/p*?u*?q=vfz71\/1]ۄݮ]»Ln&=o +tW[.E_ldDB͇=b_hܗ{SylV<.[~߻H}@S!S-uIiQzG*EoߓvLodW}Qv<tUQ/Ɖ1QA^W~-z_ بcآmءXxP>?diPgīj99}'nb@8DH8D"7"hPK]A-ꈺVP+:uwN;ڭgvߤ/>|3tg??>g/)-LR$Cg~;7$M A7$|,YU+2!pD<pp4pt:p<x<x|'pdͥ B(luzow4_žkމyCkkFcst"5{]>hV|V|||r>2p|ʘ ̘ ĸ:X|:|rβI1= )`-C+Tnr;No2׮'m\yjuvއsҰ˜Y5OGLFL#F Cw9'\F^h6gj?8s*w-|Y$ (=/4Dq܄ wZԉGND;DS'E1# 1ӿJ{F""0 Uϵ.+;x< vYx]Ӑ|gUi8|Jĝƴ>ށO8&`Xk֓8 %`؅>l>Ɇ{'vK.)BuҁLjo!s+XwvE8KaX,zDIRҔ~YUj>&:GevBA萝#ˮ[eI-ffLD5)`3A\2&K?Ki % +c: 7Q%sRU.ܡ4)(JҤZFeEyfV>UHLڐ $g {A14yB+́Hs֟*sC +{ml UּfUWu iVw2YS:Evzmm#ʹ?d@p% @pyo5/:aLX8)LPo(Hߢ$X9sv`V.[3eY榠\DXm~Gȁ(5<-`yZ!.nwyH۫XۏVZ˰F2PRcUy +m\{$T-.юsBuq~JFAܟEy9E6rNԃGȹ7!ALZ&̡1xVl7w943>U^P (/X":cݤ4K7'IO.StJjOP M5z1Np܊[c?z&}O}4RE*7hXEy¼b,[_)TL}\?-W/d2ywU1fC3P +>CwͿ҄2hFFZ@fwjajF뱸A_VUbJA./UH˛C32 RaI"XM* +ȕT@3?C]Ps?vp1l ^Mm-m5G+Ÿ,YwPEeq5cDl4IӍG$"S/&2tiQ$0= M9Bd9h'GF9L0\mn¦.nhY裂IB%Q٨a`<\*M"*[l|e˳pE5q͐mgVѻgEtK|r~:ׁcA2^?]el)c( r3U]rCMm%Lni286:}jIc/m$fk"R z>C]Dwp";5ky ']@c+uV,?A\8LqC2"XQ&g"n$2Vޛ°$})ַO}O8j"|'G;0c(ԟA7 QI9g>Smq1q$gTcf8::CQFGFgG>"9V#I'DzЊ2@_Dώ.2jL{s7l!!@Bʎ([ViGNksU;u +UC@\PY QW*ZAyO99Ϲ'y~~r?/XFgyNO1Q'L03S+byT)e6c3;`=sses%9;dsysMPgaչ?`J*mK_iux^eu@*Jr0j)1ɘDը**wRU1zwB^q5[uCj*<Wqjw930*r|5Wd/2ZiKS<{ F5 1H!$5b34D4@^@οLr S 1Y}'iyFiH,2(',gzy_&5Vw|zD!X89 9 rGI ;X@CtxE@/>f>z!wApQP)Sd %D drS 6Df( Q =jF(ƒj '# ,${b(#*)NH\_.^$OD/ fbHQ!Pr2ٔcXB9VQD>e($~$)q!i>h'G'CgyԒݛ0()GhajdTL.S_Pycr8l"}\TgzLtON%>! C== "&R765*)Q3]P>G֧X(}\*T{U|G,䞉{nmT{<ў<ҶJv0wz%nvG'roiOF?w5h>CD4ikn y,.|Y'Ba{{+߸X3};>MlMwݯbB Kŷ@?Th+1LT`AAjD}A5Oǫ:|^\Kem-͐epR+4[K.>6B4qE`Za2F.a&0uwd(|x7]M[UK둳W*oZ~)zbw 1b)ڭyPqřz({OձX_*E՛`?u$VT9#xL5JbTmC4k&6&$MP;)R8gO7 5v|H3~p|ٱ |#9Gu\8qTiTgoX( , +B aIB[ D’Bl ;"QhѺDbX8n9gTڙ)N[[7~yyw[:]I'TD4Xsiطdعr .I},Rm L>-s(5k=)E>Au@!G#w ȝaJE'8&l< jI%9_s +)18vNdǾm9+lIyQ+$ρtbrwZ~`g2C +nօ [BZf>jp4Ax&T+>+.4"T~Mx . +|)TiLA)ߟ^7 ΢eIBZ2 B22µ 4MF6c:c$*TDeƵHUHUM$PS\ s ;;kT\L ȎRbsOcL%/ ΡjeQqD"RTFWv3v0JER 8>X:Z&”D؅bʰk0=epr["̦ة亶%4ȅZYu$^+.JU1 +q#H[(b.YQs :*TD+b[VfPuլU:EeaFyNbY(-͗2'/9Q~?Kr%#̖Q92n&s>{Gj jz5K;j"wjqʓ}Kӂ +=(%)(DLyk|?>M~8^(:.E>O7FX@0 +HS]9T AG״7:(Vtz ˩VQ裬L+2vY%9iJe\bg@'*OJ& %/bKޱIJ"ToNzx3/.cat5̦Jq)O,%5TQUvR*&ԼxU#/NˉS'bx,9#*f%M.\C:ps`ų{)uu]!*wEٗk6J[d7 “xMQxF&WhFqt9c-^c x'6zl0P7E*룭(tp]r6w%wd¸텴vn ,D0Kw;<6Oa.-Df>3fp "'0={U5daw(fQL6ee[dt?N.9SQ} F/7rKds>>={`w +~'y CQg"I-EmI#5 lЃ:P{F=z&~=\?~k;nA} p.b![@vcXOm k}'WpN0S!y-͐> [j([jЬ:ׄ Vn;26H>ȘŘ٨':[ی'Vo^xٖs+|.~}5uFi;{p +MU^FU7I6S xӌ3k:˒ >Z MuyG=V\u d'`O ,aC{p\y\QHG=>I'yOrzZ `p=߃ݓ 3SG)~ }w +@5SA6;fּZNm38HK}K%ټ!-,R:c# =x7':N̻з}![l!l +9`-8,֒=L @=?*@ʖ𨝬@'/bGM'H*`ٞRK!)AB! x#Ne#|B(ddn"nRK'C#|yOSU<nT7*F#DGH:ҩTlaYBed5YOgL(y~ ܃#흼.h%p%E0ՠ^|IJ5R/TG>PD%GX| +ʭ픹yKpmT3zJ~!ONІhk/A%X!7J~ bՐS )`e0L;/-𜩆62'O +-7pLRtZJ2[1:Vh.F8'ɼ7t+D Lv$TZj2OG +桴i k1e4=[FGd$ | H%&W^!)F`{蕳VdFs9<}k'VK1ru F|;|vvipod껵z/{"'rϓs_C(FX|)a=w> +c/gkwIFߙ9qnpWrWpTq^ +<x{>L=ɠcA p +v1xhR^2N['%8Xp70F}aтkYa‹a φ/((X/:UtTOT8*>">-ޯxjO^GH";; pʏƳwjaZ]YMQQ}{ mNζ>j]c}H@bژ256d7fnAj9۝Fv[ToThWBM@<)ce;/HA\VJ%PoR?.{y;;Ŏ+d[5͚*>& Nh8Ӵ;ՠl?+`E=Kh3РNyu/$$9Lu{B˖LתI 3\7&̕.-Ӗj7VkW%\q_^}LQ^E-P li'Wg3pjGYJR;lR9`zH +ϵuY^+uVy{/Uxy/MYxgq⏾Eϼ>xЃt#PE=^z\&iLv#-b6.k IL+,etR}RTbE  +U O[ֿZyzuxJ=hN;hk{K>H=m)aT6kWx1,0GabÌE=V66T2 a6lQ4ûc '~>>E;'e_WL13hHÎtL]UteFV2AaA9w<9Y3ӍƊ\IQף?Gf߄eŞGg-4f@;߿)ڷh贈tW6ga}VN^VjO!Asɡ3DL3eDN1l{i^Sq,V8erL21#H( 6i4fMq[66t9"YvcpO5;82,tȑcz7g)3͹>>c+c2WŎ6ZFhJ +@:4P.wcղ.W+sͼ }d&zLHf 9vt2-%Oeb|ez@=R6[6[YΪZnd=܂HTC=\{Xǿ{ڵ*2)R)$]uHiJdKmM)#HrefJ3gʐNf$saϳ]ou:k!]l^]h.C%Yʂy*̨͉?gVD3RRB>IJL^6!8dMMau䫣S:ƥ "R[p}5,}(6Xg|GyfZf-=R3&xM3?qiqiť},,6m㨱{CcOD_ I?&M<~_4y}(axsY}PT.+a8 ,#?6-7oJv$fMI7-CujyљQWQoR9z^C@+v.LCsm@g5Ky/4|.-p ,(g*KTV)QI %DQ̭D0<,K>L5TP ΍T5бGUze]m]Uf9jWUٰCwc[bw*e x 啴fj L} DbT-B\0SW# VxՎ6ZoY;ģv,unu ]kw =n0R8F+?Ǿn-,S}H&j:(0k?lG#$d.(=g]nI7[˓:K?mKz%v'#!Fz~-p;8vH*z<8 ̤wq 8 8 A +6DfGX7ê-a0o$(/΅B(ZVðe7- ϠN@ucݷsܕtZ7;x4.̀% +`|C +[FݲV?n<@.7»۸}GS-zֻGJ?sg |kLz^ xdEbw6靷Tӿc_^НqJ@y/Jum^N/3sbg7ϑK_p O ߲{1f͓9#p瘝v?f>$u'w&;Ă8/ L)F+ּED_HP`@@L`T`D@E"fi+ G:t J?R{1;Л98*`UOw0~ dhw%NٟI'*aL005R #!g7sP180Y3%ϑIoEt-GؕZo~IC3pwf~{&\a$ +aT3;CaP 1 =NL

  • UBO9+-ng\5I#%=Vm\@%γX&c!9ka02{\[;ngf~&q&I{TQqS"\Ur% l;Zkp-dلַ8m%9i'i7{tF5ueq\H!򰠼IDH <HH $ \LH0;1;"*TԂJe`0ejkGl5:vf:egvZl?ʇ:~sw7BPID= ͍ןGk差WnYC=zi@yѧޭOvۧ{[n@V)Ku:B}-^X.^ 6APHYl %{AxBem_bi nyr-t#t=EZf$-1HטEIU,22yJ|-Y?Z !g,zzVЫ(qwYL*v7$m&Z WY/EZ/FZ_^losmso39ϙN۞^.Nsn=ܗvǸo즸$; ,HV4oR?rѝh/cy16$~1bgcg='cDž' w.:;Mv4*iX@qhYG0 t?"ZKpCK1vN$v8'Ju}H|BT|Llp97p\Fœ;Fgw w Ww}}"-. "2Z(/Aw)hA`q>%Tp29y*I$m\s{WR>"t%.CC%cf)^ɊWsN3zK$!6 BV<'We8t4IVG\FSS݇RpYwLcɪ|{d2_ϯC6.;F1f)mkV]Z)IoF x7J @{}wJ S\q.d٢:fF2ғ͊=>=iJJW!/Mڀ6yK@3Y>(? W['j*9Ae@>7xs\aN@9A8}DTv<֖hIћE:E{p\cV*N3 yV㐒= +)Q *Qa(@ `AdBt}PM廢|`^Y'pڗӤy{uAոYr]BDX>~1\G?2sq"('j,Eu>e] l9xh/bo.ok<ɩnbrBUEʈ|ecdShSlyF{n!l`iTsrȅ}9ޫ}K59as;C +-!(ZN}A{u^_NA/*YtzVS1F5&JSj25<\K|;'Cs8!@ϠA~Rqݫ:X*;W:-*96cMnWCԧ0-@3ypu~FNk"ߣx)ϣSt/8"9D_(@hFн܄-ේo +u~#kVQ%v)HԗiҌb/rGj&C'ndb%T_es3_C ށ<PPA0jvek?>uE7Qq^J׳vP"e꧃1uZ.+NCx}s/BU620}o8Yߚ%r;%i jI(61DrFg5 M4i"0܏ڏJP[~3x55%3FCꆵ~:# e,UVmC ۓ*<*Xs\cn᛻OGy=|ύܕ=p"<6 yw +yvL#tx|P {=E{'swsowK Z8S$^Y~=V*˪u̳1'f}N~W_NWQ>d߅B`BڀEbO *(q\ǥwE6=6B>6Qo}n-reFۊt] k] +j:|ʿ'\# WK%kībJ^U,^^eE\e'twW{T]I(NTOTyr=M`/P٫R*oB+Xo9e +`.}SJUj~stD;G4B&8,R# A9;X_G.[h2~Kjd7<\@tAbw{I 7;t hpqB sd(( 9|$`j%U\rzk +$;k@zOo~ `8ShwaD!B9l /_w {tcwFA? F}K: <<8opɏMq8N.}_StO{,k$5whwnt. J%AseOQ +s׽ d>#ȚYsfZ]T\wH~"%w} x CE8ڈ/-4@0QHP! 3T2, )$!kQG؊px3L*g&{  9C[Ѝ9aH>'1Aițc!)tѱ? +Tp{krv0+t7*OPү߃}d̡RItCx0 :XLr\JzYGG!c*\ڛp8'1b_yg!tZ\ZjJHCHw15Q>g,nϹ-p{':QʸvzD41#aळx'TW- /Yx(tR$;1tG4gqZ1 qRtCrr4kШއ͗ا=nwQpxҫd "D觸&]sE]_4i81G>aLd7 Cbag@5vA] };RU*b xCZ#%n+h ǩ8зmg>fKuHJ5iҶ5RuxTQ"UFTJTqHQyA)$\)d[P"^"X$^$$4xh4J_D%( Uu6VY*z\3]3GY(oIˌ+ԸAUlܬ*Q66~Ώ%(49$;%_Yؗc 4cT]=:+jLq\{֔z_S?QS(~0~vivi6ߔ]gӮ5rL[u٦5S뮫[[3Vi>+,|R- |YX2}X-e~,sEy;G|I+{pu7xxyg7uؘ¤7uYCy<'mpCu2븀 . \`MoMg c-m3ۺ߬3C2j ;K@X H%l {XKTAEE +PG2괂ӪxslSO3N0<' {kWq&2N56?cuWYLSaPfEzNq}OjSwԥ#9mKrfQ{ΣM*lNٔMc׋8YNWGvqn:1CUYsmie\΢aa;-&9%nmi9-bIҊ5^bwXFܳJ<Ոp+g|JSRV*a/"g1 y(D3'c-X->E鶼V[vBfi63S!q5r^ַB[&SIa~䊿B2|WH y<<@ ܁s3'ڌIp!%hW'wEX6%8˓ݪs9ܲ|_T/jҭA +i_P`\z"8Gz)8[ypy`-?[E Go!Uf`ⱻ̒zݨHWfޢn(.HrUyR"*zAL'ȒmHe Mv< N H1|=j[uȃyh$:oخ1NmZSmEUuY]J,I,,s + +RAF~MXz~[XZ~OXb04E10CO g9z S-5Ўu7 tZM 5U16*MCae{nywviD(V*)%U$e`r_P9JP +W~__/;ϗm}3D`=#ځ|K&kjh&*mԲuI5b*'jMP9(AoLjn6|SÍ)śU=At 硓kykovhT&[k"t44fp6iem/A٠ݻ*F{;Z{Ɏ>\WYǰ#k"seE- =D-D.#RuSq)YKӷ/O"rnNwxlcth]gcn:QH9k;Eyu+¸.rg63AcG==;#c~RQV/+/D3"iG҄屽ѽYz "{*hv8Dۯ9"]Xa +_مt2+;E>Ely$cD[@,sЈC+(eCICp(}V#2mmlBl[C, 8bwjI,wl,cyfPោΣ}0`ī1>ǍZP̨#EzSh +btqh`DhJgiP~GQނ琟ޟxpWmd0bFJeNO <0+cE'A wU$R"JÈDSD~07&g-9CZaXO dkȠe2Ta3Y'd2}͑d2L&s bp 1 }mvuNy D9c"ә%Ěq \ijgQ($6s:׸&=w?pj,5\$}Hu9h  2Egfh>mu% ͠K%zCQŗ>^-p +1?}%w3›m"?Y}7'zhfĝ#)gg(g(gܳGi{=O><89K 9,IY4 +hKj:zAzCoz}HN#5Wk 47=[xgB/:9(F5oi-kV'zx,(cv-d9ʇ/0 9ƒ57&KXм&ނX>qYK5a^3w$D.Blj%!&#Gt +:k2F'}\L0GmS1?B9/_`5qXgb^` ;SKzv(G7(7Ri,.kE}lBg,7GVtjE'qq:j;IGlШWt^02o`];1/p=qっǞGw- f#IE4ᢦt@MtңtLPOG=::IzCAｗz ϟie9;փq=țAtW-!v>]x҄ :?NF1aJaF3~QWT͌b>Y 3B̠xrsz,o57!A\}t`::=w}3=3g-휕vHyvjVI OѬWkE2dy٧uIN(gAļM׃uSW/#kJ$zŸR;:4ן͝l(,ʼ?Lk-L 3{r=aEaM:.iFziE߲M:bN:f*j޵Z#}lں!?q~; +W0ۋ11Ϩ̂.򦝋s皿/[Ȣ6;e)2Md&+Y'im5ۮmm5ʆVˎحMn;ʾvh_wڟb;2}G;i{E1ۼ+rՆVyCJ$ojNsTF8kn1{1됃Y>=xA>6SK5ɴ*<(WSZ7h ˵&a,(E[׶'j{D ]xQQvR ϧX-~S|uS9r yi5rJF!SmxW<̢(5Δ钩W &$uiAlNW,Ոcukt1!ZwX$V>Qt0: S:\3F'1sF w k>ۑs<{(=sSB,CSzR`mrX/U+BɝKwD&_YWђo_ #l`d:\Bh?~}D둏UGU {SQ˛meo>%;5!S1TCRCXaX!44,1lEѠ "pÿ_/gj4b?RZE-a?ui) +J)42KgK)E N*ug)1 27]k +rLNp49 G *ej0.5CD0  b* y,SAvt5P#wUk/ϙ~=|3)9{b+.sBJGliULu-}FDU9Yvn~#BPswz:[x0?s}zv41+,aD)S3_˘r\2etǨ쑑Ͷ'mƦ_S ].dh:՜FW[\ @g ۣ%|F H^Ř[&XGkg)"oڄkڌjcY/i[j+B-7m&To-Zg/ pspo=@i .!B$3+E\䄉E>P,+Eƙ-bVhR8O[l[e4W붚~&߂22m?xo7E4'tf@s!a'PP4~N.~%S.ˣ%哤~hlm(r~S/qח +Υy=_P*E̱{Pͳq$YM!l͢j5۳Q48 7C\ Qp1La:iX: lr:XG!sòJC73z(#w/k@Rdzk6>̀s+0hFaj8ӝKڏG yZ0S $ş:V|ID_+~}NjYnNza=aw[^Oo +]@tzc!gOe@Rðㅘ[m/wY8/CY7}>&ǢDzoc^:'Ή7Ћ7| @.76#S ExaNE"Eag&†] @;*AǑidYDTI6|R@ xJ` V1X12$9я)lZ>:c=wq?4+_,#L[/@/c0c 182o>CD< ӵ>2rɣcn]chTq] 5:aF c a CTf3t%ӵutlcnrNnpN92߰_W 9nStm:k`l~8Fϼ忘-XCzYܖqsr :\tY/Єqg85N24~J:I0̟ro\= f~tNcNJg).`%KYӳ\zSDG)ǯl@;rU`$_<~)ɹ̹$`5#XxH%T B{BY@P! $| KvTH +{%6v6U]Y_M󐯺[_a3~G1h rE]ZTKs5}q$3$$*p$H p$r 3J(Z +U[vnw1n;q:|Cb朴yPZ˜60{SN椬咍eXdYc3Uaُ<eg> ^{b 8B? DKLz-Y@ a9+Og k\^On7zۼASWz)}z|w}O:_/I~ɳ^˲=6rr<-33qt{Z2wXY;,PV+w*mϿS9Ʊ+g8{9ʥV孀f_MFۘh1GEh9nz[1t\Y[]ٙYZ^ߢ16kLAMKp9^[3 h͙j[a&̓JVW@N z]sDŽE9 70z +X|w>cix9,Vk Va'ܤ iOJW%E߁e@*G o<{^ٍy 32YH=(lh+Nj.L/YA|ADX7q&1"EHDdrdH7KNXs@*E7Z3(bB\C"j]\.+M5fp*tbCPY`h7tD ha*:pJ>hw9x{#`NՉ6X`׌ElGSݵѥUvj9)d{/^K۸2{wԾ#a?o m|ĶV9\G$]m33b2&ez026R`#u0LLrjy>RgO'u`;psm֦b6`ov{w}Vy׎y/&?O_!}|'\L4!ĉM$w)mw[]XWkj`ntuzl]5~v][ 1c`F_xFa7k0pF͢a>L4 :1D% (96m 9 mL5" \C&Zl$IN |x^8?`E 1x)5X{#gבsDB..3c9F"q@MN ,_nxK(%L|L'X|5'hAc4h\"e%6Av(-k0י9 +m !YA7q`a 70Æk\B(&/b-@i3u2xsB$EĻCp +6oАߗ4F{a-&6~q^ tZhCSdh%/e7 Yx4?H !% ", +qAPUq츔:h:Q8uZe7 =?w}D/ +޿c8+FNκGN.]Ht%.' l@7&בk%pwuwm%Mf ,Ò}nҧtQW +2F/s,83!B1;:/3 K O>}6a.FVbx 9ڎ |W08F +wOsΎȫp2p +VGs0xi+Oh'V :oH +g0 5rF?9 +s Bጆ/ ɀ'bT[9<̃xڑp³X-+ V;[^s!Ruj8LpYϔO><%̄ +W/oD'\=p-ُom}<c0k8C1 Ml`W=ozI4Ci]PJ[fj&amz.Z縆j=Z|z\P+rcX>KlŖ4cJl /rUрGmigmJOsiw!Π5 +Z-^Y#Rl)u{KwR!T:|Q%)YVh6hQ3>5Y Htds9m%Yjns`wa`+wArnCP>ho~>^m׼炪@VP9̜k8VN?Cµ# w;e Le&pBxTQVߢT6UQUWTZu`I0W)R:T7;TfOgo +OE3Tr$щXA0`ס5ɊŴD3is[4/Ԅ;4hu6* U犪DsEjYFrMcǩTѩD۹XsԹPsC\y,~X;vCPnOFn^cn%Q[&4DL׆G:VjNYTrm TqvD[RRȥ@嚯]alU,W07\u4~8u`C? 9@]Mϣzo˩*u +gE;EK1Z +|=)ejrm,Z`K qLvMFKqޱ<ƒ᣷LU,3%ciQNNHW'.K>#( Mz!Ib!,BœZVl|^T*Zv%/ǝrrFRF`QBfؔs7zmIHM1ٖ*jEXz<4\{Teǿ r%njP IZQAaDKɠDR*ʬLUw;Y[ڳіi(?g y=m N4~ H% uLG-=z}AK]˰ahd 6i5YDMr477Dԃq.sə9㱻|gM1?){nls`zvAx64sTA)^d}/&>zcP`䟐?A  =)l[ >_H]2 z @s +#toaafASO1ݙ?gBqy~y~)yK|+ޑ'1wB~W|iS\eǯ{u ]q'-UR\u2b8TӊGjjqaT,X3%YJ<`3[yY*{r.z8qԟ{,txF8LNJaźV XÆ*fVJijLSJ54@K)4F)wJ]S⬳cXk1ƺ8Z6Z6Z:ºe]"V2DhVc2SF/TӏR&f%]]sM76lcTmmehmnc3Dr CmE0jVjHe*(`/\k)aXpqz?XfXM#kfKa4C|v/ۃjT=Vd')>C5Ⱦ@򱯐iz m{M6.P{zws;̶&Eje6ߌ{$(Iޭ&yɣ%R2&˵Nbs-4Z3D2M e#p! o w-mR !3@P*0f[Gro7"bp\NoiWhlmlv>we&6bhU]vofm^i9ZvHЄ}R3Rd%"]~6!.Ciѷ/`=\/Ӱ_>'"'};9d `s x `Q/\tIpéӠ.}B-CqGtg?v7lJ"p0SXc$2p6КvcOh- +t9ctW^Go_1|'#\rA%œ5|2h,E90(":IoQFXzMͬK/1"8D<;;@ފ|i09Gp9͆ C.9CQU +\AGݦgաNӬqS~R;=hw]>SMjqZ/8dyN!gUk +Xh_l翷SZf: S[N;@c_=oEMCFM9#Xڧd&EP +a-zt;=i-En1tpX]N3ٍWU~S5m+'}oc sQ3ҭuū#]{LNj3= m.VU}֪n`T;pj|;UwXNj_SeChS}(Fm~+#ח9rWmj 38~T]m +QMH6.QuhևVU: kڰ,VҡWr +S? c9-l WCdꆧv4mq6De*jlQ"*Wk +T>rh&3~# V$I$ ApI!\& )jhmԶ*X^:Sgv<;;uu[na9_|=}=/wN.Q5hH3\eE4X/Y}?irz5 W8B[;̆@ h;I+i4ڛړ^O/aݬZkT[ֶAm;k v.՝.su/yBZ< q݂2"&Sڗvg)qv8z7r~nMw~^~ש>o>f_fdL؜Ga_F=#lZė|Ǎ@ *<>4.ܛϦqv步tvĘ7ZxF?l$2T +j&a=Vhq\l< j4&ϋ덷%u%'E2/ʑ*{5T5,(tLAn<$`J/Hedq,yM4ZnqZl4H΄z@f<)KY%Vo&U?M5`i ѻ۵9XͰ1 1g_Naվ,Z6JlJk55$=ڶMViU=#r &[ +c[ieF"} q:B(tTQk:Mz^CI&9U +{kWmrGXYR{/'Nv_O.r|\x,t]YhgEE~0̶_zc=l +ŽݩLn&"R%+sV(g٥".U%u*u5z_irFir `E|ޅvxl:-hRzUY*20ʼROQy6O٪x̞d2;0xߓz-Uf9GnA_F0n{1g!hQM[GuZ=U',J%V_)L2׮4L?(O'e$&ff$eT12@?7Qc~%h=6h7sۤ w**kJe6ep-P MRcCURnCCRNC();ПĤY$#pE1c.H^Da3#Mcj{[ž/lCo܎z(LCK/ .U %Pqh9C)d iY`6'?hڊ9m.RV/h 7DP< <)HkOm{{W<͖ofFĈxyz8y^\w@=F1xO氒ëNp&K6r2Vp)O7iV^j|xt^}뗬՝x[W- +FЛ^@=":E`г6AG(#tu@ilJX-gk-50kUd22A+"Ҳ t=R }CK=ez6_pOC86o݃ zJƉ11ڱz,VŴ\,V +hY*I Prl+)bQHұ$9G;$9 Dă ]<8fycؑP!01yfh2M.'d +%LjIWAf14΂ $ d@+g o+΁Hye  h|P H00I"D7`yB~.a(0@gOh`7[ +n>fw=T$Oqtaw ]n@ = ݓ=@>FG#DxN g (2@UϴαcD}!|~ǻM7niHX ]M.7 =EB:(O0*/ i 9F `,c J߉ Ŗlq]F-.]@~ tmһ_y @0czTF5`4FYIҋ{8KC8.Gt +EFt /yNB~د/,30'@1V,G|:8N!8zQHi+=FWOX}:jߴw<1ݟh[c-!a,xz,r_AErpz:WkbFvPvTz;NhD aѣ }|y[^*X#x&"څ={*s+͈eK蚍vcڋy\$u**f4:z9x@-cql`u +༂!^t ZSQuCp5i:<\œ|PC %? +fxz2h3'6q i#<4z7Sz+GG[Y.v)KmL\߸N;f?Ɓ]0%3i46hc~&9wV?3V=SJݓiFZ>y-޽ὑڼwP[xIjr}>#_^ĕ~;xrs_4fYxQM2x֏L biմ$f.LZKK}]WLm~eį5SvZ8}%->@MӷQ5/PM]x© +`9U," اP=u-Ǝ8QEC3iHZ@m)A%(fSSURCP#/.NMp?*dS&<(4'$1o^˛Gu5}q3z {`f|duϚLF-ᱜ:p!ʭ sk s܊ZnYBnQ+Q+V)(?仕_ \ʟV8pVx 9 170XQAkP.ı$JF-ӨIL(NJíRy4~**QT%bUH$.tǬb^| rU VlקxRπyĎ}Gh+zRıP-jfP&[yZA(,Ύ D"qL\[%n]^y+K˦>'oJ-RK<;84AF}3v,8V6m1O:o*O'O,\]4oV#piE&q^U'riFmYu]2n,]]nEnҝ7DvL <=wf" .ıqb_JSg"cǕVOdӥ6}̢/g苙4}%c6,`R  ۘd[L 3|h etz58qmK C<qT"t/rOIS3Ŕ,I7fMjcRLszS"4_3w(>EyBcǨͧxuy>gbq"*bLE{O)rc>+Upg )?s +92);sǖK MV8Ś*[,$Z܊kBcmPL cmC24vMeAe`t9 bxN؀ݰE[я\X n|.eN"[/e9W5:bzGHgO$3j{,_e*G4+r('Ꭻ0_Y @;Џ}50V#ĒpIJF һ8:N(֙&V9%N$(]uqG, ur>23""Q\q սU*8ʀ #2( .ȦR%BdQc +Ԙi$5165*&j=`=was}}L3n9%{vw}VSK[` x/s~*.f 0E# C##_rcqm6;28M=[B{wAsn:~kww8FW=[sϠ&eeIIR,%r4sz⦁_EX[}, , aFe12b3Y ,CgPzuK|[ w &<2$My8w*KP>KsG\Y4[$S +T򷎔u[5V>օf5_V#o5:\ۢ'd7!52 r-X 'z4"K_?|l]eWIz6TrM-F.yrі+cv  mXZ,eܑ˰Įج +Rꑟ؊"znd!Ct,(/ d(` + (|8#Kyʕ\t +@-Q-+H9~xz K(^\`+e(e(.oidno|,N?Am67™ b⊃燙GE'<o?,=@!39K; q*}r!gҌW0t3½%(Md9`8Grh?dҟ+z::sz&}KgQzm[(H@K*t` &WZ1;-C@+Qh5uuut25 ./gpMo>C+k}3X~t=y$\c'Xbc)%;:"~\PPHlx^vr9M6R>R~Ï`r#] WeT8fr_"S)t/g)IW]p=ҀFs2z<n+r8shO4L$c6=Yr*JT*ߠվo2+ORZ(%` - \AEhnPOiv%5 +gcX&]χqs>9]&F(P-9JI J4Ei)ZM*4WDܰ4C\0;|aV&*ÌCƘ8D쎭x8=jŊӺ2n;#HekY6]Є&4M($mJ i)4Ȗ*[,@Uѩɢ"2:0(BuX93z 2B0y{S,Nnb:$ь2-#Cɰ*"fb٣55栲\oVˌ(+3Uc3TŪժҬ%Y;6Q_vfFڔRkDV[cU)rdKL lEbS WUZ +K:d)UY415ܹ@QUbko}AWd=^ {s~?/blx_74Ll#:6>i  c?i*ieՄi&ԁr!i=cڛ]x6lWM 63Ð] XTnwijwxXZSA%~8쌝H"FBM`8l:MC!!: !67I "kcB!j'8-ξ _9vS?w!npޣNNb ļ|@Cyoseq81{8չuvG;up7MYaϧK3g+_<-(@2~暄q "pJ r-NW8Kx/qB)) $So}|'a交bP|$pL/0n 4n]bqs}61Mq(0UZ/+a).4=}?[*zX +\C,mA|FX ĩ>^N98MN=yd^fF ew?hdH>&qԟD\G- [21xj5qL:G!bkQ$vz;Ǚ&czwX,b@~O6cy_`})-KQ֬y\♉UNKSOzUX-06k1-NcS,QaBZt1~k 봇1c}6de ,-H{8R20ǶlYLGzLEu"ՇuQX5g1dK  (c4-N)m6{3>g3>3lO-}[b16Sq&L.a2'k1# NcMB07#IK:N~]ɿBW?љrɚAy#Na_ܴ'[,m>NSNDJFSJ`(ӗc ҽdt`eF/2ѓ9iteDF*|EЬL^&z35.~79\n{ù#V5mV2WHV4R0` 9˩DON 2N_h +m#/wb.xsBh"6덿댟Jo\M5h9K?p =M9ʑcNL:?g ].T :ItM+!cM[:Ӭ.*,//zC2} ;MSg8 4uE۸ku09n(L3c<-*ciNCـIKf1zG3nK\cT[&jiݣTZ)KzK-\Y,,̬ޡ_#59~g)"!\D--d4ٲ u6XSZ&Jj[RekV+m],v&fZ-QKUulZlD-.JWl"Krz#j/kׁ)}?WXG VFG]ejBHt:J%!;JcjЕT묕#:sܭ9JJ}%%+]CUho;=K۫ WrL*줽jT\vҕ +WP沊rr)G-vE5+USͰZޠw*y}N6_r?KY/嚚Uޠop~c!~c3W +baQɃc=eS-x仉D]$ ͟ ^MoҤWiĿ0d}*cs\Fȥv*5w0v-+ ]z[@)&$@-!ֿ1X_wDwK5aI&ܤpb#r23 _Ϝ /?VyVK!X@iH >`² *<#*@dp [ B R r?~G X/lfNld2CZ4@._K.6r56#"J@d(BFBf +!7 ]ӔcT.- %>:=Üż>o$@fS:aa60o/臙a$;I~Xr8'1N#_P +?ϵ{s}Yoz/1yہ]QQW}ஸ@Fdf%숀QDA\qjDtbpE+1ĚQQS۴6Mml&i1'<|}>~)P,.pqֹ..Z4U-\KkHpMMd bn1l!l5yvA ߮K\mt0].7sx-F[ _@ Kv mC`4phX˫wrޣl+f#?$=p|^@փEmM$Ky72?6m~8u0d4f f& F6pm'~iU|C$$oϱLexWoflŏVgq @rFR[,=Tڱ25ʽ(y Ĵ݋.M >d>"z>=Bu- x%ɏc;89%p8[E)A:v uC8 +"68Nzp +,B\/Czr?bAHM.q/\x(-𭃫Jx8,X>.g9p\C-Nw-Vsvoܦ?=].w.*3N|Qx\1D +R>p#(5-EHҫGx-ЗR.z[~D HChݧR*Od&p|) Q҅;o((HB~N e kup |oF"U_u2X&uD=D9}ǏOP?P^~⼏μ%o.H$}No?Qo |Abp&a{|v?nnn0~!MplL)We;E u~A 9i%7΃/ 01ȥĤ_^I<)" /$RyWfUṗc1XDތ^Zǥ(Y165 ycy &# +qS0R1|%Y*i2G'UW+_*eF2ޣJz,=Ȏ).tOܐdR')}/3ϰ׍jw e,->en@꥗12E%e}ejl)7AJHRAπ?ItA4e[E6֓:곀uҷiCtH ⡉R44U +2e_L(vb_.y$:yidZddސL2VH2tπSUb?Ϻ |n6r +ʚ:ud0) ÆKA@>,$ox<,A$+hd/I"cBkFդ\$|I~$; rX">ֿԁutd^Wô2)dCt*Qrha)9b&#,GI ^I __J](#?Wjw02ki Kmg%ߔ^]+|(7ҳy刡2."P2#%=(c"4I4eTx%9ʮ$^U 3UKBJMޤGQcOk1ShdpjMQN/ךuCvVO־Hh2?G>~dXI)TM$cj(S:2&S5Ej\l6&n}׬ԨjD{>U/>$'(`&!Z§%QSN2-ZII'6$Ē&lVbj9C5F,,ejeaYMjUa=ZUS-_f IEV%#hD,dŏ +jS MH|Rd3hm([( rߑKCbxԓU + A\Aŵ(-56D<Ɠjb2&1iDMNMV63eĎKt7y@l(|HJ~C_vC!!xCaqBu9r9EḷUw,.[/8I"52"]C5(&DW Nj8oh2M2IeO*1%-WhRz%5($鰂.*(㻜&t9 MD!5x.q4je16Y1)S}/5Z}R+.= e,yg#'\J|1l1m1˯f.l0Cл;Bj%oÜGj&h:ɆHOǕLlIč+,;*и +.r[N,,erA++l: +!q|ԫpmeF=l,<ԃ9=BVrRe_ť_%SɅSp*YBk!!r2xv[ǛuIj2y?( +I@v䀍EԆ6B[/ȉF,l =8z»C C=oeYx/w2۞6ѺSu,&\ E'u>[Vr v5UJf'j$E`&80Á/@*tfUd7̒Lm''(w3y{mZ[K.VYZYΐ Y?s@}pm O2<##s A+` 0t\mej= Z*=rUùb&e=OIna?o. S`0w!/oyy D-}P& -f*{wAFu-&$:r7ѓ'tw+P4wwUߡuo)qvB|R5u*4hkhNK69p :u & 2z}TUTv\v츌kcp:{@,@usoZa:qpaC'`r%§3# ).s9]٥R_S軓zI ms\~~X>SWJ +bǍp$s~-2s9{6gЪ%_ +uoӫ +G?H! SD^;9`[p(m{[mU/o0\)ر4QNh Z i-@U ok ӊmx_ 51D7S? /YӉz<S +2ήR5_X'i1] +/Us0} urO| ã4_?“OcR(>ʴ +&HlIxUD `d.ׂuaBܣ\w-\K͓;^'qZbHZH},cRs|љT *.ȡoG;YN2J=gy1_͊֕T_,\CaOF2e+óA6c ǕihSNwRkY֯X}є[blVŞ*qBwe\ihpgeqi1]yXY,gҽ5ɫI&cJjDJ:3\\{є Hbk, ;@پ7\~cT{LT&g?KEX*%*!h⃎i|PA_@]:ur+ /ك{ {Pq{/`p;b_AW0_tT3MB3Q RaHCR5<ԡ +VvX'^̈:#+ݲJJa I8c"wS/vfac| / g1-kȾ* K,ʱ*˒(G]9Gc +#5z3Hi6l+؍F\lOSLL)6Hx<)guEHltLAG9Zl3kV_٭QJ+ŚaFR\a/56ք9Fш-7lo>#v]QSx|Gk~]{*G_"QJ2jq${)-qR![UII&gyFLrRnDTYFDB#,mA洷zRzJo +J8̚s"8s125h{5)V>}g*=T1hEmd+"#ie!2g*ȱ@ uc|'4$|3o/k1tQpnmM'R+l!9X&^I9l_EdМxsRB䎕hHsi@^Wܿ;{ Ⱦ'c?<oco-YWei4Z dzRA +*P@A bW!\8B PX!WT/YF} +wTD77Gyoe&l *hAK5Ur5=K`B+AqRgp˙y8]2&W_F'f{7er,EyخhMdzi*GK!#Ġ%Zqy5H@.Sąs.ĺX*aܞ8}H}vz| 4af-cJy)-hcyOL9@! +pTqWqTQ̕l1N&%L"SH]KV-AR lHM_bd8̲L\ \ԐrQ[C԰y3=MN_TM Mez^Lݬw+^lha^@^밅S2-їBn,êyIhbo xzz.$h:6x[|YuulYFOlXM_b~rRg^= b}hf.E C"{h&4^3DR!XKuX=k3#:8QJIh +_! @O6J>Zrt,gOZ9LZE+~,#-[C G&O&i> F%-Z'(>/X8<h>ڨ6.6zd=uN.H:$8R]{ +y`'mXA bكql'';wEfOpؽIӿI;O6Ky<LX]y4`l=p{[n{oNtٮj.z8U?Ojp$;;݆w`?8v.1Q.`:Ef=P{r.Y|7?<^YM` p xLG8۬? W o8op |t|^Zp!IYY8?g ;oo|ゾƅ}Jq\a.Pt IiG xqC}\)p'q'hwi(ů0lA 5 ȫXXy/:Ul]л~ Vg%߅=(Wd &=HTa_`sdKB)|/h:EML}q.ju8eX` oT`Snzn~%#R#:6G";qTa8pJ<=ĥW;.+S;pJ[1mMeZPF bnf~K+͝ܣJjj+i;k Om‹h7P t뱇˥{VF-*6è;wigV;e ,/X`UfZa~suDZKNTUd`%Yg'>Md! rg"/3S 62^`UjְYUr1J|h /gy#71?}h2%W;!jz-NQ͒LU/YJ+Vש$Y* +'pXAG2A7@AkEW>tȮ#\ƐCaF?U"8N!* IZ7PRW+?Qer-Rn~D*G)eG^Wf#~'{ʈx9}\<`.y\Dz!x ?F{UQ%Z%OrDYe;)WtrW)'RΘz9b*+v2e7M*tR)kWrgJ6}%ksYc q_$yYC.2[Yr ;gܦpLZaiJQv|]\\ts6+%al}JL(,weS7Zn+`N3|o}u xtzXt4fJRFbhWJRlIJN.UF֍ضl۫1RRbl+kE۾T!:gܼzAzdUn~{\ Gj+ {jRRɚTSS9ͭŊOޤX{31i-˸hW +Ea' +O3Wa9LM`4H1')%dʜ,L6fg*&ۥhG"p4*٦PnRPΔPK*0{N0#OƷ1YWI;7.E͉O} +Rtn"]&E+,/GK +W +pݭ\F nS$?gۘǰvը ^piBW' $0{bߓ*?C+-['vayE,k^/܃ +7 8wn U4|b'ZR,(-*H(rU2\ʷczIXp/aJC]G#6k:#s6Me $Yi Zv;ObV555I"YQ ;Vߥ5O.wk>8@064@oໍp7%f;ߍ~dlf43liM4&Ip=ai T=:c~{wXÎ i` + s |.с/p vHFѷ8C[kmRz܈mzK,'G0I=|jҩ.4Ҽ2{xI!1EEwA|'܁"~ǂ 78?ӅCp T'Пxd}q\Jq +' +~ooĈg6D~>O^6=Dp&:>O5|V'gLp +Gq1?C0xqD` _Sc0=)dA|>Ai }[̨7~s`xa7a/GN!c2EL3)i:Ń'/COћ(WRlNS|˫WF|1Kg^e,1HDR_$3G<N,!Uzx݂UcX*\$0ۥOj]ȍ ;].˃ӫBS;ƙ}َüX!9pcbL2rga)>H{D2?f?aZ}H<"GO5 ;FJrc~O +c_,/ur `a@`F"2TDToiF-oi^G-]M4m۳g3vsMۭsZ[]O{ǵ6=?f<}W|U,FiYAx{{\a9޸ʬ^cISl?CE-t7h3 3lgw5sjT G(Pi)؟Hֻ{Mq oo W?b/ogn1?Q-^C64{>~ѫ=Z*My= N?)yUs旤l@|'~ B3DW4A]FGG..ɭP&Poc~x<ΒWqUv} +2Ct~W/dGCس>qbK_B62Y@ .Wo$N|Zu{|C&xYX#=Tv7ێ}_bkרit)rq8"w WF|Ow#ۉYڋn.tji+o|.8볍$Ũw!N/ ?S)`LK$ѫ3z YGkjbѮm*6@ }^yߘ!c?M.3#(20_ Z]]᱊b&eVlb2Mz>s>#_O6QJ,QMpƁN+8xXd>ey.g6@W3-?\5xn' +n,%8S*il2 3AaRxjkn'SIt$i7&8BUA&U',$]#BrtH(Vq*a3+e,q2"N)-o(#UT3&VpY*5ڴQFVѬe*T1^d9"3BFdVveL-.մ\)MJ6SRIc>tK0Z5g[s5{ fc22F80)YqʌRF\K5%'NSyeJ*޼W&/k qw!4[#7b +?1~i@2TfI&ghlfS%I)IJNU -9y.S\Ŧ.UtFE1S&cwLω }h B1ިȌ6msnQh R *(cg|!:Fur3w_[zjSANLƜ=DqYQJPtv"3e+^0{Bs*$UAd]eeQaaK%z?;![Z9ѳ+axK9iK=\ʩ[9Icn#Ђ +)P#OGn;WX8-b.ZBV؇8ckɿ#Ӥ{.5N \Y}XWqѸS5m%MS9ϼ䆼' 0ywe/gK(}%s{ +In=|6M5*(Yqk"'!GhL}ACK1u4UAnpf0 +aP>Nqip9DwE;,p1RҬ i.f.f&&nxbx4X6-Aqx}[s FH%& .& >QY;ڲ 3\ w18Sh)4['k&!"'-\^v(>󉒭uzx&u|.b!/#o\4hJ/}1m}E_tquq̤g2\3 =@t?"owD}acFATT((@E +V.(֋jUmlScS趱m665kjulݮiibɆ<<{}{>xsO'I*ޯ2{*~G!1/9cNc;: h /E=SOXttsuqw+Wڅ;ORx&}_ihepBl oA>'g 0 \Ѓw~r:6,&Msx3g\ 8M~Zp1B~4sy< L=ڍY [ +13 MF]Șk!:Q/H/HLS#'lc-('sٽkrw.<.%'X#%|Y&>^V?o7q?+?6p>%;-&?3EIs߱Y|F 'l!S,>bq}>`%/. W8x | d%3|1bk.< Y Oح{lSWhVﰁ-tLAAb\y`I6I\F/@WpvkwW*E-f96+9G56f-aʙ](qp)ttCzMl$'<?:#|1%ÓDvK[ح"ErJ6bhDzG%!n^'#0Qu7!c$ۈKZ~ـuxQNxxTSmUTj.]b$(2usknι᠝:mFd!6$%sEZ?֡c-QC5߬GE%V`?L+'eTB)NƸ^NRz-\pq#B \1)3p&lʅ%((pnvANxS)ETp!_H< +4\b `:?8x,kmngǪ$77at!i)K[/Eb$`\[J+,f×"J~ f2'9"9nYƭaF%h5080_'ݕl`4-ZnJwOR{fyd*#OIJ4+P)K1^z*kLS>,^[=YVH=n/N-kWɛfҼdofX5.O5[(_V)¿V)sL?  +:ǘug\`=b=n[JȗM92$觘&Y+:ЦDE*;bD1"US,w5iZص8"+*I'Y"aR`d"c$ sm-BZybc~1Yy[R s}k@-[ѲV_|;#%]FcgWMDyƧݞ#7;δc2;d:C/FgzG{yb_7z'h)B|̢vb3>1&sFܒح)d(eC2IuLndn*i}c=3 6.Ѳ +-%Z29Z:" |bpp8hu$Ee0f'C{:qe*f)=A3z_zT3 gI(G̡g6ͦg'Y0ٵy>-e"%iٮફ; +I 1*(K,A6AEUEDDTDaPZwetڎ3utNt*N;M?!ϩ:swFu Kp麈 2\ʦj#[Ʀ)c1]zVifG( Z!‘Lj':fMjNKj9R8J˕E%AɌK¥;I=&D'&*O[5Ǭ0g+#֬ғbrseUx:[\s DHtUrQ%U*4=1M3M@[u`k}jvw5~w-3xqch%ۢI4'Llx"Of؎qqTo3 }qBOpS_;br{kC[]rͤ="[f\`.oow=C}ʜrV:Dw47/T﹄8$~EcHOr@' ۱oi7 { W}r|R _'Q/_ŧў +8~K M3CQcyx!/:^e~O 'xAJcxGg!ESÿ]gM;AJHM|s^OO''4r_em/OxH40?K`'NO ^q/%kIgcL3ׄǣ\^U#Ӷp>-\_ȷVn9mkq9 M^5yۅCxe9vޮǣN]ƪآ7ɓ`Q&M5|zĝ+x&Fo/+rPwܯ&uVy`PlYƎf hUʓ-g\O&]Wnuzt?8ePǐN]ZuE`] eO<9+b^.ÓLood3ݮusJ~L^g:[."X= k*aMu%8ǞiG +'AOR5,~gG˖<E9` 5$.5/Gf'+b{*NNAhdn$ 5]BPV``v|XEz:rPu&|Q'sNn5}߮yWJ-IŤ\9AM!MEfe7x=ΆU kO>9}Ul= ԗ8mKLdӱYqnS^k=$Z-w.""7dXR*L9́^ >PkorN^I#?>u1d7_,6q7w.@N%Ƒ#ȑtJR.'z+^ɥQ7ڗEQaDwy)"'薺$EVZ]d6Gc1d~,{زȋƑB/( e /lEiFZgE^gENs[Aixtθ422YՑH6:t4Er#)뗑Q2Mrngo!Ǘu=~3f~7B9gvr#';-"K^ddD~H64RsD)H5]Dy.Ku'zz9y샿k\̢x]&.d.aEizUꑡrr~\{DznfuE'(,洐Y-dz:mzotdS-tCK ōqv#(;;ڋ,+-H[0)ǷrCKoᲞ]v?uC_a/GxptC73w[fU/'̓䂼H`/.΋=9܋֋eыeɓŠ q+&%£D,f 4~:nrG ˕-KIsL +2(a =ը7tpҘCUэٕՕǥ @hpV$?!SP^B^bj~%b .f4R7OtI*[w|זܗ a9 c-}.zEo#cK6r'r` f Kewny]T,b ⛩CgL@'@]o 6&R%4(9.͍Me֟ //%L'}YTBQLtRh#z`qr ŧؽ:WudAGp$Fr'#pd8y1Q$P(9@!,s2:+5|#Ĭd?}fT+|iObdPc,&xƏhq4q $cb,EaE>GӧFm3}[-|"ek/M.8/QM:ݤӤ2q/qq4p1>bqUO$OsM2\$4VO Id=8`ɉYLzDe=dcB` <~9l&MSPߧI~dhE\,B 2mN,evCm6AkJre\.6/1-(< ">GNð +.V+/gZvRG{o~6{Xf:gIL \EAФkt0.KeIj> f;yH\熣}N8ױwMg%k4,[tr&3,J'FW􎃼G<'HBPh)UV^=]>W٥ 5~i-ZѪWv}:ԩ@nt+>}a9)R3s-ygUkֽGjJR!)dV$Q&q(^Hv\BW⟈[ {˃>DM4D_#c/c[h&OܿPj߾-wK=%9Enc&hJGv&'ڱ_v &O_Dc̚hɯo4};懻t#=D޽ǧT avfD'Pm[|ps/ב_6D6n:Sn(g^=9Ke{)#]ʀ}edM+گj(wE$*F6D+v˝75ZU3*QŢI6_QMckbv6ܟIe(ߎە%%KoqŊ ݘPQ=*WR+˿%@@%jHhsNм`#ƕ֕K +G7FsRewdBFf_tN 6hb!?Yv%?+a@U;5d/Xz%Y`_He]L-FfP|6W ;mC5߳ Yhc_l ]s,"~ +zx[n}6Sաv#/41#9i+6^pZp>y ``,PX\ b$q/b8 u֫)iĜGTXG'Ds "j"@D0:削-J N8}??<;B( VzQ +~T 7_l;oIRYW~WqWq#|G@.Dp((n+Gǟ/2v.;k0~6v>go1Ij p5If;pd| PMu>(YN$V|k.'.g`aN{+!8ژT +l H9"~s +Dۜiы)VD$f6>d (sb nck-_gMxE7m~@e9mբ֍̌y UoQ6=-;iբyǫXͶV+*K y6Hs5H07d6H|L{b+EF^S03!-sK275UجK{;'_/%2$nMHP`@`m1]V»tKu$^ ء٦"r`.Cl۠f P8r$`1Au5 <*ur$@2glY+vJCܟvhC$f]8}`=vFt:6-۶nָq&f[&4'9 b1Wq=)\Lڜ5R1]iMNY񾛏ҭmXͤ}ϡS}^*2d9mhůϟ>{.IXt񂹳= `q-=U᧨|Elw` $̀=KY+f ,@~o5:x" c0`y -g0W`;2 +endstream endobj 10 0 obj <> endobj xref +0 11 +0000000000 65535 f +0000000016 00000 n +0000000076 00000 n +0000059182 00000 n +0000000000 00000 f +0000059233 00000 n +0000059439 00000 n +0000137044 00000 n +0000059519 00000 n +0000137077 00000 n +0000629746 00000 n +trailer +<]>> +startxref +629948 +%%EOF diff --git a/doc/makefile b/doc/makefile new file mode 100644 index 0000000..ac16ff2 --- /dev/null +++ b/doc/makefile @@ -0,0 +1,78 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating documentation process +## based on markdown and pandoc +## +## ---------------------------------------------------------------------------- + +################################################################### +# Definitions +# +################################################################### +PROJECT = pulse_width_modulator + +DATASHEET_YAML = datasheet.yaml +REPORT_YAML = report.yaml +PRESENTATION_YAML = presentation.yaml + +################################################################### +# Main Targets +# +################################################################### + +help: + @echo '"make" does intentionally nothing. Type:' + @echo ' "make datasheet" to create a datasheet' + @echo ' "make report" to create a report' + @echo ' "make presentation" to create a presentation' + @echo ' "make clean" to remove all generated files' + + +datasheet: $(PROJECT)_datasheet.md + pandoc --template uasa_meng_vlsi_template.tex $(DATASHEET_YAML) $(PROJECT)_datasheet.md -o $(PROJECT)_datasheet.pdf --highlight-style tango + + +report: $(PROJECT)_report.md + pandoc --template uasa_meng_vlsi_template.tex $(REPORT_YAML) $(PROJECT)_report.md -o $(PROJECT)_report.pdf --highlight-style tango --number-sections + + +presentation: $(PROJECT)_presentation.md + pandoc -t beamer --template uasa_meng_vlsi_template.tex $(PRESENTATION_YAML) $(PROJECT)_presentation.md -o $(PROJECT)_presentation.pdf + + + +clean: + rm -rf $(PROJECT)_datasheet.pdf $(PROJECT)_report.pdf $(PROJECT)_presentation.pdf + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## project +## | +## |-- makefile +## | +## +-- doc/ +## | |-- stepper_motor_controller_datasheet.md +## | |-- stepper_motor_controller_datasheet.pdf +## | |-- stepper_motor_controller_report.md +## | |-- stepper_motor_controller_report.pdf +## | |-- stepper_motor_controller_presentation.md +## | |-- stepper_motor_controller_presentation.pdf +## | |-- ... +## | | +## | +-- images +## | |-- smctrl_modes.fodg +## | |-- smctrl_modes.png +## | |-- smctrl_modes_simwave.png +## | |-- wave_drive_timing.pdf +## | |-- wave_drive_timing.svg +## | |-- ... +## | +## ---------------------------------------------------------------------------- + diff --git a/doc/presentation.yaml b/doc/presentation.yaml new file mode 100644 index 0000000..fbb54bf --- /dev/null +++ b/doc/presentation.yaml @@ -0,0 +1,11 @@ +--- +title: Presentation Title +subtitle: VLSI-Design Module - Presentation +author: J Färber +date: July 202x +lang: en-UK +theme: Pittsburgh +colortheme: default +code-block-font-size: \tiny +--- + diff --git a/doc/pulse_width_modulator_datasheet.md b/doc/pulse_width_modulator_datasheet.md new file mode 100644 index 0000000..2f1caa4 --- /dev/null +++ b/doc/pulse_width_modulator_datasheet.md @@ -0,0 +1,206 @@ +Introduction +============ + +A heartbeat generator can be used in a digital system to ... + +Features +======== + +Normal rhythm produces four entities – a P wave, a QRS complex, a T wave, and a U wave – that each +have a fairly unique pattern. [[1]](https://en.wikipedia.org/wiki/Electrocardiography) + +For simplicity the existing heartbeat module generates the QRS complex and T wave only. + + * Models QRS-Complex and T-Wave + * Average time values based on 72 bpm + * Enable input for external prescaler + + +General Description +=================== + +![Heartbeat Generator - Schematic Symbol](images/heartbeat_gen.png){width=40%} + +| **Name** | **Type** | **Direction** | **Polarity** | **Description** | +|-------------|-------------------|:-------------:|:------------:|-----------------| +| clk_i | std_ulogic | IN | HIGH | clock | + +: Heartbeat Generator - Description of I/O Signals + + +Functional Description +====================== + +The shape of an [electrogardiogramm](https://en.wikipedia.org/wiki/Electrocardiography) as a voltage graph over time + + + +![Electrocardiogram](images/ECG-SinusRhythmLabel.png){width=20%} + +The important QRS complex and T wave are modelled as digital pulses. + +![QRS Complex and T Wave Pulses](images/qrs-complex-t-wave-pulses.pdf){width=80%} + + +Design Description +================== + +A conceptional RTL diagram is shown below. + +![Heartbeat Generator - Conceptional RTL](images/heartbeat_gen_conceptional_rtl.pdf){width=60%} + +The simulation result shows two full periods based on a clock period of 1 ms + +![Two Periods - Simulation Result](images/heartbeat_gen_two_periods_simwave.png){width=80%} + +In more detail using cursors to display correct parameters of the QRS complex and T wave. + +![QRS-Complex and T-Wave - Simulation Result](images/qrs-complex-t-wave_simwave.png){width=80%} + + + +Device Utilization and Performance +================================== + +The following table shows the utilisation of both modules heartbeat_gen and cntdnmodm. + +The following results are extracted from + + ```pure + pnr/de1_heartbeat_gen/de1_heartbeat_gen.fit.rpt + ``` + + +```pure ++--------------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+-------------------------------------------------+ +``` + +The following results are extracted from + + ```pure +de1_heartbeat_gen.sta.rpt +``` + +```pure ++----------------------------------------------------------------------------------------+ +; TimeQuest Timing Analyzer Summary ; ++--------------------+-------------------------------------------------------------------+ + +-----------------------------------------+ +; Clocks ; ++------------+------+--------+-----------+ + + ++-----------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+-------+-------+----------+---------+---------------------+ + +``` + +Application Note +================ + +The following test environment on a DE1 prototype board uses a system clock frequency of 50 MHz. +A prescaler is parameterised to generate an output signal with a period of 1 ms. + +![Test Environment on DE1 Prototype Board](images/de1_heartbeat_gen_schematic.pdf){width=70%} + + + +Appendix +======== + +References +---------- + +* [Wiki: Electrocardiography](https://en.wikipedia.org/wiki/Electrocardiography) + +Project Hierarchy +----------------- + +### Module Hierarchy for Verification + +```pure +t_heartbeat_gen(tbench) + heartbeat_gen(rtl) +``` + +### Prototype Environment + +```pure +de1_heartbeat_gen(structure) + heartbeat_gen(rtl) + cntdnmodm(rtl) +``` + +VHDL Sources +------------ + +```vhdl +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY heartbeat_gen IS + PORT (clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + en_pi : IN std_ulogic; + count_o : OUT std_ulogic_vector; + heartbeat_o : OUT std_ulogic + ); +END heartbeat_gen; +``` + +```vhdl +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ARCHITECTURE rtl OF heartbeat_gen IS + + CONSTANT n : natural := 10; + CONSTANT zero : unsigned(n-1 DOWNTO 0) := (OTHERS => '0'); + + CONSTANT heartbeat_period : unsigned(n-1 DOWNTO 0) := to_unsigned(833, n); + CONSTANT qrs_width : unsigned(n-1 DOWNTO 0) := to_unsigned(100, n); + CONSTANT st_width + CONSTANT t_width + CONSTANT qt_width + + SIGNAL next_state, current_state : unsigned(n-1 DOWNTO 0); + + SIGNAL tc_qrs : std_ulogic; -- qrs interval + SIGNAL tc_t : std_ulogic; -- T wave + +BEGIN + + next_state_logic : + + + + state_register : + + + -- output_logic + t_wave : tc_t <= + + + + qrs_complex : tc_qrs <= + + + output_value : heartbeat_o <= + + +END rtl; +``` + +Revision History +---------------- + +| **Date** | **Version** | **Change Summary** | +|:----------|:-------------|:--------------------| +| May 2020 | 0.1 | Initial Release | +| April 2021 | 0.2 | Added parameterisation | + diff --git a/doc/pulse_width_modulator_presentation.md b/doc/pulse_width_modulator_presentation.md new file mode 100644 index 0000000..d742c03 --- /dev/null +++ b/doc/pulse_width_modulator_presentation.md @@ -0,0 +1,106 @@ +--- +title: Heartbeat Generator +subtitle: VLSI-Design Module - Presentation +author: J Färber +date: SS2021 +--- + +Overview +======== + +* Features +* Interface Signals +* Block Diagram +* Functional Description +* Simulation Result +* Device Utilization and Performance +* Demonstration +* Questions + +Features +======== + + * Models QRS-Complex and T-Wave + * Average time values based on 72 bpm + * Enable input for external prescaler + +Interface Signals +================= + +![Heartbeat Generator - Schematic Symbol](images/heartbeat_gen_symbol.pdf){width=40%} + + +Functional Description +====================== + +Simplification to Digital Pulses +--------- + +![Electrocardiogram](images/ECG-SinusRhythmLabel.png){width=20%} + + +![QRS Complex and T Wave Pulses](images/qrs-complex-t-wave-pulses.pdf){width=80%} + + +Functional Description +====================== + +Conceptional RTL Diagram +--------------- + +![Heartbeat Generator - Conceptional RTL](images/heartbeat_gen_conceptional_rtl.pdf){width=60%} + +Simulation Result - Top Level +============================= + +![Two Periods - Simulation Result](images/heartbeat_gen_two_periods_simwave.png){width=80%} + +Device Utilization and Performance +================================== + +```pure ++------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+-----------------------------------------+ +; Fitter Status ; Successful - Wed Mar 31 11:50:15 2021 ; +; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web ; +; Revision Name ; de1_heartbeat_gen ; +; Top-level Entity Name ; de1_heartbeat_gen ; +; Family ; Cyclone II ; +; Device ; EP2C20F484C7 ; +; Timing Models ; Final ; +; Total logic elements ; 50 / 18,752 ( < 1 % ) ; +; Total combinational functions ; 50 / 18,752 ( < 1 % ) ; +; Dedicated logic registers ; 26 / 18,752 ( < 1 % ) ; +; Total registers ; 26 ; +; Total pins ; 15 / 315 ( 5 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 239,616 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; ++------------------------------------+-----------------------------------------+ +``` + +Demonstration +============= + +Prototype Setup +--------------- + +![Test Environment on DE1 Prototype Board](images/de1_heartbeat_gen_schematic.pdf){width=70%} + +Demonstration +============= + +Test Environment +---------------- + + + + + +Questions +========= + +Thank you for your attention ! + diff --git a/doc/pulse_width_modulator_report.md b/doc/pulse_width_modulator_report.md new file mode 100644 index 0000000..67cb4c2 --- /dev/null +++ b/doc/pulse_width_modulator_report.md @@ -0,0 +1,235 @@ +Introduction +============ + +A heartbeat generator can be used in a digital system to display activity of a system. +Based on population studies, a heartrate between 60 and 100 beats per minute (bpm) +is considered as normal for a human adult. + +Features +======== + +Normal rhythm produces four entities – a P wave, a QRS complex, a T wave, and a U wave – that each +have a fairly unique pattern. [[1]](https://en.wikipedia.org/wiki/Electrocardiography) + +For simplicity the existing heartbeat modules generates the QRS complex and T wave only. + + * Models QRS-Complex and T-Wave + * Average time values based on 72 bpm + * Enable input for external prescaler + + +General Description +=================== + +![Heartbeat Generator - Schematic Symbol](images/heartbeat_gen_symbol.pdf){width=40%} + +| **Name** | **Type** | **Direction** | **Polarity** | **Description** | +|-------------|-------------------|:-------------:|:------------:|-----------------| +| clk_i | std_ulogic | IN | HIGH | clock | +| rst_ni | std_ulogic | IN | LOW | reset | +| en_pi | std_ulogic | IN | HIGH | enable | +| count_o | std_ulogic_vector | OUT | HIGH | count value | +| heartbeat_o | std_ulogic | OUT | HIGH | hearbeat pulse output | + +: Heartbeat Generator - Description of I/O Signals + + +Functional Description +====================== + +The shape of an [electrogardiogramm](https://en.wikipedia.org/wiki/Electrocardiography) as a voltage graph over time + + + +![Electrocardiogram](images/ECG-SinusRhythmLabel.png){width=20%} + +The important QRS complex and T wave are modelled as digital pulses. + +![QRS Complex and T Wave Pulses](images/qrs-complex-t-wave-pulses.pdf){width=80%} + + +Design Description +================== + +A conceptional RTL diagram is shown below. + +![Heartbeat Generator - Conceptional RTL](images/heartbeat_gen_conceptional_rtl.pdf){width=60%} + +The simulation result shows two full periods based on a clock period of 1 ms + +![Two Periods - Simulation Result](images/heartbeat_gen_two_periods_simwave.png){width=80%} + +In more detail using cursors to display correct parameters of the QRS complex and T wave. + +![QRS-Complex and T-Wave - Simulation Result](images/qrs-complex-t-wave_simwave.png){width=80%} + + + +Device Utilization and Performance +================================== + +The following table shows the utilisation of both modules heartbeat_gen and cntdnmodm. + +```pure ++--------------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+-------------------------------------------------+ +; Fitter Status ; Successful - Wed Mar 31 11:50:15 2021 ; +; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; +; Revision Name ; de1_heartbeat_gen ; +; Top-level Entity Name ; de1_heartbeat_gen ; +; Family ; Cyclone II ; +; Device ; EP2C20F484C7 ; +; Timing Models ; Final ; +; Total logic elements ; 50 / 18,752 ( < 1 % ) ; +; Total combinational functions ; 50 / 18,752 ( < 1 % ) ; +; Dedicated logic registers ; 26 / 18,752 ( < 1 % ) ; +; Total registers ; 26 ; +; Total pins ; 15 / 315 ( 5 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 239,616 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; ++------------------------------------+-------------------------------------------------+ +``` + +```pure + ++----------------------------------------------------------------------------------------+ +; TimeQuest Timing Analyzer Summary ; ++--------------------+-------------------------------------------------------------------+ +; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ; +; Revision Name ; de1_heartbeat_gen ; +; Device Family ; Cyclone II ; +; Device Name ; EP2C20F484C7 ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Unavailable ; ++--------------------+-------------------------------------------------------------------+ + +-----------------------------------------+ +; Clocks ; ++------------+------+--------+-----------+ +; Clock Name ; Type ; Period ; Frequency ; ++------------+------+--------+-----------+ +; CLOCK_50 ; Base ; 20.000 ; 50.0 MHz ; ++------------+------+--------+-----------+ + + ++-----------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+-------+-------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+-------+-------+----------+---------+---------------------+ +; Worst-case Slack ; 3.390 ; 0.241 ; 13.381 ; 3.796 ; 8.889 ; +; CLOCK_50 ; 3.390 ; 0.241 ; 13.381 ; 3.796 ; 8.889 ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; +; CLOCK_50 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; ++------------------+-------+-------+----------+---------+---------------------+ +``` + +Application Note +================ + +The following test environment on a DE1 prototype board uses a system clock frequency of 50 MHz. +A prescaler is parameterised to generate an output signal with a period of 1 ms. + +![Test Environment on DE1 Prototype Board](images/de1_heartbeat_gen_schematic.pdf){width=70%} + + + +Appendix +======== + +References +---------- + +* [Wiki: Electrocardiography](https://en.wikipedia.org/wiki/Electrocardiography) + +Project Hierarchy +----------------- + +### Module Hierarchy for Verification + +```pure +t_heartbeat_gen(tbench) + heartbeat_gen(rtl) +``` + +### Prototype Environment + +```pure +de1_heartbeat_gen(structure) + heartbeat_gen(rtl) + cntdnmodm(rtl) +``` + +VHDL Sources +------------ + +```vhdl +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY heartbeat_gen IS + PORT (clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + en_pi : IN std_ulogic; + count_o : OUT std_ulogic_vector; + heartbeat_o : OUT std_ulogic + ); +END heartbeat_gen; +``` + +```vhdl +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ARCHITECTURE rtl OF heartbeat_gen IS + + CONSTANT n : natural := 10; + CONSTANT zero : unsigned(n-1 DOWNTO 0) := (OTHERS => '0'); + + CONSTANT heartbeat_period : unsigned(n-1 DOWNTO 0) := to_unsigned(833, n); + CONSTANT qrs_width : unsigned(n-1 DOWNTO 0) := to_unsigned(100, n); + CONSTANT st_width + CONSTANT t_width + CONSTANT qt_width + + SIGNAL next_state, current_state : unsigned(n-1 DOWNTO 0); + + SIGNAL tc_qrs : std_ulogic; -- qrs interval + SIGNAL tc_t : std_ulogic; -- T wave + +BEGIN + + next_state_logic : + + + + state_register : + + + -- output_logic + t_wave : tc_t <= + + + + qrs_complex : tc_qrs <= + + + output_value : heartbeat_o <= + + +END rtl; +``` + +Revision History +---------------- + +| **Date** | **Version** | **Change Summary** | +|:----------|:-------------|:--------------------| +| May 2020 | 0.1 | Initial Release | +| April 2021 | 0.2 | Added parameterisation | + diff --git a/doc/report.yaml b/doc/report.yaml new file mode 100644 index 0000000..1989e0a --- /dev/null +++ b/doc/report.yaml @@ -0,0 +1,27 @@ +--- +title: Pulse Width Modulator +subtitle: VLSI-Design Module - Report +author: J Färber +date: SS2022 +lang: en-UK +geometry: a4paper, left=25mm, right=20mm, top=20mm, bottom=25mm +fontsize: 12pt +code-block-font-size: \scriptsize +titlepage: true +logo: images/uasa-logo.pdf +toc: true +lof: true +lot: true +toc-own-page: true +colorlinks: true +secnumdepth: 4 +header-includes: +# 4th level header rendering +# see https://stackoverflow.com/questions/21198025/pandoc-generation-of-pdf-from-markdown-4th-header-is-rendered-differently/21204829#21204829 + - | + ``` {=latex} + \let\originAlParaGraph\paragraph + \renewcommand{\paragraph}[1]{\originAlParaGraph{#1} \hfill} + ``` +--- + diff --git a/doc/uasa_meng_vlsi_template.tex b/doc/uasa_meng_vlsi_template.tex new file mode 100644 index 0000000..7aac2a7 --- /dev/null +++ b/doc/uasa_meng_vlsi_template.tex @@ -0,0 +1,1038 @@ +%% +% Copyright (c) 2017 - 2020, Pascal Wagler; +% Copyright (c) 2014 - 2020, John MacFarlane +% +% All rights reserved. +% +% Redistribution and use in source and binary forms, with or without +% modification, are permitted provided that the following conditions +% are met: +% +% - Redistributions of source code must retain the above copyright +% notice, this list of conditions and the following disclaimer. +% +% - Redistributions in binary form must reproduce the above copyright +% notice, this list of conditions and the following disclaimer in the +% documentation and/or other materials provided with the distribution. +% +% - Neither the name of John MacFarlane nor the names of other +% contributors may be used to endorse or promote products derived +% from this software without specific prior written permission. +% +% THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +% "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +% LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +% FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +% COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +% INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +% BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +% LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +% CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +% LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +% ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +% POSSIBILITY OF SUCH DAMAGE. +%% + +%% +% This is the Eisvogel pandoc LaTeX template. +% +% For usage information and examples visit the official GitHub page: +% https://github.com/Wandmalfarbe/pandoc-latex-template +%% + +% Options for packages loaded elsewhere +\PassOptionsToPackage{unicode$for(hyperrefoptions)$,$hyperrefoptions$$endfor$}{hyperref} +\PassOptionsToPackage{hyphens}{url} +\PassOptionsToPackage{dvipsnames,svgnames*,x11names*,table}{xcolor} +$if(dir)$ +$if(latex-dir-rtl)$ +\PassOptionsToPackage{RTLdocument}{bidi} +$endif$ +$endif$ +% +\documentclass[ +$if(fontsize)$ + $fontsize$, +$endif$ +$if(lang)$ + $babel-lang$, +$endif$ +$if(papersize)$ + $papersize$paper, +$else$ + a4paper, +$endif$ +$if(beamer)$ + ignorenonframetext, +$if(handout)$ + handout, +$endif$ +$if(aspectratio)$ + aspectratio=$aspectratio$, +$endif$ +$endif$ +$for(classoption)$ + $classoption$$sep$, +$endfor$ +,tablecaptionabove +]{$if(beamer)$$documentclass$$else$$if(book)$scrbook$else$scrartcl$endif$$endif$} +$if(beamer)$ +$if(background-image)$ +\usebackgroundtemplate{% + \includegraphics[width=\paperwidth]{$background-image$}% +} +$endif$ +\usepackage{pgfpages} +\setbeamertemplate{caption}[numbered] +\setbeamertemplate{caption label separator}{: } +\setbeamercolor{caption name}{fg=normal text.fg} +\beamertemplatenavigationsymbols$if(navigation)$$navigation$$else$empty$endif$ +$for(beameroption)$ +\setbeameroption{$beameroption$} +$endfor$ +% Prevent slide breaks in the middle of a paragraph +\widowpenalties 1 10000 +\raggedbottom +$if(section-titles)$ +\setbeamertemplate{part page}{ + \centering + \begin{beamercolorbox}[sep=16pt,center]{part title} + \usebeamerfont{part title}\insertpart\par + \end{beamercolorbox} +} +\setbeamertemplate{section page}{ + \centering + \begin{beamercolorbox}[sep=12pt,center]{part title} + \usebeamerfont{section title}\insertsection\par + \end{beamercolorbox} +} +\setbeamertemplate{subsection page}{ + \centering + \begin{beamercolorbox}[sep=8pt,center]{part title} + \usebeamerfont{subsection title}\insertsubsection\par + \end{beamercolorbox} +} +\AtBeginPart{ + \frame{\partpage} +} +\AtBeginSection{ + \ifbibliography + \else + \frame{\sectionpage} + \fi +} +\AtBeginSubsection{ + \frame{\subsectionpage} +} +$endif$ +$endif$ +$if(beamerarticle)$ +\usepackage{beamerarticle} % needs to be loaded first +$endif$ +$if(fontfamily)$ +\usepackage[$for(fontfamilyoptions)$$fontfamilyoptions$$sep$,$endfor$]{$fontfamily$} +$else$ +\usepackage{lmodern} +$endif$ +$if(linestretch)$ +\usepackage{setspace} +\setstretch{$linestretch$} +$else$ +\usepackage{setspace} +\setstretch{1.2} +$endif$ +\usepackage{amssymb,amsmath} +\usepackage{ifxetex,ifluatex} +\ifnum 0\ifxetex 1\fi\ifluatex 1\fi=0 % if pdftex + \usepackage[$if(fontenc)$$fontenc$$else$T1$endif$]{fontenc} + \usepackage[utf8]{inputenc} + \usepackage{textcomp} % provide euro and other symbols +\else % if luatex or xetex +$if(mathspec)$ + \ifxetex + \usepackage{mathspec} + \else + \usepackage{unicode-math} + \fi +$else$ + \usepackage{unicode-math} +$endif$ + \defaultfontfeatures{Scale=MatchLowercase} + \defaultfontfeatures[\rmfamily]{Ligatures=TeX,Scale=1} +$if(mainfont)$ + \setmainfont[$for(mainfontoptions)$$mainfontoptions$$sep$,$endfor$]{$mainfont$} +$endif$ +$if(sansfont)$ + \setsansfont[$for(sansfontoptions)$$sansfontoptions$$sep$,$endfor$]{$sansfont$} +$endif$ +$if(monofont)$ + \setmonofont[$for(monofontoptions)$$monofontoptions$$sep$,$endfor$]{$monofont$} +$endif$ +$for(fontfamilies)$ + \newfontfamily{$fontfamilies.name$}[$for(fontfamilies.options)$$fontfamilies.options$$sep$,$endfor$]{$fontfamilies.font$} +$endfor$ +$if(mathfont)$ +$if(mathspec)$ + \ifxetex + \setmathfont(Digits,Latin,Greek)[$for(mathfontoptions)$$mathfontoptions$$sep$,$endfor$]{$mathfont$} + \else + \setmathfont[$for(mathfontoptions)$$mathfontoptions$$sep$,$endfor$]{$mathfont$} + \fi +$else$ + \setmathfont[$for(mathfontoptions)$$mathfontoptions$$sep$,$endfor$]{$mathfont$} +$endif$ +$endif$ +$if(CJKmainfont)$ + \ifxetex + \usepackage{xeCJK} + \setCJKmainfont[$for(CJKoptions)$$CJKoptions$$sep$,$endfor$]{$CJKmainfont$} + \fi +$endif$ +$if(luatexjapresetoptions)$ + \ifluatex + \usepackage[$for(luatexjapresetoptions)$$luatexjapresetoptions$$sep$,$endfor$]{luatexja-preset} + \fi +$endif$ +$if(CJKmainfont)$ + \ifluatex + \usepackage[$for(luatexjafontspecoptions)$$luatexjafontspecoptions$$sep$,$endfor$]{luatexja-fontspec} + \setmainjfont[$for(CJKoptions)$$CJKoptions$$sep$,$endfor$]{$CJKmainfont$} + \fi +$endif$ +\fi +$if(beamer)$ +$if(theme)$ +\usetheme[$for(themeoptions)$$themeoptions$$sep$,$endfor$]{$theme$} +$endif$ +$if(colortheme)$ +\usecolortheme{$colortheme$} +$endif$ +$if(fonttheme)$ +\usefonttheme{$fonttheme$} +$endif$ +$if(mainfont)$ +\usefonttheme{serif} % use mainfont rather than sansfont for slide text +$endif$ +$if(innertheme)$ +\useinnertheme{$innertheme$} +$endif$ +$if(outertheme)$ +\useoutertheme{$outertheme$} +$endif$ +$endif$ +% Use upquote if available, for straight quotes in verbatim environments +\IfFileExists{upquote.sty}{\usepackage{upquote}}{} +\IfFileExists{microtype.sty}{% use microtype if available + \usepackage[$for(microtypeoptions)$$microtypeoptions$$sep$,$endfor$]{microtype} + \UseMicrotypeSet[protrusion]{basicmath} % disable protrusion for tt fonts +}{} +$if(indent)$ +$else$ +\makeatletter +\@ifundefined{KOMAClassName}{% if non-KOMA class + \IfFileExists{parskip.sty}{% + \usepackage{parskip} + }{% else + \setlength{\parindent}{0pt} + \setlength{\parskip}{6pt plus 2pt minus 1pt}} +}{% if KOMA class + \KOMAoptions{parskip=half}} +\makeatother +$endif$ +$if(verbatim-in-note)$ +\usepackage{fancyvrb} +$endif$ +\usepackage{xcolor} +\definecolor{default-linkcolor}{HTML}{A50000} +\definecolor{default-filecolor}{HTML}{A50000} +\definecolor{default-citecolor}{HTML}{4077C0} +\definecolor{default-urlcolor}{HTML}{4077C0} +\IfFileExists{xurl.sty}{\usepackage{xurl}}{} % add URL line breaks if available +$if(footnotes-pretty)$ +% load footmisc in order to customize footnotes (footmisc has to be loaded before hyperref, cf. https://tex.stackexchange.com/a/169124/144087) +\usepackage[hang,flushmargin,bottom,multiple]{footmisc} +\setlength{\footnotemargin}{0.8em} % set space between footnote nr and text +\setlength{\footnotesep}{\baselineskip} % set space between multiple footnotes +\setlength{\skip\footins}{0.3cm} % set space between page content and footnote +\setlength{\footskip}{0.9cm} % set space between footnote and page bottom +$endif$ +\IfFileExists{bookmark.sty}{\usepackage{bookmark}}{\usepackage{hyperref}} +\hypersetup{ +$if(title-meta)$ + pdftitle={$title-meta$}, +$endif$ +$if(author-meta)$ + pdfauthor={$author-meta$}, +$endif$ +$if(lang)$ + pdflang={$lang$}, +$endif$ +$if(subject)$ + pdfsubject={$subject$}, +$endif$ +$if(keywords)$ + pdfkeywords={$for(keywords)$$keywords$$sep$, $endfor$}, +$endif$ +$if(colorlinks)$ + colorlinks=true, + linkcolor=$if(linkcolor)$$linkcolor$$else$default-linkcolor$endif$, + filecolor=$if(filecolor)$$filecolor$$else$default-filecolor$endif$, + citecolor=$if(citecolor)$$citecolor$$else$default-citecolor$endif$, + urlcolor=$if(urlcolor)$$urlcolor$$else$default-urlcolor$endif$, +$else$ + hidelinks, +$endif$ + breaklinks=true, + pdfcreator={LaTeX via pandoc with the Eisvogel template}} +\urlstyle{same} % disable monospaced font for URLs +$if(verbatim-in-note)$ +\VerbatimFootnotes % allow verbatim text in footnotes +$endif$ +$if(geometry)$ +$if(beamer)$ +\geometry{$for(geometry)$$geometry$$sep$,$endfor$} +$else$ +\usepackage[$for(geometry)$$geometry$$sep$,$endfor$]{geometry} +$endif$ +$else$ +$if(beamer)$ +$else$ +\usepackage[margin=2.5cm,includehead=true,includefoot=true,centering,$for(geometry)$$geometry$$sep$,$endfor$]{geometry} +$endif$ +$endif$ +$if(logo)$ +\usepackage[export]{adjustbox} +\usepackage{graphicx} +$endif$ +$if(beamer)$ +\newif\ifbibliography +$endif$ +$if(listings)$ +\usepackage{listings} +\newcommand{\passthrough}[1]{#1} +\lstset{defaultdialect=[5.3]Lua} +\lstset{defaultdialect=[x86masm]Assembler} +$endif$ +$if(listings-no-page-break)$ +\usepackage{etoolbox} +\BeforeBeginEnvironment{lstlisting}{\par\noindent\begin{minipage}{\linewidth}} +\AfterEndEnvironment{lstlisting}{\end{minipage}\par\addvspace{\topskip}} +$endif$ +$if(lhs)$ +\lstnewenvironment{code}{\lstset{language=Haskell,basicstyle=\small\ttfamily}}{} +$endif$ +$if(highlighting-macros)$ +$highlighting-macros$ + +% Workaround/bugfix from jannick0. +% See https://github.com/jgm/pandoc/issues/4302#issuecomment-360669013) +% or https://github.com/Wandmalfarbe/pandoc-latex-template/issues/2 +% +% Redefine the verbatim environment 'Highlighting' to break long lines (with +% the help of fvextra). Redefinition is necessary because it is unlikely that +% pandoc includes fvextra in the default template. +\usepackage{fvextra} +\DefineVerbatimEnvironment{Highlighting}{Verbatim}{breaklines,fontsize=$if(code-block-font-size)$$code-block-font-size$$else$\small$endif$,commandchars=\\\{\}} + +$endif$ +$if(tables)$ +\usepackage{longtable,booktabs} +$if(beamer)$ +\usepackage{caption} +% Make caption package work with longtable +\makeatletter +\def\fnum@table{\tablename~\thetable} +\makeatother +$else$ +% Correct order of tables after \paragraph or \subparagraph +\usepackage{etoolbox} +\makeatletter +\patchcmd\longtable{\par}{\if@noskipsec\mbox{}\fi\par}{}{} +\makeatother +% Allow footnotes in longtable head/foot +\IfFileExists{footnotehyper.sty}{\usepackage{footnotehyper}}{\usepackage{footnote}} +\makesavenoteenv{longtable} +$endif$ +$endif$ +% add backlinks to footnote references, cf. https://tex.stackexchange.com/questions/302266/make-footnote-clickable-both-ways +$if(footnotes-disable-backlinks)$ +$else$ +\usepackage{footnotebackref} +$endif$ +$if(graphics)$ +\usepackage{graphicx,grffile} +\makeatletter +\def\maxwidth{\ifdim\Gin@nat@width>\linewidth\linewidth\else\Gin@nat@width\fi} +\def\maxheight{\ifdim\Gin@nat@height>\textheight\textheight\else\Gin@nat@height\fi} +\makeatother +% Scale images if necessary, so that they will not overflow the page +% margins by default, and it is still possible to overwrite the defaults +% using explicit options in \includegraphics[width, height, ...]{} +\setkeys{Gin}{width=\maxwidth,height=\maxheight,keepaspectratio} +$endif$ +$if(links-as-notes)$ +% Make links footnotes instead of hotlinks: +\DeclareRobustCommand{\href}[2]{#2\footnote{\url{#1}}} +$endif$ +$if(strikeout)$ +\usepackage[normalem]{ulem} +% Avoid problems with \sout in headers with hyperref +\pdfstringdefDisableCommands{\renewcommand{\sout}{}} +$endif$ +\setlength{\emergencystretch}{3em} % prevent overfull lines +\providecommand{\tightlist}{% + \setlength{\itemsep}{0pt}\setlength{\parskip}{0pt}} +$if(numbersections)$ +\setcounter{secnumdepth}{$if(secnumdepth)$$secnumdepth$$else$3$endif$} +$else$ +\setcounter{secnumdepth}{-\maxdimen} % remove section numbering +$endif$ +$if(beamer)$ +$else$ +$if(block-headings)$ +% Make \paragraph and \subparagraph free-standing +\ifx\paragraph\undefined\else + \let\oldparagraph\paragraph + \renewcommand{\paragraph}[1]{\oldparagraph{#1}\mbox{}} +\fi +\ifx\subparagraph\undefined\else + \let\oldsubparagraph\subparagraph + \renewcommand{\subparagraph}[1]{\oldsubparagraph{#1}\mbox{}} +\fi +$endif$ +$endif$ +$if(pagestyle)$ +\pagestyle{$pagestyle$} +$endif$ + +% Make use of float-package and set default placement for figures to H. +% The option H means 'PUT IT HERE' (as opposed to the standard h option which means 'You may put it here if you like'). +\usepackage{float} +\floatplacement{figure}{$if(float-placement-figure)$$float-placement-figure$$else$H$endif$} + +$for(header-includes)$ +$header-includes$ +$endfor$ +$if(lang)$ +\ifxetex + $if(mainfont)$ + $else$ + % See issue https://github.com/reutenauer/polyglossia/issues/127 + \renewcommand*\familydefault{\sfdefault} + $endif$ + % Load polyglossia as late as possible: uses bidi with RTL langages (e.g. Hebrew, Arabic) + \usepackage{polyglossia} + \setmainlanguage[$polyglossia-lang.options$]{$polyglossia-lang.name$} +$for(polyglossia-otherlangs)$ + \setotherlanguage[$polyglossia-otherlangs.options$]{$polyglossia-otherlangs.name$} +$endfor$ +\else + \usepackage[shorthands=off,$for(babel-otherlangs)$$babel-otherlangs$,$endfor$main=$babel-lang$]{babel} +$if(babel-newcommands)$ + $babel-newcommands$ +$endif$ +\fi +$endif$ +$if(dir)$ +\ifxetex + % Load bidi as late as possible as it modifies e.g. graphicx + \usepackage{bidi} +\fi +\ifnum 0\ifxetex 1\fi\ifluatex 1\fi=0 % if pdftex + \TeXXeTstate=1 + \newcommand{\RL}[1]{\beginR #1\endR} + \newcommand{\LR}[1]{\beginL #1\endL} + \newenvironment{RTL}{\beginR}{\endR} + \newenvironment{LTR}{\beginL}{\endL} +\fi +$endif$ +$if(natbib)$ +\usepackage[$natbiboptions$]{natbib} +\bibliographystyle{$if(biblio-style)$$biblio-style$$else$plainnat$endif$} +$endif$ +$if(biblatex)$ +\usepackage[$if(biblio-style)$style=$biblio-style$,$endif$$for(biblatexoptions)$$biblatexoptions$$sep$,$endfor$]{biblatex} +$for(bibliography)$ +\addbibresource{$bibliography$} +$endfor$ +$endif$ +$if(csl-refs)$ +\newlength{\cslhangindent} +\setlength{\cslhangindent}{1.5em} +\newenvironment{cslreferences}% + {$if(csl-hanging-indent)$\setlength{\parindent}{0pt}% + \everypar{\setlength{\hangindent}{\cslhangindent}}\ignorespaces$endif$}% + {\par} +$endif$ + +$if(title)$ +\title{$title$$if(thanks)$\thanks{$thanks$}$endif$} +$endif$ +$if(subtitle)$ +$if(beamer)$ +$else$ +\usepackage{etoolbox} +\makeatletter +\providecommand{\subtitle}[1]{% add subtitle to \maketitle + \apptocmd{\@title}{\par {\large #1 \par}}{}{} +} +\makeatother +$endif$ +\subtitle{$subtitle$} +$endif$ +$if(author)$ +\author{$for(author)$$author$$sep$ \and $endfor$} +$endif$ +\date{$date$} +$if(beamer)$ +$if(institute)$ +\institute{$for(institute)$$institute$$sep$ \and $endfor$} +$endif$ +$if(titlegraphic)$ +\titlegraphic{\includegraphics{$titlegraphic$}} +$endif$ +$if(logo)$ +\logo{\includegraphics{$logo$}} +$endif$ +$endif$ + + + +%% +%% added +%% + +% +% language specification +% +% If no language is specified, use English as the default main document language. +% +$if(lang)$$else$ +\ifnum 0\ifxetex 1\fi\ifluatex 1\fi=0 % if pdftex + \usepackage[shorthands=off,$for(babel-otherlangs)$$babel-otherlangs$,$endfor$main=english]{babel} +$if(babel-newcommands)$ + $babel-newcommands$ +$endif$ +\else + $if(mainfont)$ + $else$ + % Workaround for bug in Polyglossia that breaks `\familydefault` when `\setmainlanguage` is used. + % See https://github.com/Wandmalfarbe/pandoc-latex-template/issues/8 + % See https://github.com/reutenauer/polyglossia/issues/186 + % See https://github.com/reutenauer/polyglossia/issues/127 + \renewcommand*\familydefault{\sfdefault} + $endif$ + % load polyglossia as late as possible as it *could* call bidi if RTL lang (e.g. Hebrew or Arabic) + \usepackage{polyglossia} + \setmainlanguage[]{english} +$for(polyglossia-otherlangs)$ + \setotherlanguage[$polyglossia-otherlangs.options$]{$polyglossia-otherlangs.name$} +$endfor$ +\fi +$endif$ + +$if(page-background)$ +\usepackage[pages=all]{background} +$endif$ + +% +% for the background color of the title page +% +$if(titlepage)$ +\usepackage{pagecolor} +\usepackage{afterpage} +$if(titlepage-background)$ +\usepackage{tikz} +$endif$ +$if(geometry)$ +$else$ +\usepackage[margin=2.5cm,includehead=true,includefoot=true,centering]{geometry} +$endif$ +$endif$ + +% +% break urls +% +\PassOptionsToPackage{hyphens}{url} + +% +% When using babel or polyglossia with biblatex, loading csquotes is recommended +% to ensure that quoted texts are typeset according to the rules of your main language. +% +\usepackage{csquotes} + +% +% captions +% +\definecolor{caption-color}{HTML}{777777} +$if(beamer)$ +$else$ +\usepackage[font={stretch=1.2}, textfont={color=caption-color}, position=top, skip=4mm, labelfont=bf, singlelinecheck=false, justification=$if(caption-justification)$$caption-justification$$else$raggedright$endif$]{caption} +\setcapindent{0em} +$endif$ + +% +% blockquote +% +\definecolor{blockquote-border}{RGB}{221,221,221} +\definecolor{blockquote-text}{RGB}{119,119,119} +\usepackage{mdframed} +\newmdenv[rightline=false,bottomline=false,topline=false,linewidth=3pt,linecolor=blockquote-border,skipabove=\parskip]{customblockquote} +\renewenvironment{quote}{\begin{customblockquote}\list{}{\rightmargin=0em\leftmargin=0em}% +\item\relax\color{blockquote-text}\ignorespaces}{\unskip\unskip\endlist\end{customblockquote}} + +% +% Source Sans Pro as the de­fault font fam­ily +% Source Code Pro for monospace text +% +% 'default' option sets the default +% font family to Source Sans Pro, not \sfdefault. +% +\ifnum 0\ifxetex 1\fi\ifluatex 1\fi=0 % if pdftex + $if(fontfamily)$ + $else$ + \usepackage[default]{sourcesanspro} + \usepackage{sourcecodepro} + $endif$ +\else % if not pdftex + $if(mainfont)$ + $else$ + \usepackage[default]{sourcesanspro} + \usepackage{sourcecodepro} + + % XeLaTeX specific adjustments for straight quotes: https://tex.stackexchange.com/a/354887 + % This issue is already fixed (see https://github.com/silkeh/latex-sourcecodepro/pull/5) but the + % fix is still unreleased. + % TODO: Remove this workaround when the new version of sourcecodepro is released on CTAN. + \ifxetex + \makeatletter + \defaultfontfeatures[\ttfamily] + { Numbers = \sourcecodepro@figurestyle, + Scale = \SourceCodePro@scale, + Extension = .otf } + \setmonofont + [ UprightFont = *-\sourcecodepro@regstyle, + ItalicFont = *-\sourcecodepro@regstyle It, + BoldFont = *-\sourcecodepro@boldstyle, + BoldItalicFont = *-\sourcecodepro@boldstyle It ] + {SourceCodePro} + \makeatother + \fi + $endif$ +\fi + +% +% heading color +% +\definecolor{heading-color}{RGB}{40,40,40} +$if(beamer)$ +$else$ +\addtokomafont{section}{\color{heading-color}} +$endif$ +% When using the classes report, scrreprt, book, +% scrbook or memoir, uncomment the following line. +%\addtokomafont{chapter}{\color{heading-color}} + +% +% variables for title and author +% +$if(beamer)$ +$else$ +\usepackage{titling} +\title{$title$} +\author{$for(author)$$author$$sep$, $endfor$} +$endif$ + +% +% tables +% +$if(tables)$ + +\definecolor{table-row-color}{HTML}{F5F5F5} +\definecolor{table-rule-color}{HTML}{999999} + +%\arrayrulecolor{black!40} +\arrayrulecolor{table-rule-color} % color of \toprule, \midrule, \bottomrule +\setlength\heavyrulewidth{0.3ex} % thickness of \toprule, \bottomrule +\renewcommand{\arraystretch}{1.3} % spacing (padding) + +$if(table-use-row-colors)$ +% TODO: This doesn't work anymore. I don't know why. +% Reset rownum counter so that each table +% starts with the same row colors. +% https://tex.stackexchange.com/questions/170637/restarting-rowcolors +% +% Unfortunately the colored cells extend beyond the edge of the +% table because pandoc uses @-expressions (@{}) like so: +% +% \begin{longtable}[]{@{}ll@{}} +% \end{longtable} +% +% https://en.wikibooks.org/wiki/LaTeX/Tables#.40-expressions +\let\oldlongtable\longtable +\let\endoldlongtable\endlongtable +\renewenvironment{longtable}{ +\rowcolors{3}{}{table-row-color!100} % row color +\oldlongtable} { +\endoldlongtable +\global\rownum=0\relax} +$endif$ +$endif$ + +% +% remove paragraph indention +% +\setlength{\parindent}{0pt} +\setlength{\parskip}{6pt plus 2pt minus 1pt} +\setlength{\emergencystretch}{3em} % prevent overfull lines + +% +% +% Listings +% +% + +$if(listings)$ + +% +% general listing colors +% +\definecolor{listing-background}{HTML}{F7F7F7} +\definecolor{listing-rule}{HTML}{B3B2B3} +\definecolor{listing-numbers}{HTML}{B3B2B3} +\definecolor{listing-text-color}{HTML}{000000} +\definecolor{listing-keyword}{HTML}{435489} +\definecolor{listing-keyword-2}{HTML}{1284CA} % additional keywords +\definecolor{listing-keyword-3}{HTML}{9137CB} % additional keywords +\definecolor{listing-identifier}{HTML}{435489} +\definecolor{listing-string}{HTML}{00999A} +\definecolor{listing-comment}{HTML}{8E8E8E} + +\lstdefinestyle{eisvogel_listing_style}{ + language = java, +$if(listings-disable-line-numbers)$ + xleftmargin = 0.6em, + framexleftmargin = 0.4em, +$else$ + numbers = left, + xleftmargin = 2.7em, + framexleftmargin = 2.5em, +$endif$ + backgroundcolor = \color{listing-background}, + basicstyle = \color{listing-text-color}\linespread{1.0}$if(code-block-font-size)$$code-block-font-size$$else$\small$endif$\ttfamily{}, + breaklines = true, + frame = single, + framesep = 0.19em, + rulecolor = \color{listing-rule}, + frameround = ffff, + tabsize = 4, + numberstyle = \color{listing-numbers}, + aboveskip = 1.0em, + belowskip = 0.1em, + abovecaptionskip = 0em, + belowcaptionskip = 1.0em, + keywordstyle = {\color{listing-keyword}\bfseries}, + keywordstyle = {[2]\color{listing-keyword-2}\bfseries}, + keywordstyle = {[3]\color{listing-keyword-3}\bfseries\itshape}, + sensitive = true, + identifierstyle = \color{listing-identifier}, + commentstyle = \color{listing-comment}, + stringstyle = \color{listing-string}, + showstringspaces = false, + escapeinside = {/*@}{@*/}, % Allow LaTeX inside these special comments + literate = + {á}{{\'a}}1 {é}{{\'e}}1 {í}{{\'i}}1 {ó}{{\'o}}1 {ú}{{\'u}}1 + {Á}{{\'A}}1 {É}{{\'E}}1 {Í}{{\'I}}1 {Ó}{{\'O}}1 {Ú}{{\'U}}1 + {à}{{\`a}}1 {è}{{\'e}}1 {ì}{{\`i}}1 {ò}{{\`o}}1 {ù}{{\`u}}1 + {À}{{\`A}}1 {È}{{\'E}}1 {Ì}{{\`I}}1 {Ò}{{\`O}}1 {Ù}{{\`U}}1 + {ä}{{\"a}}1 {ë}{{\"e}}1 {ï}{{\"i}}1 {ö}{{\"o}}1 {ü}{{\"u}}1 + {Ä}{{\"A}}1 {Ë}{{\"E}}1 {Ï}{{\"I}}1 {Ö}{{\"O}}1 {Ü}{{\"U}}1 + {â}{{\^a}}1 {ê}{{\^e}}1 {î}{{\^i}}1 {ô}{{\^o}}1 {û}{{\^u}}1 + {Â}{{\^A}}1 {Ê}{{\^E}}1 {Î}{{\^I}}1 {Ô}{{\^O}}1 {Û}{{\^U}}1 + {œ}{{\oe}}1 {Œ}{{\OE}}1 {æ}{{\ae}}1 {Æ}{{\AE}}1 {ß}{{\ss}}1 + {ç}{{\c c}}1 {Ç}{{\c C}}1 {ø}{{\o}}1 {å}{{\r a}}1 {Å}{{\r A}}1 + {€}{{\EUR}}1 {£}{{\pounds}}1 {«}{{\guillemotleft}}1 + {»}{{\guillemotright}}1 {ñ}{{\~n}}1 {Ñ}{{\~N}}1 {¿}{{?`}}1 + {…}{{\ldots}}1 {≥}{{>=}}1 {≤}{{<=}}1 {„}{{\glqq}}1 {“}{{\grqq}}1 + {”}{{''}}1 +} +\lstset{style=eisvogel_listing_style} + +% +% Java (Java SE 12, 2019-06-22) +% +\lstdefinelanguage{Java}{ + morekeywords={ + % normal keywords (without data types) + abstract,assert,break,case,catch,class,continue,default, + do,else,enum,exports,extends,final,finally,for,if,implements, + import,instanceof,interface,module,native,new,package,private, + protected,public,requires,return,static,strictfp,super,switch, + synchronized,this,throw,throws,transient,try,volatile,while, + % var is an identifier + var + }, + morekeywords={[2] % data types + % primitive data types + boolean,byte,char,double,float,int,long,short, + % String + String, + % primitive wrapper types + Boolean,Byte,Character,Double,Float,Integer,Long,Short + % number types + Number,AtomicInteger,AtomicLong,BigDecimal,BigInteger,DoubleAccumulator,DoubleAdder,LongAccumulator,LongAdder,Short, + % other + Object,Void,void + }, + morekeywords={[3] % literals + % reserved words for literal values + null,true,false, + }, + sensitive, + morecomment = [l]//, + morecomment = [s]{/*}{*/}, + morecomment = [s]{/**}{*/}, + morestring = [b]", + morestring = [b]', +} + +\lstdefinelanguage{XML}{ + morestring = [b]", + moredelim = [s][\bfseries\color{listing-keyword}]{<}{\ }, + moredelim = [s][\bfseries\color{listing-keyword}]{}, + moredelim = [l][\bfseries\color{listing-keyword}]{/>}, + moredelim = [l][\bfseries\color{listing-keyword}]{>}, + morecomment = [s]{}, + morecomment = [s]{}, + commentstyle = \color{listing-comment}, + stringstyle = \color{listing-string}, + identifierstyle = \color{listing-identifier} +} +$endif$ + +% +% header and footer +% +$if(beamer)$ +$else$ +$if(disable-header-and-footer)$ +$else$ +\usepackage{fancyhdr} + +\fancypagestyle{eisvogel-header-footer}{ + \fancyhead{} + \fancyfoot{} + \lhead[$if(header-right)$$header-right$$else$$date$$endif$]{$if(header-left)$$header-left$$else$$title$$endif$} + \chead[$if(header-center)$$header-center$$else$$endif$]{$if(header-center)$$header-center$$else$$endif$} + \rhead[$if(header-left)$$header-left$$else$$title$$endif$]{$if(header-right)$$header-right$$else$$date$$endif$} + \lfoot[$if(footer-right)$$footer-right$$else$\thepage$endif$]{$if(footer-left)$$footer-left$$else$$for(author)$$author$$sep$, $endfor$$endif$} + \cfoot[$if(footer-center)$$footer-center$$else$$endif$]{$if(footer-center)$$footer-center$$else$$endif$} + \rfoot[$if(footer-left)$$footer-left$$else$$for(author)$$author$$sep$, $endfor$$endif$]{$if(footer-right)$$footer-right$$else$\thepage$endif$} + \renewcommand{\headrulewidth}{0.4pt} + \renewcommand{\footrulewidth}{0.4pt} +} +\pagestyle{eisvogel-header-footer} +$if(page-background)$ +\backgroundsetup{ +scale=1, +color=black, +opacity=$if(page-background-opacity)$$page-background-opacity$$else$0.2$endif$, +angle=0, +contents={% + \includegraphics[width=\paperwidth,height=\paperheight]{$page-background$} + }% +} +$endif$ +$endif$ +$endif$ + +%% +%% end added +%% + +\begin{document} + +%% +%% begin titlepage +%% +$if(beamer)$ +$else$ +$if(titlepage)$ +\begin{titlepage} +$if(titlepage-background)$ +\newgeometry{top=2cm, right=4cm, bottom=3cm, left=4cm} +$else$ +\newgeometry{left=6cm} +$endif$ +$if(titlepage-color)$ +\definecolor{titlepage-color}{HTML}{$titlepage-color$} +\newpagecolor{titlepage-color}\afterpage{\restorepagecolor} +$endif$ +$if(titlepage-background)$ +\tikz[remember picture,overlay] \node[inner sep=0pt] at (current page.center){\includegraphics[width=\paperwidth,height=\paperheight]{$titlepage-background$}}; +$endif$ +\newcommand{\colorRule}[3][black]{\textcolor[HTML]{#1}{\rule{#2}{#3}}} +\begin{flushleft} +\noindent +\\[-1em] +\color[HTML]{$if(titlepage-text-color)$$titlepage-text-color$$else$5F5F5F$endif$} +\makebox[0pt][l]{\colorRule[$if(titlepage-rule-color)$$titlepage-rule-color$$else$435488$endif$]{1.3\textwidth}{$if(titlepage-rule-height)$$titlepage-rule-height$$else$4$endif$pt}} +\par +\noindent + +$if(logo)$ +\noindent +\includegraphics[width=$if(logo-width)$$logo-width$$else$100$endif$pt, right]{$logo$} +$endif$ + + +$if(titlepage-background)$ +% The titlepage with a background image has other text spacing and text size +{ + \setstretch{2} + \vfill + \vskip -8em + \noindent {\huge \textbf{\textsf{$title$}}} + $if(subtitle)$ + \vskip 1em + {\Large \textsf{$subtitle$}} + $endif$ + \vskip 2em + \noindent {\Large \textsf{$for(author)$$author$$sep$, $endfor$} \vskip 0.6em \textsf{$date$}} + \vfill +} +$else$ +{ + \setstretch{1.4} + \vfill + \noindent {\huge \textbf{\textsf{$title$}}} + $if(subtitle)$ + \vskip 1em + {\Large \textsf{$subtitle$}} + $endif$ + \vskip 2em + \noindent {\Large \textsf{$for(author)$$author$$sep$, $endfor$}} + \vfill +} +$endif$ + + +$if(titlepage-background)$ +$else$ +\textsf{$date$} +$endif$ +\end{flushleft} +\end{titlepage} +\restoregeometry +$endif$ +$endif$ + +%% +%% end titlepage +%% + +$if(has-frontmatter)$ +\frontmatter +$endif$ +$if(title)$ +$if(beamer)$ +\frame{\titlepage} +$endif$ +$if(abstract)$ +\begin{abstract} +$abstract$ +\end{abstract} +$endif$ +$endif$ + +$if(first-chapter)$ +\setcounter{chapter}{$first-chapter$} +\addtocounter{chapter}{-1} +$endif$ + +$for(include-before)$ +$include-before$ + +$endfor$ +$if(toc)$ +$if(toc-title)$ +\renewcommand*\contentsname{$toc-title$} +$endif$ +$if(beamer)$ +\begin{frame} +$if(toc-title)$ + \frametitle{$toc-title$} +$endif$ + \tableofcontents[hideallsubsections] +\end{frame} +$if(toc-own-page)$ +\newpage +$endif$ +$else$ +{ +$if(colorlinks)$ +\hypersetup{linkcolor=$if(toccolor)$$toccolor$$else$$endif$} +$endif$ +\setcounter{tocdepth}{$if(toc-depth)$$toc-depth$$else$3$endif$} +\tableofcontents +$if(toc-own-page)$ +\newpage +$endif$ +} +$endif$ +$endif$ +$if(lot)$ +\listoftables +\newpage +$endif$ +$if(lof)$ +\listoffigures +\newpage +$endif$ +$if(linestretch)$ +\setstretch{$linestretch$} +$endif$ +$if(has-frontmatter)$ +\mainmatter +$endif$ +$body$ + +$if(has-frontmatter)$ +\backmatter +$endif$ +$if(natbib)$ +$if(bibliography)$ +$if(biblio-title)$ +$if(has-chapters)$ +\renewcommand\bibname{$biblio-title$} +$else$ +\renewcommand\refname{$biblio-title$} +$endif$ +$endif$ +$if(beamer)$ +\begin{frame}[allowframebreaks]{$biblio-title$} + \bibliographytrue +$endif$ + \bibliography{$for(bibliography)$$bibliography$$sep$,$endfor$} +$if(beamer)$ +\end{frame} +$endif$ + +$endif$ +$endif$ +$if(biblatex)$ +$if(beamer)$ +\begin{frame}[allowframebreaks]{$biblio-title$} + \bibliographytrue + \printbibliography[heading=none] +\end{frame} +$else$ +\printbibliography$if(biblio-title)$[title=$biblio-title$]$endif$ +$endif$ + +$endif$ +$for(include-after)$ +$include-after$ + +$endfor$ +\end{document} diff --git a/doc/vec.conf b/doc/vec.conf new file mode 100644 index 0000000..856e7eb --- /dev/null +++ b/doc/vec.conf @@ -0,0 +1,243 @@ + + +############################################################################# +# Parser keywords +############################################################################# +# Polarity +HIGHActiveSuffix=_pi +LOWActiveSuffix=_ni + +# Special ports +#resetName=rst_n +#clockName=clk +resetName=rst_ni +clockName=clk_i +#resetName=rst_pi +#clockName=clk_i +#resetName=rst_i +#clockName=clk_i +#clockName=CLOCK_50 +#resetName=KEY +#resetName=reset +#clockName=clock + +# Default label to print above entity box. Leave empty if no label is desired +default_label= + + +############################################################################# +# Font settings +############################################################################# +# Label +label.fontFamily=Arial +label.fontSize=10pt +label.fontWeight=normal + +# Entity +entity.fontFamily=Arial +entity.fontSize=12pt +entity.fontWeight=bold + +#Port +port.fontFamily=Arial +port.fontSize=12pt +port.fontWeight=normal + +# Generic signal +genericSignal.fontFamily=Arial +genericSignal.fontSize=10pt +genericSignal.fontWeight=normal + +# Vector +vector.fontFamily=Arial +vector.fontSize=10pt +vector.fontWeight=normal + + +############################################################################# +# Shape settings +############################################################################# +# Margin +vertical_Margin=0.5 +horizontal_Margin=0.5 +fixed_Width=0 + +# Label +label.stroke=none +label.strokeWidth=0.00cm +label.strokeColor=#000000 +label.fill=none +label.fillColor=#FFFFFF + +# Entity +entity.stroke=solid +entity.strokeWidth=0.05cm +entity.strokeColor=#000000 +entity.fill=solid +entity.fillColor=#FFFFFF + +# Port +port.stroke=none +port.strokeWidth=0.00cm +port.strokeColor=#FFF +port.fill=none +port.fillColor=#FFFFFF + +# Connector +connector.stroke=solid +connector.strokeWidth=0.025cm +connector.strokeColor=#000000 +connector.fill=solid +connector.fillColor=#FFFFFF + +# Generics +generics.stroke=solid +generics.strokeWidth=0.02cm +generics.strokeColor=#BFBFBF +generics.fill=solid +generics.fillColor=#F2F2F2 + +# Generic signal +genericSignal.stroke=none +genericSignal.strokeWidth=0.00cm +genericSignal.strokeColor=#C2C2C2 +genericSignal.fill=none +genericSignal.fillColor=#FFFFFF + + +############################################################################# +# Doku Wiki markup settings +############################################################################# +DokuWiki.enableExport=0 + +# If left empty the output files will be placed in the same directory where the executable is located. +# Both absolute and relative path are working +DokuWiki.outputPath=dokuwiki + + +############################################################################# +# Markdown settings +############################################################################# +Markdown.enableExport=0 + +# If left empty the output files will be placed in the same directory where the executable is located. +# Both absolute and relative path are working +Markdown.outputPath=markdown + + +############################################################################# +# LaTeX settings +############################################################################# +LaTeX.enableExport=0 + +# If left empty the output files will be placed in the same directory where the executable is located. +# Both absolute and relative path are working +LaTeX.outputPath=latex + +# VEC can add a 'table' environment to label and place the actual tabular element. +# VEC will use the entity name as caption and label +LaTeX.addTable=1 +LaTeX.centering=1 +LaTeX.caption=1 +LaTeX.label=1 + + +############################################################################# +# Table export settings +############################################################################# +# Set the entity information the table should contain +Table.exportType=1 +Table.exportDirection=1 +Table.exportPolarity=1 +Table.exportDescription=1 +Table.exportBlank1=0 +Table.exportBlank2=0 + +# Export generics. Generate a seperate table for generic signals +Table.exportGenerics=1 + +# Heading formatting +Table.boldHeadings=1 + +# Column alignments +Table.centeredName=0 +Table.centeredType=0 +Table.centeredDirection=1 +Table.centeredPolarity=1 +Table.centeredDescription=0 +Table.centeredBlank=0 +Table.centeredGenericName=0 +Table.centeredGenericType=0 +Table.centeredGenericDefaultValue=0 + +# Column headings +Table.Name_heading=Name +Table.Type_heading=Type +Table.Direction_heading=Direction +Table.Polarity_heading=Polarity +Table.Description_heading=Description +Table.Blank1_heading=Blank1 +Table.Blank2_heading=Blank2 +Table.GenericName=Name +Table.GenericType=Type +Table.GenericDefaultValue=Default value + +# Captions for the port directions +Table.caption_IN=IN +Table.caption_OUT=OUT +Table.caption_INOUT=INOUT +Table.caption_BUFFER=BUFFER +Table.caption_LINKAGE=LINKAGE + +# Polarity labels +Table.caption_HIGHactive=HIGH +Table.caption_LOWactive=LOW + +# Vector settings +Table.combineNameAndType=0 +Table.showArrayLength=1 +Table.arrayNotation=1 + + +############################################################################# +# PATH settings +############################################################################# +# Path to LibreOffice executable. +# e.g. for WINDOWS +# C:\Program Files (x86)\LibreOffice 4.0\program\soffice.exe +# e.g. for UNIX platforms +# /usr/bin/soffice + +#PATH.soffice=C:\Program Files (x86)\LibreOffice 3.6\program\soffice.exe +PATH.soffice=/usr/bin/soffice + + +############################################################################# +# FODG Export +############################################################################# +FODG.enableExport=1 + +# If left empty the output files will be placed in the same directory where the executable is located +#FODG.outputPath=fodg +FODG.outputPath=. + + +############################################################################# +# PNG Export +############################################################################# +PNG.enableExport=1 + +# If left empty the output files will be placed in the same directory where the executable is located +#PNG.outputPath=png +PNG.outputPath=. + + +############################################################################# +# SVG Export +############################################################################# +SVG.enableExport=0 + +# If left empty the output files will be placed in the same directory where the executable is located +#SVG.outputPath=svg +SVG.outputPath=. + diff --git a/matlab/audio/audio_first.slx b/matlab/audio/audio_first.slx new file mode 100644 index 0000000..848e1be Binary files /dev/null and b/matlab/audio/audio_first.slx differ diff --git a/matlab/audio/audio_tone.slx b/matlab/audio/audio_tone.slx new file mode 100644 index 0000000..5b8586b Binary files /dev/null and b/matlab/audio/audio_tone.slx differ diff --git a/matlab/audio/makefile b/matlab/audio/makefile new file mode 100644 index 0000000..37ef569 --- /dev/null +++ b/matlab/audio/makefile @@ -0,0 +1,4 @@ +PROJECT=audio_first +TOPLEVEL=$(PROJECT)/ml_audio + +include ../makefile diff --git a/matlab/makefile b/matlab/makefile new file mode 100644 index 0000000..2832597 --- /dev/null +++ b/matlab/makefile @@ -0,0 +1,15 @@ +################################################################### +# Main Targets +################################################################### + +help: + @echo '"make" does intentionally nothing. Type:' + @echo ' "make hdl" - create vhdl files from matlab simulink model' + @echo ' "make clean" - to remove all generated files' + +hdl: $(PROJECT).slx + # create hdl from matlab + matlab -nodisplay -nosplash -nodesktop -r "$(PROJECT); makehdl('$(TOPLEVEL)') ;exit;" + +clean: + rm -rf hdl_prj slprj *~ diff --git a/pnr/de1_and2gate/de1_and2gate_pins.tcl b/pnr/de1_and2gate/de1_and2gate_pins.tcl new file mode 100644 index 0000000..9c70aec --- /dev/null +++ b/pnr/de1_and2gate/de1_and2gate_pins.tcl @@ -0,0 +1,10 @@ +# assign pin locations to a quartus project + +#---------------------------------------------------------------------- +# Pin Assignments +set_location_assignment PIN_L22 -to SW[0] +set_location_assignment PIN_L21 -to SW[1] +set_location_assignment PIN_R20 -to LEDR[0] +set_location_assignment PIN_R19 -to LEDR[1] +set_location_assignment PIN_U19 -to LEDR[2] +# ---------------------------------------------------------------------------- diff --git a/pnr/de1_and2gate/makefile b/pnr/de1_and2gate/makefile new file mode 100644 index 0000000..103b8c1 --- /dev/null +++ b/pnr/de1_and2gate/makefile @@ -0,0 +1,53 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with Quartus, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# - assign variable SIM_PROJECT_NAME with the top level project name +# - add additional VHDL sources to SOURCE_FILES, if necessary +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd +################################################################### + +SIM_PROJECT_NAME = and2gate +PROJECT = de1_$(SIM_PROJECT_NAME) + +# Prototype Board FPGA family and device settings +# DE1 +FAMILY = "Cyclone II" +DEVICE = EP2C20F484C7 +PROGFILEEXT = sof +# DEMMK +# FAMILY = "MAX II" +# DEVICE = EPM2210F324C3 +# PROGFILEEXT = pof +# DE2 +#FAMILY = "Cyclone II" +#DEVICE = EP2C35F484C7 +#PROGFILEEXT = sof +# DE0 +#FAMILY = "Cyclone IV E" +#DEVICE = EP4CE22F17C6 +#PROGFILEEXT = sof + +# Here the VHDL files for synthesis are defined. +include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources + +# Add the toplevel fpga vhdl file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/$(PROJECT)_structure.vhd + +include ../makefile + + diff --git a/pnr/de1_audio/de1_audio_pins.tcl b/pnr/de1_audio/de1_audio_pins.tcl new file mode 100644 index 0000000..28fe709 --- /dev/null +++ b/pnr/de1_audio/de1_audio_pins.tcl @@ -0,0 +1,23 @@ +# Pin Configuration +set_location_assignment PIN_L1 -to CLOCK_50 +set_location_assignment PIN_R22 -to KEY0 +set_location_assignment PIN_A3 -to I2C_SCLK +set_location_assignment PIN_B3 -to I2C_SDAT +set_location_assignment PIN_A6 -to AUD_ADCLRCK +set_location_assignment PIN_B6 -to AUD_ADCDAT +set_location_assignment PIN_A5 -to AUD_DACLRCK +set_location_assignment PIN_B5 -to AUD_DACDAT +set_location_assignment PIN_B4 -to AUD_XCK +set_location_assignment PIN_A4 -to AUD_BCLK +set_location_assignment PIN_R20 -to LEDR[0] +set_location_assignment PIN_R19 -to LEDR[1] +set_location_assignment PIN_U19 -to LEDR[2] +set_location_assignment PIN_Y19 -to LEDR[3] +set_location_assignment PIN_T18 -to LEDR[4] +set_location_assignment PIN_V19 -to LEDR[5] +set_location_assignment PIN_Y18 -to LEDR[6] +set_location_assignment PIN_U18 -to LEDR[7] +set_location_assignment PIN_R18 -to LEDR[8] +set_location_assignment PIN_R17 -to LEDR[9] + + diff --git a/pnr/de1_audio/makefile b/pnr/de1_audio/makefile new file mode 100644 index 0000000..0a8636c --- /dev/null +++ b/pnr/de1_audio/makefile @@ -0,0 +1,16 @@ +SIM_PROJECT_NAME = de1_audio +PROJECT = $(SIM_PROJECT_NAME) + +# Here the VHDL files for synthesis are defined. +include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources + +# Add the toplevel fpga vhdl file +SOURCE_FILES = $(SYN_SOURCE_FILES) + +FAMILY = "Cyclone II" +DEVICE = EP2C20F484C7 +PROGFILEEXT = sof + +include ../makefile + + diff --git a/pnr/de1_binto7segment/de1_binto7segment_pins.tcl b/pnr/de1_binto7segment/de1_binto7segment_pins.tcl new file mode 100644 index 0000000..ad20fb6 --- /dev/null +++ b/pnr/de1_binto7segment/de1_binto7segment_pins.tcl @@ -0,0 +1,20 @@ +# assign pin locations to a quartus project + +#---------------------------------------------------------------------- +# Pin Assignments +set_location_assignment PIN_L22 -to SW[0] +set_location_assignment PIN_L21 -to SW[1] +set_location_assignment PIN_M22 -to SW[2] +set_location_assignment PIN_V12 -to SW[3] +set_location_assignment PIN_R20 -to LEDR[0] +set_location_assignment PIN_R19 -to LEDR[1] +set_location_assignment PIN_U19 -to LEDR[2] +set_location_assignment PIN_Y19 -to LEDR[3] +set_location_assignment PIN_J2 -to HEX0[0] +set_location_assignment PIN_J1 -to HEX0[1] +set_location_assignment PIN_H2 -to HEX0[2] +set_location_assignment PIN_H1 -to HEX0[3] +set_location_assignment PIN_F2 -to HEX0[4] +set_location_assignment PIN_F1 -to HEX0[5] +set_location_assignment PIN_E2 -to HEX0[6] +# ---------------------------------------------------------------------------- diff --git a/pnr/de1_binto7segment/makefile b/pnr/de1_binto7segment/makefile new file mode 100644 index 0000000..60faed4 --- /dev/null +++ b/pnr/de1_binto7segment/makefile @@ -0,0 +1,53 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with Quartus, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# - assign variable SIM_PROJECT_NAME with the top level project name +# - add additional VHDL sources to SOURCE_FILES, if necessary +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd +################################################################### + +SIM_PROJECT_NAME = binto7segment +PROJECT = de1_$(SIM_PROJECT_NAME) + +# Prototype Board FPGA family and device settings +# DE1 +FAMILY = "Cyclone II" +DEVICE = EP2C20F484C7 +PROGFILEEXT = sof +# DEMMK +# FAMILY = "MAX II" +# DEVICE = EPM2210F324C3 +# PROGFILEEXT = pof +# DE2 +#FAMILY = "Cyclone II" +#DEVICE = EP2C35F484C7 +#PROGFILEEXT = sof +# DE0 +#FAMILY = "Cyclone IV E" +#DEVICE = EP4CE22F17C6 +#PROGFILEEXT = sof + +# Here the VHDL files for synthesis are defined. +include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources + +# Add the toplevel fpga vhdl file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/$(PROJECT)_structure.vhd + +include ../makefile + + diff --git a/pnr/de1_cntdn/de1_cntdn_pins.tcl b/pnr/de1_cntdn/de1_cntdn_pins.tcl new file mode 100644 index 0000000..cb02476 --- /dev/null +++ b/pnr/de1_cntdn/de1_cntdn_pins.tcl @@ -0,0 +1,14 @@ +# assign pin locations to a quartus project + +#---------------------------------------------------------------------- +# Pin Assignments +set_location_assignment PIN_L1 -to CLOCK_50 +set_location_assignment PIN_R22 -to KEY[0] +set_location_assignment PIN_R21 -to KEY[1] +set_location_assignment PIN_H12 -to GPO_1[0] +set_location_assignment PIN_H13 -to GPO_1[1] +set_location_assignment PIN_H14 -to GPO_1[2] +set_location_assignment PIN_G15 -to GPO_1[3] +set_location_assignment PIN_E14 -to GPO_1[4] +set_location_assignment PIN_E15 -to GPO_1[5] +# ---------------------------------------------------------------------------- diff --git a/pnr/de1_cntdn/makefile b/pnr/de1_cntdn/makefile new file mode 100644 index 0000000..fc13333 --- /dev/null +++ b/pnr/de1_cntdn/makefile @@ -0,0 +1,53 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with Quartus, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# - assign variable SIM_PROJECT_NAME with the top level project name +# - add additional VHDL sources to SOURCE_FILES, if necessary +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd +################################################################### + +SIM_PROJECT_NAME = cntdn +PROJECT = de1_$(SIM_PROJECT_NAME) + +# Prototype Board FPGA family and device settings +# DE1 +FAMILY = "Cyclone II" +DEVICE = EP2C20F484C7 +PROGFILEEXT = sof +# DEMMK +# FAMILY = "MAX II" +# DEVICE = EPM2210F324C3 +# PROGFILEEXT = pof +# DE2 +#FAMILY = "Cyclone II" +#DEVICE = EP2C35F484C7 +#PROGFILEEXT = sof +# DE0 +#FAMILY = "Cyclone IV E" +#DEVICE = EP4CE22F17C6 +#PROGFILEEXT = sof + +# Here the VHDL files for synthesis are defined. +include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources + +# Add the toplevel fpga vhdl file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/$(PROJECT)_structure.vhd + +include ../makefile + + diff --git a/pnr/de1_cntdnmodm/de1_cntdnmodm_pins.tcl b/pnr/de1_cntdnmodm/de1_cntdnmodm_pins.tcl new file mode 100644 index 0000000..81d32b6 --- /dev/null +++ b/pnr/de1_cntdnmodm/de1_cntdnmodm_pins.tcl @@ -0,0 +1,16 @@ +# assign pin locations to a quartus project + +#---------------------------------------------------------------------- +# Pin Assignments +set_location_assignment PIN_L1 -to CLOCK_50 +set_location_assignment PIN_R22 -to KEY[0] +set_location_assignment PIN_R21 -to KEY[1] +set_location_assignment PIN_H12 -to GPO_1[0] +set_location_assignment PIN_H13 -to GPO_1[1] +set_location_assignment PIN_H14 -to GPO_1[2] +set_location_assignment PIN_G15 -to GPO_1[3] +set_location_assignment PIN_E14 -to GPO_1[4] +set_location_assignment PIN_E15 -to GPO_1[5] +set_location_assignment PIN_F15 -to GPO_1[6] +set_location_assignment PIN_G16 -to GPO_1[7] +# ---------------------------------------------------------------------------- diff --git a/pnr/de1_cntdnmodm/makefile b/pnr/de1_cntdnmodm/makefile new file mode 100644 index 0000000..72e14e0 --- /dev/null +++ b/pnr/de1_cntdnmodm/makefile @@ -0,0 +1,53 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with Quartus, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# - assign variable SIM_PROJECT_NAME with the top level project name +# - add additional VHDL sources to SOURCE_FILES, if necessary +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd +################################################################### + +SIM_PROJECT_NAME = cntdnmodm +PROJECT = de1_$(SIM_PROJECT_NAME) + +# Prototype Board FPGA family and device settings +# DE1 +FAMILY = "Cyclone II" +DEVICE = EP2C20F484C7 +PROGFILEEXT = sof +# DEMMK +# FAMILY = "MAX II" +# DEVICE = EPM2210F324C3 +# PROGFILEEXT = pof +# DE2 +#FAMILY = "Cyclone II" +#DEVICE = EP2C35F484C7 +#PROGFILEEXT = sof +# DE0 +#FAMILY = "Cyclone IV E" +#DEVICE = EP4CE22F17C6 +#PROGFILEEXT = sof + +# Here the VHDL files for synthesis are defined. +include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources + +# Add the toplevel fpga vhdl file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/$(PROJECT)_structure.vhd + +include ../makefile + + diff --git a/pnr/de1_incrementer/de1_incrementer_pins.tcl b/pnr/de1_incrementer/de1_incrementer_pins.tcl new file mode 100644 index 0000000..7f21d8a --- /dev/null +++ b/pnr/de1_incrementer/de1_incrementer_pins.tcl @@ -0,0 +1,25 @@ +# assign pin locations to a quartus project + +#---------------------------------------------------------------------- +# Pin Assignments +set_location_assignment PIN_L1 -to CLOCK_50 +set_location_assignment PIN_R22 -to KEY +set_location_assignment PIN_H12 -to GPI_1[0] +set_location_assignment PIN_H13 -to GPI_1[1] +set_location_assignment PIN_U22 -to LEDG[0] +set_location_assignment PIN_U21 -to LEDG[1] +set_location_assignment PIN_J2 -to HEX0[0] +set_location_assignment PIN_J1 -to HEX0[1] +set_location_assignment PIN_H2 -to HEX0[2] +set_location_assignment PIN_H1 -to HEX0[3] +set_location_assignment PIN_F2 -to HEX0[4] +set_location_assignment PIN_F1 -to HEX0[5] +set_location_assignment PIN_E2 -to HEX0[6] +set_location_assignment PIN_E1 -to HEX1[0] +set_location_assignment PIN_H6 -to HEX1[1] +set_location_assignment PIN_H5 -to HEX1[2] +set_location_assignment PIN_H4 -to HEX1[3] +set_location_assignment PIN_G3 -to HEX1[4] +set_location_assignment PIN_D2 -to HEX1[5] +set_location_assignment PIN_D1 -to HEX1[6] +# ---------------------------------------------------------------------------- diff --git a/pnr/de1_incrementer/makefile b/pnr/de1_incrementer/makefile new file mode 100644 index 0000000..2202ce2 --- /dev/null +++ b/pnr/de1_incrementer/makefile @@ -0,0 +1,55 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with Quartus, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# - assign variable SIM_PROJECT_NAME with the top level project name +# - add additional VHDL sources to SOURCE_FILES, if necessary +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd +################################################################### + +SIM_PROJECT_NAME = incrementer +PROJECT = de1_$(SIM_PROJECT_NAME) + +# Prototype Board FPGA family and device settings +# DE1 +FAMILY = "Cyclone II" +DEVICE = EP2C20F484C7 +PROGFILEEXT = sof +# DEMMK +# FAMILY = "MAX II" +# DEVICE = EPM2210F324C3 +# PROGFILEEXT = pof +# DE2 +#FAMILY = "Cyclone II" +#DEVICE = EP2C35F484C7 +#PROGFILEEXT = sof +# DE0 +#FAMILY = "Cyclone IV E" +#DEVICE = EP4CE22F17C6 +#PROGFILEEXT = sof + +# Here the VHDL files for synthesis are defined. +include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources + +# Add the toplevel fpga vhdl file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/binto7segment_truthtable.vhd \ +../../src/synchroniser_rtl.vhd \ +../../src/$(PROJECT)_structure.vhd + +include ../makefile + + diff --git a/pnr/de1_mux2to1/de1_mux2to1_pins.tcl b/pnr/de1_mux2to1/de1_mux2to1_pins.tcl new file mode 100644 index 0000000..d6984a3 --- /dev/null +++ b/pnr/de1_mux2to1/de1_mux2to1_pins.tcl @@ -0,0 +1,9 @@ +# assign pin locations to a quartus project + +#---------------------------------------------------------------------- +# Pin Assignments +set_location_assignment PIN_L22 -to SW[0] +set_location_assignment PIN_L21 -to SW[1] +set_location_assignment PIN_M22 -to SW[2] +set_location_assignment PIN_R20 -to LEDR +# ---------------------------------------------------------------------------- diff --git a/pnr/de1_mux2to1/makefile b/pnr/de1_mux2to1/makefile new file mode 100644 index 0000000..b4c830b --- /dev/null +++ b/pnr/de1_mux2to1/makefile @@ -0,0 +1,87 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with Quartus, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# - assign variable SIM_PROJECT_NAME with the top level project name +# - add additional VHDL sources to SOURCE_FILES, if necessary +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd +################################################################### + +SIM_PROJECT_NAME = mux2to1 +PROJECT = de1_$(SIM_PROJECT_NAME) + +# Prototype Board FPGA family and device settings +# DE1 +FAMILY = "Cyclone II" +DEVICE = EP2C20F484C7 +PROGFILEEXT = sof +# DEMMK +# FAMILY = "MAX II" +# DEVICE = EPM2210F324C3 +# PROGFILEEXT = pof +# DE2 +#FAMILY = "Cyclone II" +#DEVICE = EP2C35F484C7 +#PROGFILEEXT = sof +# DE0 +#FAMILY = "Cyclone IV E" +#DEVICE = EP4CE22F17C6 +#PROGFILEEXT = sof + +# Here the VHDL files for synthesis are defined. +include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources + +# Add the toplevel fpga vhdl file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/$(PROJECT)_structure.vhd + +include ../makefile + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## DigitaltechnikPraktikum +## | +## +---src +## | and2gate_equation.vhd +## | invgate_equation.vhd +## | mux2to1_structure.vhd +## | or2gate_equation.vhd +## | t_mux2to1.vhd +## | de1_mux2to1_structure.vhd +## | +## +---sim +## | | makefile +## | | +## | \---mux2to1 +## | makefile +## | makefile.sources +## | +## +---pnr +## | | makefile +## | | +## | \---de1_mux2to1 +## | de1_mux2to1_pins.tcl +## | makefile +## | +## \---scripts +## de1_pin_assignments_minimumio.csv +## de1_pin_assignments_minimumio.tcl +## modelsim.ini +## quartus_project_settings.tcl +## ---------------------------------------------------------------------------- diff --git a/pnr/de1_pwm/de1_pwm_pins.tcl b/pnr/de1_pwm/de1_pwm_pins.tcl new file mode 100644 index 0000000..1d79959 --- /dev/null +++ b/pnr/de1_pwm/de1_pwm_pins.tcl @@ -0,0 +1,27 @@ +# assign pin locations to a quartus project + +#---------------------------------------------------------------------- +# Pin Assignments +set_location_assignment PIN_L1 -to CLOCK_50 +set_location_assignment PIN_R22 -to KEY[0] +set_location_assignment PIN_R21 -to KEY[1] +set_location_assignment PIN_L22 -to SW[0] +set_location_assignment PIN_L21 -to SW[1] +set_location_assignment PIN_M22 -to SW[2] +set_location_assignment PIN_V12 -to SW[3] +set_location_assignment PIN_W12 -to SW[4] +set_location_assignment PIN_U12 -to SW[5] +set_location_assignment PIN_U11 -to SW[6] +set_location_assignment PIN_M2 -to SW[7] +set_location_assignment PIN_R20 -to LEDR[0] +set_location_assignment PIN_R19 -to LEDR[1] +set_location_assignment PIN_U19 -to LEDR[2] +set_location_assignment PIN_Y19 -to LEDR[3] +set_location_assignment PIN_T18 -to LEDR[4] +set_location_assignment PIN_V19 -to LEDR[5] +set_location_assignment PIN_Y18 -to LEDR[6] +set_location_assignment PIN_U18 -to LEDR[7] +set_location_assignment PIN_H12 -to GPO_1[0] +set_location_assignment PIN_H13 -to GPO_1[1] +set_location_assignment PIN_H14 -to GPO_1[2] +# ---------------------------------------------------------------------------- diff --git a/pnr/de1_pwm/makefile b/pnr/de1_pwm/makefile new file mode 100644 index 0000000..5ed5024 --- /dev/null +++ b/pnr/de1_pwm/makefile @@ -0,0 +1,87 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with Quartus, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# - assign variable SIM_PROJECT_NAME with the top level project name +# - add additional VHDL sources to SOURCE_FILES, if necessary +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd +################################################################### + +SIM_PROJECT_NAME = pwm +PROJECT = de1_$(SIM_PROJECT_NAME) + +# Prototype Board FPGA family and device settings +# DE1 +FAMILY = "Cyclone II" +DEVICE = EP2C20F484C7 +PROGFILEEXT = sof +# DEMMK +# FAMILY = "MAX II" +# DEVICE = EPM2210F324C3 +# PROGFILEEXT = pof +# DE2 +#FAMILY = "Cyclone II" +#DEVICE = EP2C35F484C7 +#PROGFILEEXT = sof +# DE0 +#FAMILY = "Cyclone IV E" +#DEVICE = EP4CE22F17C6 +#PROGFILEEXT = sof + +# Here the VHDL files for synthesis are defined. +include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources + +# Add the toplevel fpga vhdl file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/$(PROJECT)_structure.vhd + +include ../makefile + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## DigitaltechnikPraktikum +## | +## +---src +## | and2gate_equation.vhd +## | invgate_equation.vhd +## | mux2to1_structure.vhd +## | or2gate_equation.vhd +## | t_mux2to1.vhd +## | de1_mux2to1_structure.vhd +## | +## +---sim +## | | makefile +## | | +## | \---mux2to1 +## | makefile +## | makefile.sources +## | +## +---pnr +## | | makefile +## | | +## | \---de1_mux2to1 +## | de1_mux2to1_pins.tcl +## | makefile +## | +## \---scripts +## de1_pin_assignments_minimumio.csv +## de1_pin_assignments_minimumio.tcl +## modelsim.ini +## quartus_project_settings.tcl +## ---------------------------------------------------------------------------- diff --git a/pnr/de1_pwm_incrementer/de1_pwm_incrementer_pins.tcl b/pnr/de1_pwm_incrementer/de1_pwm_incrementer_pins.tcl new file mode 100644 index 0000000..8eba56a --- /dev/null +++ b/pnr/de1_pwm_incrementer/de1_pwm_incrementer_pins.tcl @@ -0,0 +1,36 @@ +# assign pin locations to a quartus project + +#---------------------------------------------------------------------- +# Pin Assignments +set_location_assignment PIN_L1 -to CLOCK_50 +set_location_assignment PIN_R22 -to KEY +set_location_assignment PIN_H12 -to GPI_1[0] +set_location_assignment PIN_H13 -to GPI_1[1] +set_location_assignment PIN_U22 -to LEDG[0] +set_location_assignment PIN_U21 -to LEDG[1] +set_location_assignment PIN_J2 -to HEX0[0] +set_location_assignment PIN_J1 -to HEX0[1] +set_location_assignment PIN_H2 -to HEX0[2] +set_location_assignment PIN_H1 -to HEX0[3] +set_location_assignment PIN_F2 -to HEX0[4] +set_location_assignment PIN_F1 -to HEX0[5] +set_location_assignment PIN_E2 -to HEX0[6] +set_location_assignment PIN_E1 -to HEX1[0] +set_location_assignment PIN_H6 -to HEX1[1] +set_location_assignment PIN_H5 -to HEX1[2] +set_location_assignment PIN_H4 -to HEX1[3] +set_location_assignment PIN_G3 -to HEX1[4] +set_location_assignment PIN_D2 -to HEX1[5] +set_location_assignment PIN_D1 -to HEX1[6] +set_location_assignment PIN_R20 -to LEDR[0] +set_location_assignment PIN_R19 -to LEDR[1] +set_location_assignment PIN_U19 -to LEDR[2] +set_location_assignment PIN_Y19 -to LEDR[3] +set_location_assignment PIN_T18 -to LEDR[4] +set_location_assignment PIN_V19 -to LEDR[5] +set_location_assignment PIN_Y18 -to LEDR[6] +set_location_assignment PIN_U18 -to LEDR[7] +set_location_assignment PIN_H14 -to GPO_1[2] +set_location_assignment PIN_G15 -to GPO_1[3] +set_location_assignment PIN_E14 -to GPO_1[4] +# ---------------------------------------------------------------------------- diff --git a/pnr/de1_pwm_incrementer/makefile b/pnr/de1_pwm_incrementer/makefile new file mode 100644 index 0000000..c894956 --- /dev/null +++ b/pnr/de1_pwm_incrementer/makefile @@ -0,0 +1,55 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with Quartus, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# - assign variable SIM_PROJECT_NAME with the top level project name +# - add additional VHDL sources to SOURCE_FILES, if necessary +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd +################################################################### + +SIM_PROJECT_NAME = pwm_incrementer +PROJECT = de1_$(SIM_PROJECT_NAME) + +# Prototype Board FPGA family and device settings +# DE1 +FAMILY = "Cyclone II" +DEVICE = EP2C20F484C7 +PROGFILEEXT = sof +# DEMMK +# FAMILY = "MAX II" +# DEVICE = EPM2210F324C3 +# PROGFILEEXT = pof +# DE2 +#FAMILY = "Cyclone II" +#DEVICE = EP2C35F484C7 +#PROGFILEEXT = sof +# DE0 +#FAMILY = "Cyclone IV E" +#DEVICE = EP4CE22F17C6 +#PROGFILEEXT = sof + +# Here the VHDL files for synthesis are defined. +include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources + +# Add the toplevel fpga vhdl file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/binto7segment_truthtable.vhd \ +../../src/synchroniser_rtl.vhd \ +../../src/$(PROJECT)_structure.vhd + +include ../makefile + + diff --git a/pnr/de1_tone/de1_tone_pins.tcl b/pnr/de1_tone/de1_tone_pins.tcl new file mode 100644 index 0000000..e9c32ae --- /dev/null +++ b/pnr/de1_tone/de1_tone_pins.tcl @@ -0,0 +1,33 @@ +# Pin Configuration +set_location_assignment PIN_L1 -to CLOCK_50 +set_location_assignment PIN_R22 -to KEY0 +set_location_assignment PIN_A3 -to I2C_SCLK +set_location_assignment PIN_B3 -to I2C_SDAT +set_location_assignment PIN_A6 -to AUD_ADCLRCK +set_location_assignment PIN_B6 -to AUD_ADCDAT +set_location_assignment PIN_A5 -to AUD_DACLRCK +set_location_assignment PIN_B5 -to AUD_DACDAT +set_location_assignment PIN_B4 -to AUD_XCK +set_location_assignment PIN_A4 -to AUD_BCLK +set_location_assignment PIN_R20 -to LEDR[0] +set_location_assignment PIN_R19 -to LEDR[1] +set_location_assignment PIN_U19 -to LEDR[2] +set_location_assignment PIN_Y19 -to LEDR[3] +set_location_assignment PIN_T18 -to LEDR[4] +set_location_assignment PIN_V19 -to LEDR[5] +set_location_assignment PIN_Y18 -to LEDR[6] +set_location_assignment PIN_U18 -to LEDR[7] +set_location_assignment PIN_R18 -to LEDR[8] +set_location_assignment PIN_R17 -to LEDR[9] +set_location_assignment PIN_L22 -to SW[0] +set_location_assignment PIN_L21 -to SW[1] +set_location_assignment PIN_M22 -to SW[2] +set_location_assignment PIN_V12 -to SW[3] +set_location_assignment PIN_W12 -to SW[4] +set_location_assignment PIN_U12 -to SW[5] +set_location_assignment PIN_U11 -to SW[6] +set_location_assignment PIN_M2 -to SW[7] +set_location_assignment PIN_M1 -to SW[8] +set_location_assignment PIN_L2 -to SW[9] + + diff --git a/pnr/de1_tone/makefile b/pnr/de1_tone/makefile new file mode 100644 index 0000000..e9cf6e6 --- /dev/null +++ b/pnr/de1_tone/makefile @@ -0,0 +1,14 @@ +SIM_PROJECT_NAME = de1_tone +PROJECT = $(SIM_PROJECT_NAME) + +# Here the VHDL files for synthesis are defined. +include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources + +# Add the toplevel fpga vhdl file +SOURCE_FILES = $(SYN_SOURCE_FILES) + +FAMILY = "Cyclone II" +DEVICE = EP2C20F484C7 +PROGFILEEXT = sof + +include ../makefile diff --git a/pnr/makefile b/pnr/makefile new file mode 100644 index 0000000..ffc1cf0 --- /dev/null +++ b/pnr/makefile @@ -0,0 +1,92 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with Quartus, +## it is based on a design directory structure shown at +## the end of this file. +## ---------------------------------------------------------------------------- + +################################################################### +# Main Targets +# +################################################################### + +help: + @echo '"make" does intentionally nothing. Type:' + @echo ' "make qproject" to create quartus project only' + @echo ' "make compile" to synthesize the design' + @echo ' "make prog" to configure programmable device' + @echo ' "make quartus" to start quartus graphical user interface' + @echo ' "make clean" to remove all generated files' + +qproject: $(PROJECT).qpf + +$(PROJECT).sdc: + # create a default timing constraint file assuming CLOCK_50 + echo "create_clock -period 20.000 -name CLOCK_50 [get_ports CLOCK_50]" > $(PROJECT).sdc + echo "set_input_delay -clock CLOCK_50 2 [all_inputs]" >> $(PROJECT).sdc + echo "set_output_delay -clock CLOCK_50 2 [all_outputs]" >> $(PROJECT).sdc + +$(PROJECT).qpf: $(SOURCE_FILES) ../../scripts/create_quartus_project_settings.tcl $(PROJECT)_pins.tcl $(PROJECT).sdc + # assign VHDL design files + rm -rf quartus_vhdl_source_files.tcl + for source_file in $(SOURCE_FILES); do \ + echo set_global_assignment -name VHDL_FILE $$source_file >> quartus_vhdl_source_files.tcl; \ + done + # just create a quartus project + quartus_sh -t ../../scripts/create_quartus_project_settings.tcl -projectname $(PROJECT) -family $(FAMILY) -device $(DEVICE) + +compile: $(PROJECT).qpf flowsummary.log + +flowsummary.log: $(SOURCE_FILES) + quartus_sh -t ../../scripts/quartus_project_flow.tcl -projectname $(PROJECT) -process compile + +prog: $(PROJECT).qpf flowsummary.log + quartus_pgm -c USB-Blaster --mode jtag --operation="p;$(PROJECT).$(PROGFILEEXT)" + +quartus: $(PROJECT).qpf + # start quartus gui + quartus $(PROJECT).qpf & + +clean: + rm -rf *.rpt *.chg *.log quartus_vhdl_source_files.tcl *.htm *.eqn *.pin *.sof *.pof db incremental_db *.qpf *.qsf *.summary $(PROJECT).* *~ + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## DigitaltechnikPraktikum +## | +## +---src +## | and2gate_equation.vhd +## | invgate_equation.vhd +## | mux2to1_structure.vhd +## | or2gate_equation.vhd +## | t_mux2to1.vhd +## | de1_mux2to1_structure.vhd +## | +## +---sim +## | | makefile +## | | +## | \---mux2to1 +## | makefile +## | makefile.sources +## | +## +---pnr +## | | makefile +## | | +## | \---de1_mux2to1 +## | de1_mux2to1_pins.tcl +## | makefile +## | +## \---scripts +## de1_pin_assignments_minimumio.csv +## de1_pin_assignments_minimumio.tcl +## modelsim.ini +## quartus_project_settings.tcl +## ---------------------------------------------------------------------------- + diff --git a/scripts/create_quartus_project_settings.tcl b/scripts/create_quartus_project_settings.tcl new file mode 100644 index 0000000..ab55593 --- /dev/null +++ b/scripts/create_quartus_project_settings.tcl @@ -0,0 +1,84 @@ +## ---------------------------------------------------------------------------- +## Script : create_quartus_project_settings.tcl +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, F. Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: create a quartus project with default settings for device, +## unused pins, ... +## expects project name as command line parameter +## e.g. +## quartus_sh -t create_quartus_project_settings.tcl -projectname de1_mux2to1 +## -family "Cyclone II" -device EP2C20F484C7 +## ---------------------------------------------------------------------------- +## Revisions : see end of file +## ---------------------------------------------------------------------------- + +package require cmdline +# Load Quartus II Tcl Project package +package require ::quartus::project + +# ---------------------------------------------------------------------------- +# Declare command line parameters +# ---------------------------------------------------------------------------- +set parameters { + {projectname.arg "" "Project Name"} + {family.arg "" "FPGA Family"} + {device.arg "" "FPGA Device"} +} +array set arg [::cmdline::getoptions argv $parameters] + +# ---------------------------------------------------------------------------- +# Verify required paramters +# ---------------------------------------------------------------------------- +set requiredParameters {projectname family device} +foreach parameter $requiredParameters { + if {$arg($parameter) == ""} { + puts stderr "Missing required parameter: -$parameter" + exit 1 + } +} + + + # ---------------------------------------------------------------------------- + # Create project + # ---------------------------------------------------------------------------- + project_new $arg(projectname) -overwrite + + # ---------------------------------------------------------------------------- + # Assign family, device, and top-level file + # ---------------------------------------------------------------------------- + set_global_assignment -name FAMILY $arg(family) + set_global_assignment -name DEVICE $arg(device) + + # ---------------------------------------------------------------------------- + # Default settings + # ---------------------------------------------------------------------------- + set_global_assignment -name USE_CONFIGURATION_DEVICE ON + set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" + set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 + + # ---------------------------------------------------------------------------- + # Design files + # ---------------------------------------------------------------------------- + #set_global_assignment -name VHDL_FILE ../src/e_cntdnmodm.vhd + #set_global_assignment -name VHDL_FILE ../src/a_cntdnmodm_rtl.vhd + source quartus_vhdl_source_files.tcl + + # ---------------------------------------------------------------------------- + # Pin Assignments + # ---------------------------------------------------------------------------- + # set_location_assignment PIN_L1 -to CLOCK_50 + source $arg(projectname)_pins.tcl + + # ---------------------------------------------------------------------------- + # Close project + # ---------------------------------------------------------------------------- + project_close + + +## ---------------------------------------------------------------------------- +## Revisions: +## ---------- +## $Id:$ +## ---------------------------------------------------------------------------- diff --git a/scripts/de1_pin_assignments_minimumio.tcl b/scripts/de1_pin_assignments_minimumio.tcl new file mode 100644 index 0000000..d9d3470 --- /dev/null +++ b/scripts/de1_pin_assignments_minimumio.tcl @@ -0,0 +1,282 @@ +set_location_assignment PIN_D12 -to CLOCK_27[0] +set_location_assignment PIN_E12 -to CLOCK_27[1] +set_location_assignment PIN_B12 -to CLOCK_24[0] +set_location_assignment PIN_A12 -to CLOCK_24[1] +set_location_assignment PIN_L1 -to CLOCK_50 +set_location_assignment PIN_M21 -to EXT_CLOCK +set_location_assignment PIN_R22 -to KEY[0] +set_location_assignment PIN_R21 -to KEY[1] +set_location_assignment PIN_T22 -to KEY[2] +set_location_assignment PIN_T21 -to KEY[3] +set_location_assignment PIN_L22 -to SW[0] +set_location_assignment PIN_L21 -to SW[1] +set_location_assignment PIN_M22 -to SW[2] +set_location_assignment PIN_V12 -to SW[3] +set_location_assignment PIN_W12 -to SW[4] +set_location_assignment PIN_U12 -to SW[5] +set_location_assignment PIN_U11 -to SW[6] +set_location_assignment PIN_M2 -to SW[7] +set_location_assignment PIN_M1 -to SW[8] +set_location_assignment PIN_L2 -to SW[9] +set_location_assignment PIN_R20 -to LEDR[0] +set_location_assignment PIN_R19 -to LEDR[1] +set_location_assignment PIN_U19 -to LEDR[2] +set_location_assignment PIN_Y19 -to LEDR[3] +set_location_assignment PIN_T18 -to LEDR[4] +set_location_assignment PIN_V19 -to LEDR[5] +set_location_assignment PIN_Y18 -to LEDR[6] +set_location_assignment PIN_U18 -to LEDR[7] +set_location_assignment PIN_R18 -to LEDR[8] +set_location_assignment PIN_R17 -to LEDR[9] +set_location_assignment PIN_U22 -to LEDG[0] +set_location_assignment PIN_U21 -to LEDG[1] +set_location_assignment PIN_V22 -to LEDG[2] +set_location_assignment PIN_V21 -to LEDG[3] +set_location_assignment PIN_W22 -to LEDG[4] +set_location_assignment PIN_W21 -to LEDG[5] +set_location_assignment PIN_Y22 -to LEDG[6] +set_location_assignment PIN_Y21 -to LEDG[7] +set_location_assignment PIN_J2 -to HEX0[0] +set_location_assignment PIN_J1 -to HEX0[1] +set_location_assignment PIN_H2 -to HEX0[2] +set_location_assignment PIN_H1 -to HEX0[3] +set_location_assignment PIN_F2 -to HEX0[4] +set_location_assignment PIN_F1 -to HEX0[5] +set_location_assignment PIN_E2 -to HEX0[6] +set_location_assignment PIN_E1 -to HEX1[0] +set_location_assignment PIN_H6 -to HEX1[1] +set_location_assignment PIN_H5 -to HEX1[2] +set_location_assignment PIN_H4 -to HEX1[3] +set_location_assignment PIN_G3 -to HEX1[4] +set_location_assignment PIN_D2 -to HEX1[5] +set_location_assignment PIN_D1 -to HEX1[6] +set_location_assignment PIN_G5 -to HEX2[0] +set_location_assignment PIN_G6 -to HEX2[1] +set_location_assignment PIN_C2 -to HEX2[2] +set_location_assignment PIN_C1 -to HEX2[3] +set_location_assignment PIN_E3 -to HEX2[4] +set_location_assignment PIN_E4 -to HEX2[5] +set_location_assignment PIN_D3 -to HEX2[6] +set_location_assignment PIN_F4 -to HEX3[0] +set_location_assignment PIN_D5 -to HEX3[1] +set_location_assignment PIN_D6 -to HEX3[2] +set_location_assignment PIN_J4 -to HEX3[3] +set_location_assignment PIN_L8 -to HEX3[4] +set_location_assignment PIN_F3 -to HEX3[5] +set_location_assignment PIN_D4 -to HEX3[6] +set_location_assignment PIN_A13 -to GPI_0[0] +set_location_assignment PIN_B13 -to GPI_0[1] +set_location_assignment PIN_A14 -to GPI_0[2] +set_location_assignment PIN_B14 -to GPI_0[3] +set_location_assignment PIN_A15 -to GPI_0[4] +set_location_assignment PIN_B15 -to GPI_0[5] +set_location_assignment PIN_A16 -to GPI_0[6] +set_location_assignment PIN_B16 -to GPI_0[7] +set_location_assignment PIN_A17 -to GPI_0[8] +set_location_assignment PIN_B17 -to GPI_0[9] +set_location_assignment PIN_A18 -to GPI_0[10] +set_location_assignment PIN_B18 -to GPI_0[11] +set_location_assignment PIN_A19 -to GPI_0[12] +set_location_assignment PIN_B19 -to GPI_0[13] +set_location_assignment PIN_A20 -to GPI_0[14] +set_location_assignment PIN_B20 -to GPI_0[15] +set_location_assignment PIN_C21 -to GPI_0[16] +set_location_assignment PIN_C22 -to GPI_0[17] +set_location_assignment PIN_D21 -to GPI_0[18] +set_location_assignment PIN_D22 -to GPI_0[19] +set_location_assignment PIN_E21 -to GPI_0[20] +set_location_assignment PIN_E22 -to GPI_0[21] +set_location_assignment PIN_F21 -to GPI_0[22] +set_location_assignment PIN_F22 -to GPI_0[23] +set_location_assignment PIN_G21 -to GPI_0[24] +set_location_assignment PIN_G22 -to GPI_0[25] +set_location_assignment PIN_J21 -to GPI_0[26] +set_location_assignment PIN_J22 -to GPI_0[27] +set_location_assignment PIN_K21 -to GPI_0[28] +set_location_assignment PIN_K22 -to GPI_0[29] +set_location_assignment PIN_J19 -to GPI_0[30] +set_location_assignment PIN_J20 -to GPI_0[31] +set_location_assignment PIN_J18 -to GPI_0[32] +set_location_assignment PIN_K20 -to GPI_0[33] +set_location_assignment PIN_L19 -to GPI_0[34] +set_location_assignment PIN_L18 -to GPI_0[35] +set_location_assignment PIN_H12 -to GPI_1[0] +set_location_assignment PIN_H13 -to GPI_1[1] +set_location_assignment PIN_H14 -to GPI_1[2] +set_location_assignment PIN_G15 -to GPI_1[3] +set_location_assignment PIN_E14 -to GPI_1[4] +set_location_assignment PIN_E15 -to GPI_1[5] +set_location_assignment PIN_F15 -to GPI_1[6] +set_location_assignment PIN_G16 -to GPI_1[7] +set_location_assignment PIN_F12 -to GPI_1[8] +set_location_assignment PIN_F13 -to GPI_1[9] +set_location_assignment PIN_C14 -to GPI_1[10] +set_location_assignment PIN_D14 -to GPI_1[11] +set_location_assignment PIN_D15 -to GPI_1[12] +set_location_assignment PIN_D16 -to GPI_1[13] +set_location_assignment PIN_C17 -to GPI_1[14] +set_location_assignment PIN_C18 -to GPI_1[15] +set_location_assignment PIN_C19 -to GPI_1[16] +set_location_assignment PIN_C20 -to GPI_1[17] +set_location_assignment PIN_D19 -to GPI_1[18] +set_location_assignment PIN_D20 -to GPI_1[19] +set_location_assignment PIN_E20 -to GPI_1[20] +set_location_assignment PIN_F20 -to GPI_1[21] +set_location_assignment PIN_E19 -to GPI_1[22] +set_location_assignment PIN_E18 -to GPI_1[23] +set_location_assignment PIN_G20 -to GPI_1[24] +set_location_assignment PIN_G18 -to GPI_1[25] +set_location_assignment PIN_G17 -to GPI_1[26] +set_location_assignment PIN_H17 -to GPI_1[27] +set_location_assignment PIN_J15 -to GPI_1[28] +set_location_assignment PIN_H18 -to GPI_1[29] +set_location_assignment PIN_N22 -to GPI_1[30] +set_location_assignment PIN_N21 -to GPI_1[31] +set_location_assignment PIN_P15 -to GPI_1[32] +set_location_assignment PIN_N15 -to GPI_1[33] +set_location_assignment PIN_P17 -to GPI_1[34] +set_location_assignment PIN_P18 -to GPI_1[35] +set_location_assignment PIN_A13 -to GPO_0[0] +set_location_assignment PIN_B13 -to GPO_0[1] +set_location_assignment PIN_A14 -to GPO_0[2] +set_location_assignment PIN_B14 -to GPO_0[3] +set_location_assignment PIN_A15 -to GPO_0[4] +set_location_assignment PIN_B15 -to GPO_0[5] +set_location_assignment PIN_A16 -to GPO_0[6] +set_location_assignment PIN_B16 -to GPO_0[7] +set_location_assignment PIN_A17 -to GPO_0[8] +set_location_assignment PIN_B17 -to GPO_0[9] +set_location_assignment PIN_A18 -to GPO_0[10] +set_location_assignment PIN_B18 -to GPO_0[11] +set_location_assignment PIN_A19 -to GPO_0[12] +set_location_assignment PIN_B19 -to GPO_0[13] +set_location_assignment PIN_A20 -to GPO_0[14] +set_location_assignment PIN_B20 -to GPO_0[15] +set_location_assignment PIN_C21 -to GPO_0[16] +set_location_assignment PIN_C22 -to GPO_0[17] +set_location_assignment PIN_D21 -to GPO_0[18] +set_location_assignment PIN_D22 -to GPO_0[19] +set_location_assignment PIN_E21 -to GPO_0[20] +set_location_assignment PIN_E22 -to GPO_0[21] +set_location_assignment PIN_F21 -to GPO_0[22] +set_location_assignment PIN_F22 -to GPO_0[23] +set_location_assignment PIN_G21 -to GPO_0[24] +set_location_assignment PIN_G22 -to GPO_0[25] +set_location_assignment PIN_J21 -to GPO_0[26] +set_location_assignment PIN_J22 -to GPO_0[27] +set_location_assignment PIN_K21 -to GPO_0[28] +set_location_assignment PIN_K22 -to GPO_0[29] +set_location_assignment PIN_J19 -to GPO_0[30] +set_location_assignment PIN_J20 -to GPO_0[31] +set_location_assignment PIN_J18 -to GPO_0[32] +set_location_assignment PIN_K20 -to GPO_0[33] +set_location_assignment PIN_L19 -to GPO_0[34] +set_location_assignment PIN_L18 -to GPO_0[35] +set_location_assignment PIN_H12 -to GPO_1[0] +set_location_assignment PIN_H13 -to GPO_1[1] +set_location_assignment PIN_H14 -to GPO_1[2] +set_location_assignment PIN_G15 -to GPO_1[3] +set_location_assignment PIN_E14 -to GPO_1[4] +set_location_assignment PIN_E15 -to GPO_1[5] +set_location_assignment PIN_F15 -to GPO_1[6] +set_location_assignment PIN_G16 -to GPO_1[7] +set_location_assignment PIN_F12 -to GPO_1[8] +set_location_assignment PIN_F13 -to GPO_1[9] +set_location_assignment PIN_C14 -to GPO_1[10] +set_location_assignment PIN_D14 -to GPO_1[11] +set_location_assignment PIN_D15 -to GPO_1[12] +set_location_assignment PIN_D16 -to GPO_1[13] +set_location_assignment PIN_C17 -to GPO_1[14] +set_location_assignment PIN_C18 -to GPO_1[15] +set_location_assignment PIN_C19 -to GPO_1[16] +set_location_assignment PIN_C20 -to GPO_1[17] +set_location_assignment PIN_D19 -to GPO_1[18] +set_location_assignment PIN_D20 -to GPO_1[19] +set_location_assignment PIN_E20 -to GPO_1[20] +set_location_assignment PIN_F20 -to GPO_1[21] +set_location_assignment PIN_E19 -to GPO_1[22] +set_location_assignment PIN_E18 -to GPO_1[23] +set_location_assignment PIN_G20 -to GPO_1[24] +set_location_assignment PIN_G18 -to GPO_1[25] +set_location_assignment PIN_G17 -to GPO_1[26] +set_location_assignment PIN_H17 -to GPO_1[27] +set_location_assignment PIN_J15 -to GPO_1[28] +set_location_assignment PIN_H18 -to GPO_1[29] +set_location_assignment PIN_N22 -to GPO_1[30] +set_location_assignment PIN_N21 -to GPO_1[31] +set_location_assignment PIN_P15 -to GPO_1[32] +set_location_assignment PIN_N15 -to GPO_1[33] +set_location_assignment PIN_P17 -to GPO_1[34] +set_location_assignment PIN_P18 -to GPO_1[35] +set_location_assignment PIN_A13 -to GPIO_0[0] +set_location_assignment PIN_B13 -to GPIO_0[1] +set_location_assignment PIN_A14 -to GPIO_0[2] +set_location_assignment PIN_B14 -to GPIO_0[3] +set_location_assignment PIN_A15 -to GPIO_0[4] +set_location_assignment PIN_B15 -to GPIO_0[5] +set_location_assignment PIN_A16 -to GPIO_0[6] +set_location_assignment PIN_B16 -to GPIO_0[7] +set_location_assignment PIN_A17 -to GPIO_0[8] +set_location_assignment PIN_B17 -to GPIO_0[9] +set_location_assignment PIN_A18 -to GPIO_0[10] +set_location_assignment PIN_B18 -to GPIO_0[11] +set_location_assignment PIN_A19 -to GPIO_0[12] +set_location_assignment PIN_B19 -to GPIO_0[13] +set_location_assignment PIN_A20 -to GPIO_0[14] +set_location_assignment PIN_B20 -to GPIO_0[15] +set_location_assignment PIN_C21 -to GPIO_0[16] +set_location_assignment PIN_C22 -to GPIO_0[17] +set_location_assignment PIN_D21 -to GPIO_0[18] +set_location_assignment PIN_D22 -to GPIO_0[19] +set_location_assignment PIN_E21 -to GPIO_0[20] +set_location_assignment PIN_E22 -to GPIO_0[21] +set_location_assignment PIN_F21 -to GPIO_0[22] +set_location_assignment PIN_F22 -to GPIO_0[23] +set_location_assignment PIN_G21 -to GPIO_0[24] +set_location_assignment PIN_G22 -to GPIO_0[25] +set_location_assignment PIN_J21 -to GPIO_0[26] +set_location_assignment PIN_J22 -to GPIO_0[27] +set_location_assignment PIN_K21 -to GPIO_0[28] +set_location_assignment PIN_K22 -to GPIO_0[29] +set_location_assignment PIN_J19 -to GPIO_0[30] +set_location_assignment PIN_J20 -to GPIO_0[31] +set_location_assignment PIN_J18 -to GPIO_0[32] +set_location_assignment PIN_K20 -to GPIO_0[33] +set_location_assignment PIN_L19 -to GPIO_0[34] +set_location_assignment PIN_L18 -to GPIO_0[35] +set_location_assignment PIN_H12 -to GPIO_1[0] +set_location_assignment PIN_H13 -to GPIO_1[1] +set_location_assignment PIN_H14 -to GPIO_1[2] +set_location_assignment PIN_G15 -to GPIO_1[3] +set_location_assignment PIN_E14 -to GPIO_1[4] +set_location_assignment PIN_E15 -to GPIO_1[5] +set_location_assignment PIN_F15 -to GPIO_1[6] +set_location_assignment PIN_G16 -to GPIO_1[7] +set_location_assignment PIN_F12 -to GPIO_1[8] +set_location_assignment PIN_F13 -to GPIO_1[9] +set_location_assignment PIN_C14 -to GPIO_1[10] +set_location_assignment PIN_D14 -to GPIO_1[11] +set_location_assignment PIN_D15 -to GPIO_1[12] +set_location_assignment PIN_D16 -to GPIO_1[13] +set_location_assignment PIN_C17 -to GPIO_1[14] +set_location_assignment PIN_C18 -to GPIO_1[15] +set_location_assignment PIN_C19 -to GPIO_1[16] +set_location_assignment PIN_C20 -to GPIO_1[17] +set_location_assignment PIN_D19 -to GPIO_1[18] +set_location_assignment PIN_D20 -to GPIO_1[19] +set_location_assignment PIN_E20 -to GPIO_1[20] +set_location_assignment PIN_F20 -to GPIO_1[21] +set_location_assignment PIN_E19 -to GPIO_1[22] +set_location_assignment PIN_E18 -to GPIO_1[23] +set_location_assignment PIN_G20 -to GPIO_1[24] +set_location_assignment PIN_G18 -to GPIO_1[25] +set_location_assignment PIN_G17 -to GPIO_1[26] +set_location_assignment PIN_H17 -to GPIO_1[27] +set_location_assignment PIN_J15 -to GPIO_1[28] +set_location_assignment PIN_H18 -to GPIO_1[29] +set_location_assignment PIN_N22 -to GPIO_1[30] +set_location_assignment PIN_N21 -to GPIO_1[31] +set_location_assignment PIN_P15 -to GPIO_1[32] +set_location_assignment PIN_N15 -to GPIO_1[33] +set_location_assignment PIN_P17 -to GPIO_1[34] +set_location_assignment PIN_P18 -to GPIO_1[35] \ No newline at end of file diff --git a/scripts/modelsim.ini b/scripts/modelsim.ini new file mode 100644 index 0000000..d3412fe --- /dev/null +++ b/scripts/modelsim.ini @@ -0,0 +1,351 @@ +;; ---------------------------------------------------------------------------- +;; Script : modelsim.ini +;; ---------------------------------------------------------------------------- +;; Author : Johann Faerber +;; Company : University of Applied Sciences Augsburg +;; ---------------------------------------------------------------------------- +;; Description: original version modified +;; - deleted all VHDL and Verilog device libraries +;; - modified compiler standard to VHDL93 = 2008 +;; ---------------------------------------------------------------------------- +;; Revisions : see end of file +;; ---------------------------------------------------------------------------- + +; Copyright 1991-2009 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +std = $MODEL_TECH/../std +ieee = $MODEL_TECH/../ieee +verilog = $MODEL_TECH/../verilog +vital2000 = $MODEL_TECH/../vital2000 +std_developerskit = $MODEL_TECH/../std_developerskit +synopsys = $MODEL_TECH/../synopsys +modelsim_lib = $MODEL_TECH/../modelsim_lib +sv_std = $MODEL_TECH/../sv_std + +; Altera Primitive libraries +; +; VHDL Section +; +altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf +altera = $MODEL_TECH/../altera/vhdl/altera +altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim +lpm = $MODEL_TECH/../altera/vhdl/220model +220model = $MODEL_TECH/../altera/vhdl/220model + +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Default or value of 3 or 2008 for VHDL-2008. +VHDL93 = 2008 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +[vlog] + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Turn on incremental compilation of modules. Default is off. +; Incremental = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +[vsim] +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ns + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 100 + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Directive to license manager: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; nomgc Do not look for Mentor Graphics Licenses +; nomti Do not look for Model Technology Licenses +; noqueue Do not wait in the license queue when a license isn't available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license +; License = plus + +; Stop the simulator after a VHDL/Verilog assertion message +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Assertion Message Format +; %S - Severity Level +; %R - Report Message +; %T - Time of assertion +; %D - Delta +; %I - Instance or Region pathname (if available) +; %% - print '%' character +; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Assertion File - alternate file for storing VHDL/Verilog assertion messages +; AssertFile = assert.log + +; Default radix for all windows and commands... +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example, sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings from the std_logic_arith, std_logic_unsigned +; and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from the IEEE numeric_std and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Control the format of the (VHDL) FOR generate statement label +; for each iteration. Do not quote it. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate_label; the %d represents the generate parameter value +; at a particular generate iteration (this is the position number if +; the generate parameter is of an enumeration type). Embedded whitespace +; is allowed (but discouraged); leading and trailing whitespace is ignored. +; Application of the format must result in a unique scope name over all +; such names in the design so that name lookup can function properly. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave +; DefaultRestartOptions = -force + +; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs +; (> 500 megabyte memory footprint). Default is disabled. +; Specify number of megabytes to lock. +; LockedMemory = 1000 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Automatic SDF compilation +; Disables automatic compilation of SDF files in flows that support it. +; Default is on, uncomment to turn off. +; NoAutoSDFCompile = 1 + +[lmc] + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; Examples: +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of elaboration/runtime messages. +; The default is to have messages appear in the transcript and +; recorded in the wlf file (messages that are recorded in the +; wlf file can be viewed in the MsgViewer). The other settings +; are to send messages only to the transcript or only to the +; wlf file. The valid values are +; both {default} +; tran {transcript only} +; wlf {wlf file only} +; msgmode = both + +;; ---------------------------------------------------------------------------- +;; Revisions: +;; ---------- +;; $Id:$ +;; ---------------------------------------------------------------------------- diff --git a/scripts/quartus_project_flow.tcl b/scripts/quartus_project_flow.tcl new file mode 100644 index 0000000..2894685 --- /dev/null +++ b/scripts/quartus_project_flow.tcl @@ -0,0 +1,84 @@ +## ---------------------------------------------------------------------------- +## Script : quartus_project_flow.tcl +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, F. Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: executes process steps in a quartus project +## depending on the parameter process +## expects project name as command line parameter +## e.g. +## quartus_sh -t quartus_project_flow.tcl -projectname de1_mux2to1 +## -process compile +## ---------------------------------------------------------------------------- +## Revisions : see end of file +## ---------------------------------------------------------------------------- + +package require cmdline +# Load Quartus II Tcl Project package +package require ::quartus::project + +# ---------------------------------------------------------------------------- +# Declare command line parameters +# ---------------------------------------------------------------------------- +set parameters { + {projectname.arg "" "Project Name"} + {process.arg "" "Process Step"} +} +array set arg [::cmdline::getoptions argv $parameters] + +# ---------------------------------------------------------------------------- +# Verify required paramters +# ---------------------------------------------------------------------------- +set requiredParameters {projectname process} +foreach parameter $requiredParameters { + if {$arg($parameter) == ""} { + puts stderr "Missing required parameter: -$parameter" + exit 1 + } +} + +# ---------------------------------------------------------------------------- +# Check, if project exists +# ---------------------------------------------------------------------------- +if { ![project_exists $arg(projectname)] } { + post_message -type error "Project $arg(projectname) does not exist" + exit +} + # ---------------------------------------------------------------------------- + # Open project + # ---------------------------------------------------------------------------- + project_open $arg(projectname) + + # ---------------------------------------------------------------------------- + # Run specified design flow by parameter -process + # ---------------------------------------------------------------------------- + load_package flow + + if { $arg(process) == "compile" } { + execute_flow -compile + } elseif { $arg(process) == "analysis_and_elaboration" } { + execute_flow -analysis_and_elaboration + } else { + post_message -type error "Process step $arg(process) not allowed !" + exit + } + + # ---------------------------------------------------------------------------- + # Write Reports + # ---------------------------------------------------------------------------- + load_package report + load_report $arg(projectname) + write_report_panel -file flowsummary.log "Flow Summary" + + # ---------------------------------------------------------------------------- + # Close project + # ---------------------------------------------------------------------------- + project_close + + +## ---------------------------------------------------------------------------- +## Revisions: +## ---------- +## $Id:$ +## ---------------------------------------------------------------------------- diff --git a/sim/and2gate/makefile b/sim/and2gate/makefile new file mode 100644 index 0000000..e523dc3 --- /dev/null +++ b/sim/and2gate/makefile @@ -0,0 +1,67 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with ModelSim, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# assign variable PROJECT with the top level project name +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of testbench t_$(PROJECT).vhd +################################################################### + +PROJECT = and2gate + +include ./makefile.sources + +# Add here the testbench file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/t_$(PROJECT).vhd + +include ../makefile + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## DigitaltechnikPraktikum +## | +## +---src +## | and2gate_equation.vhd +## | invgate_equation.vhd +## | mux2to1_structure.vhd +## | or2gate_equation.vhd +## | t_mux2to1.vhd +## | de1_mux2to1_structure.vhd +## | +## +---sim +## | | makefile +## | | +## | \---mux2to1 +## | makefile +## | makefile.sources +## | +## +---pnr +## | | makefile +## | | +## | \---de1_mux2to1 +## | de1_mux2to1_pins.tcl +## | makefile +## | +## \---scripts +## de1_pin_assignments_minimumio.csv +## de1_pin_assignments_minimumio.tcl +## modelsim.ini +## quartus_project_settings.tcl +## ---------------------------------------------------------------------------- + diff --git a/sim/and2gate/makefile.sources b/sim/and2gate/makefile.sources new file mode 100644 index 0000000..cac390c --- /dev/null +++ b/sim/and2gate/makefile.sources @@ -0,0 +1,17 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/and2gate_equation.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/cntdn/makefile b/sim/cntdn/makefile new file mode 100644 index 0000000..1be2176 --- /dev/null +++ b/sim/cntdn/makefile @@ -0,0 +1,67 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with ModelSim, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# assign variable PROJECT with the top level project name +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of testbench t_$(PROJECT).vhd +################################################################### + +PROJECT = cntdn + +include ./makefile.sources + +# Add here the testbench file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/t_$(PROJECT).vhd + +include ../makefile + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## DigitaltechnikPraktikum +## | +## +---src +## | and2gate_equation.vhd +## | invgate_equation.vhd +## | mux2to1_structure.vhd +## | or2gate_equation.vhd +## | t_mux2to1.vhd +## | de1_mux2to1_structure.vhd +## | +## +---sim +## | | makefile +## | | +## | \---mux2to1 +## | makefile +## | makefile.sources +## | +## +---pnr +## | | makefile +## | | +## | \---de1_mux2to1 +## | de1_mux2to1_pins.tcl +## | makefile +## | +## \---scripts +## de1_pin_assignments_minimumio.csv +## de1_pin_assignments_minimumio.tcl +## modelsim.ini +## quartus_project_settings.tcl +## ---------------------------------------------------------------------------- + diff --git a/sim/cntdn/makefile.sources b/sim/cntdn/makefile.sources new file mode 100644 index 0000000..af4874d --- /dev/null +++ b/sim/cntdn/makefile.sources @@ -0,0 +1,17 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/cntdn_rtl.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/cntdnmodm/makefile b/sim/cntdnmodm/makefile new file mode 100644 index 0000000..060a0ad --- /dev/null +++ b/sim/cntdnmodm/makefile @@ -0,0 +1,67 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with ModelSim, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# assign variable PROJECT with the top level project name +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of testbench t_$(PROJECT).vhd +################################################################### + +PROJECT = cntdnmodm + +include ./makefile.sources + +# Add here the testbench file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/t_$(PROJECT).vhd + +include ../makefile + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## DigitaltechnikPraktikum +## | +## +---src +## | and2gate_equation.vhd +## | invgate_equation.vhd +## | mux2to1_structure.vhd +## | or2gate_equation.vhd +## | t_mux2to1.vhd +## | de1_mux2to1_structure.vhd +## | +## +---sim +## | | makefile +## | | +## | \---mux2to1 +## | makefile +## | makefile.sources +## | +## +---pnr +## | | makefile +## | | +## | \---de1_mux2to1 +## | de1_mux2to1_pins.tcl +## | makefile +## | +## \---scripts +## de1_pin_assignments_minimumio.csv +## de1_pin_assignments_minimumio.tcl +## modelsim.ini +## quartus_project_settings.tcl +## ---------------------------------------------------------------------------- + diff --git a/sim/cntdnmodm/makefile.sources b/sim/cntdnmodm/makefile.sources new file mode 100644 index 0000000..4752d19 --- /dev/null +++ b/sim/cntdnmodm/makefile.sources @@ -0,0 +1,17 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/cntdnmodm_rtl.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/de1_audio/makefile b/sim/de1_audio/makefile new file mode 100644 index 0000000..99b022e --- /dev/null +++ b/sim/de1_audio/makefile @@ -0,0 +1,10 @@ +PROJECT = de1_audio + +include ./makefile.sources + +# Add here the testbench file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/t_$(PROJECT).vhd + +include ../makefile + diff --git a/sim/de1_audio/makefile.sources b/sim/de1_audio/makefile.sources new file mode 100644 index 0000000..ee901cc --- /dev/null +++ b/sim/de1_audio/makefile.sources @@ -0,0 +1,14 @@ +SYN_SOURCE_FILES = \ +../../src/adcintf.vhd \ +../../src/bclk.vhd \ +../../src/dacintf.vhd \ +../../src/fsgen.vhd \ +../../src/i2c_sub.vhd \ +../../src/i2c.vhd \ +../../src/i2c_write.vhd \ +../../src/mclk.vhd \ +../../src/memory.vhd \ +../../src/ringbuf.vhd \ +../../src/audio.vhd \ +../../src/de1_audio.vhd + diff --git a/sim/de1_tone/makefile b/sim/de1_tone/makefile new file mode 100644 index 0000000..7eb97d3 --- /dev/null +++ b/sim/de1_tone/makefile @@ -0,0 +1,9 @@ +PROJECT = de1_tone + +include ./makefile.sources + +# Add here the testbench file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/t_$(PROJECT).vhd + +include ../makefile diff --git a/sim/de1_tone/makefile.sources b/sim/de1_tone/makefile.sources new file mode 100644 index 0000000..46993a5 --- /dev/null +++ b/sim/de1_tone/makefile.sources @@ -0,0 +1,13 @@ +SYN_SOURCE_FILES = \ +../../src/adcintf.vhd \ +../../src/bclk.vhd \ +../../src/dacintf.vhd \ +../../src/fsgen.vhd \ +../../src/i2c_sub.vhd \ +../../src/i2c.vhd \ +../../src/i2c_write.vhd \ +../../src/mclk.vhd \ +../../src/audio.vhd \ +../../src/tone_rtl.vhd \ +../../src/de1_tone.vhd + diff --git a/sim/falling_edge_detector/makefile b/sim/falling_edge_detector/makefile new file mode 100644 index 0000000..48792e4 --- /dev/null +++ b/sim/falling_edge_detector/makefile @@ -0,0 +1,67 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with ModelSim, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# assign variable PROJECT with the top level project name +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of testbench t_$(PROJECT).vhd +################################################################### + +PROJECT = falling_edge_detector + +include ./makefile.sources + +# Add here the testbench file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/t_$(PROJECT).vhd + +include ../makefile + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## DigitaltechnikPraktikum +## | +## +---src +## | and2gate_equation.vhd +## | invgate_equation.vhd +## | mux2to1_structure.vhd +## | or2gate_equation.vhd +## | t_mux2to1.vhd +## | de1_mux2to1_structure.vhd +## | +## +---sim +## | | makefile +## | | +## | \---mux2to1 +## | makefile +## | makefile.sources +## | +## +---pnr +## | | makefile +## | | +## | \---de1_mux2to1 +## | de1_mux2to1_pins.tcl +## | makefile +## | +## \---scripts +## de1_pin_assignments_minimumio.csv +## de1_pin_assignments_minimumio.tcl +## modelsim.ini +## quartus_project_settings.tcl +## ---------------------------------------------------------------------------- + diff --git a/sim/falling_edge_detector/makefile.sources b/sim/falling_edge_detector/makefile.sources new file mode 100644 index 0000000..03b2cd7 --- /dev/null +++ b/sim/falling_edge_detector/makefile.sources @@ -0,0 +1,18 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/e_falling_edge_detector.vhd \ +../../src/a_falling_edge_detector_rtl.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/falling_edge_detector/makefile_qfsm.sources b/sim/falling_edge_detector/makefile_qfsm.sources new file mode 100644 index 0000000..5b3eeec --- /dev/null +++ b/sim/falling_edge_detector/makefile_qfsm.sources @@ -0,0 +1,17 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/falling_edge_detector_qfsm.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/falling_edge_detector/makefile_rtl.sources b/sim/falling_edge_detector/makefile_rtl.sources new file mode 100644 index 0000000..03b2cd7 --- /dev/null +++ b/sim/falling_edge_detector/makefile_rtl.sources @@ -0,0 +1,18 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/e_falling_edge_detector.vhd \ +../../src/a_falling_edge_detector_rtl.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/falling_edge_detector/makefile_structure.sources b/sim/falling_edge_detector/makefile_structure.sources new file mode 100644 index 0000000..f644c26 --- /dev/null +++ b/sim/falling_edge_detector/makefile_structure.sources @@ -0,0 +1,19 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/d_ff_rtl.vhd \ +../../src/e_falling_edge_detector.vhd \ +../../src/a_falling_edge_detector_structure.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/incrementer/makefile b/sim/incrementer/makefile new file mode 100644 index 0000000..54e7a63 --- /dev/null +++ b/sim/incrementer/makefile @@ -0,0 +1,67 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with ModelSim, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# assign variable PROJECT with the top level project name +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of testbench t_$(PROJECT).vhd +################################################################### + +PROJECT = incrementer + +include ./makefile.sources + +# Add here the testbench file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/t_$(PROJECT).vhd + +include ../makefile + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## DigitaltechnikPraktikum +## | +## +---src +## | and2gate_equation.vhd +## | invgate_equation.vhd +## | mux2to1_structure.vhd +## | or2gate_equation.vhd +## | t_mux2to1.vhd +## | de1_mux2to1_structure.vhd +## | +## +---sim +## | | makefile +## | | +## | \---mux2to1 +## | makefile +## | makefile.sources +## | +## +---pnr +## | | makefile +## | | +## | \---de1_mux2to1 +## | de1_mux2to1_pins.tcl +## | makefile +## | +## \---scripts +## de1_pin_assignments_minimumio.csv +## de1_pin_assignments_minimumio.tcl +## modelsim.ini +## quartus_project_settings.tcl +## ---------------------------------------------------------------------------- + diff --git a/sim/incrementer/makefile.sources b/sim/incrementer/makefile.sources new file mode 100644 index 0000000..8766f99 --- /dev/null +++ b/sim/incrementer/makefile.sources @@ -0,0 +1,23 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/rising_edge_detector_qfsm.vhd \ +../../src/falling_edge_detector_qfsm.vhd \ +../../src/resolver_master_qfsm.vhd \ +../../src/resolver_structure.vhd \ +../../src/synchroniser_rtl.vhd \ +../../src/cntupdn_rtl.vhd \ +../../src/incrementer_structure.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/makefile b/sim/makefile new file mode 100644 index 0000000..6e7bd40 --- /dev/null +++ b/sim/makefile @@ -0,0 +1,87 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author(s) : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with ModelSim, +## it is based on a design directory structure shown at +## the end of this file. +## ---------------------------------------------------------------------------- + +################################################################### +# Main Targets +# +################################################################### + +help: + @echo '"make" does intentionally nothing. Type:' + @echo ' "make mproject" to create a new modelsim project only' + @echo ' "make compile" to compile all VHDL sources in batch mode' + @echo ' "make modelsim" to start modelsim with graphical user interface' + @echo ' "make sim" to start modelsim gui with the top testbench of the project' + @echo ' "make clean" to remove all generated files' + +mproject : mproject_created + +mproject_created : $(SOURCE_FILES) + # create modelsim project + rm -rf ./modelsim_sources.tcl + for source_file in $(SOURCE_FILES); do \ + echo project addfile $$source_file >> modelsim_sources.tcl; \ + done + vsim -modelsimini ../../scripts/modelsim.ini -c -do "project new [pwd] $(PROJECT); source ./modelsim_sources.tcl; quit -f" + touch mproject_created + +compile: ./work/_vmake + +./work/_vmake: mproject_created + vsim -c -do "project open $(PROJECT); project calculateorder; quit -f" + grep Error transcript; if [ $$? -eq 0 ] ; then rm -rf work/_vmake; exit 1; fi + + +modelsim: mproject_created + vsim -i -do "project open $(PROJECT)" & + +sim: ./work/_vmake + vsim -i -do "project open $(PROJECT); vsim work.t_$(PROJECT)(tbench); add wave *; run -a;" & + +clean: + rm -rf *.mpf *.mti *.ini *.wlf wlf* transcript work modelsim_sources.tcl mproject_created + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## DigitaltechnikPraktikum +## | +## +---src +## | and2gate_equation.vhd +## | invgate_equation.vhd +## | mux2to1_structure.vhd +## | or2gate_equation.vhd +## | t_mux2to1.vhd +## | de1_mux2to1_structure.vhd +## | +## +---sim +## | | makefile +## | | +## | \---mux2to1 +## | makefile +## | makefile.sources +## | +## +---pnr +## | | makefile +## | | +## | \---de1_mux2to1 +## | de1_mux2to1_pins.tcl +## | makefile +## | +## \---scripts +## de1_pin_assignments_minimumio.csv +## de1_pin_assignments_minimumio.tcl +## modelsim.ini +## quartus_project_settings.tcl +## ---------------------------------------------------------------------------- + diff --git a/sim/mux2to1/makefile b/sim/mux2to1/makefile new file mode 100644 index 0000000..c655d61 --- /dev/null +++ b/sim/mux2to1/makefile @@ -0,0 +1,67 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with ModelSim, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# assign variable PROJECT with the top level project name +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of testbench t_$(PROJECT).vhd +################################################################### + +PROJECT = mux2to1 + +include ./makefile.sources + +# Add here the testbench file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/t_$(PROJECT).vhd + +include ../makefile + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## DigitaltechnikPraktikum +## | +## +---src +## | and2gate_equation.vhd +## | invgate_equation.vhd +## | mux2to1_structure.vhd +## | or2gate_equation.vhd +## | t_mux2to1.vhd +## | de1_mux2to1_structure.vhd +## | +## +---sim +## | | makefile +## | | +## | \---mux2to1 +## | makefile +## | makefile.sources +## | +## +---pnr +## | | makefile +## | | +## | \---de1_mux2to1 +## | de1_mux2to1_pins.tcl +## | makefile +## | +## \---scripts +## de1_pin_assignments_minimumio.csv +## de1_pin_assignments_minimumio.tcl +## modelsim.ini +## quartus_project_settings.tcl +## ---------------------------------------------------------------------------- + diff --git a/sim/mux2to1/makefile.sources b/sim/mux2to1/makefile.sources new file mode 100644 index 0000000..880fac4 --- /dev/null +++ b/sim/mux2to1/makefile.sources @@ -0,0 +1,17 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/mux2to1_equation.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/mux2to1/makefile_equation.sources b/sim/mux2to1/makefile_equation.sources new file mode 100644 index 0000000..880fac4 --- /dev/null +++ b/sim/mux2to1/makefile_equation.sources @@ -0,0 +1,17 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/mux2to1_equation.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/mux2to1/makefile_rtl.sources b/sim/mux2to1/makefile_rtl.sources new file mode 100644 index 0000000..7dd9c7d --- /dev/null +++ b/sim/mux2to1/makefile_rtl.sources @@ -0,0 +1,17 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/mux2to1_rtl.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/mux2to1/makefile_structure.sources b/sim/mux2to1/makefile_structure.sources new file mode 100644 index 0000000..f797190 --- /dev/null +++ b/sim/mux2to1/makefile_structure.sources @@ -0,0 +1,20 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/and2gate_equation.vhd \ +../../src/or2gate_equation.vhd \ +../../src/invgate_equation.vhd \ +../../src/mux2to1_structure.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- \ No newline at end of file diff --git a/sim/mux2to1/makefile_structure_errors.sources b/sim/mux2to1/makefile_structure_errors.sources new file mode 100644 index 0000000..c412baf --- /dev/null +++ b/sim/mux2to1/makefile_structure_errors.sources @@ -0,0 +1,20 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/and2gate_equation.vhd \ +../../src/or2gate_equation.vhd \ +../../src/invgate_equation.vhd \ +../../src/mux2to1_structure_errors.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/mux2to1/makefile_truthtable.sources b/sim/mux2to1/makefile_truthtable.sources new file mode 100644 index 0000000..e815b55 --- /dev/null +++ b/sim/mux2to1/makefile_truthtable.sources @@ -0,0 +1,17 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/mux2to1_truthtable.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/pwm/makefile b/sim/pwm/makefile new file mode 100644 index 0000000..962c45a --- /dev/null +++ b/sim/pwm/makefile @@ -0,0 +1,67 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with ModelSim, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# assign variable PROJECT with the top level project name +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of testbench t_$(PROJECT).vhd +################################################################### + +PROJECT = pwm + +include ./makefile.sources + +# Add here the testbench file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/t_$(PROJECT).vhd + +include ../makefile + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## DigitaltechnikPraktikum +## | +## +---src +## | and2gate_equation.vhd +## | invgate_equation.vhd +## | mux2to1_structure.vhd +## | or2gate_equation.vhd +## | t_mux2to1.vhd +## | de1_mux2to1_structure.vhd +## | +## +---sim +## | | makefile +## | | +## | \---mux2to1 +## | makefile +## | makefile.sources +## | +## +---pnr +## | | makefile +## | | +## | \---de1_mux2to1 +## | de1_mux2to1_pins.tcl +## | makefile +## | +## \---scripts +## de1_pin_assignments_minimumio.csv +## de1_pin_assignments_minimumio.tcl +## modelsim.ini +## quartus_project_settings.tcl +## ---------------------------------------------------------------------------- + diff --git a/sim/pwm/makefile.sources b/sim/pwm/makefile.sources new file mode 100644 index 0000000..5db2028 --- /dev/null +++ b/sim/pwm/makefile.sources @@ -0,0 +1,17 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/pwm_rtl.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/pwm_incrementer/makefile b/sim/pwm_incrementer/makefile new file mode 100644 index 0000000..54e7a63 --- /dev/null +++ b/sim/pwm_incrementer/makefile @@ -0,0 +1,67 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with ModelSim, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# assign variable PROJECT with the top level project name +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of testbench t_$(PROJECT).vhd +################################################################### + +PROJECT = incrementer + +include ./makefile.sources + +# Add here the testbench file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/t_$(PROJECT).vhd + +include ../makefile + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## DigitaltechnikPraktikum +## | +## +---src +## | and2gate_equation.vhd +## | invgate_equation.vhd +## | mux2to1_structure.vhd +## | or2gate_equation.vhd +## | t_mux2to1.vhd +## | de1_mux2to1_structure.vhd +## | +## +---sim +## | | makefile +## | | +## | \---mux2to1 +## | makefile +## | makefile.sources +## | +## +---pnr +## | | makefile +## | | +## | \---de1_mux2to1 +## | de1_mux2to1_pins.tcl +## | makefile +## | +## \---scripts +## de1_pin_assignments_minimumio.csv +## de1_pin_assignments_minimumio.tcl +## modelsim.ini +## quartus_project_settings.tcl +## ---------------------------------------------------------------------------- + diff --git a/sim/pwm_incrementer/makefile.sources b/sim/pwm_incrementer/makefile.sources new file mode 100644 index 0000000..687a731 --- /dev/null +++ b/sim/pwm_incrementer/makefile.sources @@ -0,0 +1,24 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/rising_edge_detector_qfsm.vhd \ +../../src/falling_edge_detector_qfsm.vhd \ +../../src/resolver_master_qfsm.vhd \ +../../src/resolver_structure.vhd \ +../../src/synchroniser_rtl.vhd \ +../../src/cntupdn_rtl.vhd \ +../../src/incrementer_structure.vhd \ +../../src/pwm_rtl.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/resolver/makefile b/sim/resolver/makefile new file mode 100644 index 0000000..ac0a168 --- /dev/null +++ b/sim/resolver/makefile @@ -0,0 +1,68 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with ModelSim, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# assign variable PROJECT with the top level project name +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of testbench t_$(PROJECT).vhd +################################################################### + +PROJECT = resolver + +include ./makefile.sources + +# Add here the testbench file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/cntupdn_rtl.vhd \ +../../src/t_$(PROJECT).vhd + +include ../makefile + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## DigitaltechnikPraktikum +## | +## +---src +## | and2gate_equation.vhd +## | invgate_equation.vhd +## | mux2to1_structure.vhd +## | or2gate_equation.vhd +## | t_mux2to1.vhd +## | de1_mux2to1_structure.vhd +## | +## +---sim +## | | makefile +## | | +## | \---mux2to1 +## | makefile +## | makefile.sources +## | +## +---pnr +## | | makefile +## | | +## | \---de1_mux2to1 +## | de1_mux2to1_pins.tcl +## | makefile +## | +## \---scripts +## de1_pin_assignments_minimumio.csv +## de1_pin_assignments_minimumio.tcl +## modelsim.ini +## quartus_project_settings.tcl +## ---------------------------------------------------------------------------- + diff --git a/sim/resolver/makefile.sources b/sim/resolver/makefile.sources new file mode 100644 index 0000000..272943f --- /dev/null +++ b/sim/resolver/makefile.sources @@ -0,0 +1,21 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/rising_edge_detector_qfsm.vhd \ +../../src/falling_edge_detector_qfsm.vhd \ +../../src/resolver_master_qfsm.vhd \ +../../src/synchroniser_rtl.vhd \ +../../src/resolver_structure.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/src/a_falling_edge_detector_rtl.vhd b/src/a_falling_edge_detector_rtl.vhd new file mode 100644 index 0000000..117c3f1 --- /dev/null +++ b/src/a_falling_edge_detector_rtl.vhd @@ -0,0 +1,42 @@ +------------------------------------------------------------------------------- +-- Module : rtl +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: detects a falling edge of input signal x_i +-- and produces a high-active signal for one clock period at +-- output fall_o +-- clk_i __|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--| +-- x_i -----|___________________________________|----------- +-- fall_o ________|-----|______________________________________ +-- +-- rtl model based on two flip flops with output logic +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ARCHITECTURE rtl OF falling_edge_detector IS + + SIGNAL q0, q1 : std_ulogic; -- D-Type Flip-Flop outputs + +BEGIN + + dflipflop_0 : q0 <= '0' WHEN (rst_ni = '0') ELSE + x_i WHEN rising_edge(clk_i); + + dflipflop_1 : q1 <= '0' WHEN (rst_ni = '0') ELSE + q0 WHEN rising_edge(clk_i); + + output_logic : fall_o <= ; -- fill in the correct equation here + +END rtl; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- + diff --git a/src/adcintf.vhd b/src/adcintf.vhd new file mode 100644 index 0000000..c5ae405 --- /dev/null +++ b/src/adcintf.vhd @@ -0,0 +1,98 @@ +--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- ADC (Analog to Digital Converter) Interface +-- Shifts in 16 bits and provides the data in parallel +-- When all 16 bits are shifted in, the valid_o output is set to "1" for one clock cycle + +entity adcintf is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + en_i : in std_ulogic; + valid_o : out std_ulogic; + data_o : out std_ulogic_vector(15 downto 0); + start_i : in std_ulogic; + ser_dat_i : in std_ulogic); +end; + +architecture rtl of adcintf is + type state_t is (idle_s, shift_s, done_s); + signal state, new_state : state_t; + signal idx : integer range 0 to 15; + signal data : unsigned(15 downto 0); + signal idx_inc : std_ulogic; + signal idx_reset : std_ulogic; + signal data_shift : std_ulogic; +begin + + seq_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + idx <= 0; + data <= (others => '0'); + state <= idle_s; + elsif rising_edge(clk_i) then + if data_shift = '1' then + data <= shift_left(data,1); + data(0) <= ser_dat_i; + end if; + if idx_reset = '1' then + idx <= 0; + elsif idx_inc = '1' and idx < 15 then + idx <= idx + 1; + end if; + state <= new_state; + end if; + end process seq_p; + + statem_comb_p : process(state, idx, start_i, en_i) + begin + idx_inc <= '0'; + idx_reset <= '0'; + new_state <= state; + data_shift <= '0'; + valid_o <= '0'; + case state is + when idle_s => + if start_i = '1' and en_i = '1' then + new_state <= shift_s; + idx_reset <= '1'; + end if; + when shift_s => + if en_i = '1' then + idx_inc <= '1'; + data_shift <= '1'; + if idx = 15 then + new_state <= done_s; + end if; + end if; + when done_s => + valid_o <= '1'; + new_state <= idle_s; + when others => + new_state <= idle_s; + end case; + end process statem_comb_p; + + data_o <= std_ulogic_vector(data); + +end; -- architecture + + diff --git a/src/and2gate_equation.vhd b/src/and2gate_equation.vhd new file mode 100644 index 0000000..9c7f0f2 --- /dev/null +++ b/src/and2gate_equation.vhd @@ -0,0 +1,35 @@ +------------------------------------------------------------------------------- +-- Module : and2gate +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: 2-input AND Gate +-- function modelled by logic equation +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY and2gate IS + PORT (a_i : IN std_ulogic; -- data input a + b_i : IN std_ulogic; -- data input b + y_o : OUT std_ulogic -- data output y + ); +END and2gate; + +ARCHITECTURE equation OF and2gate IS + +BEGIN + + y_o <= a_i AND b_i; + +END equation; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- + diff --git a/src/audio.vhd b/src/audio.vhd new file mode 100644 index 0000000..9a6ad17 --- /dev/null +++ b/src/audio.vhd @@ -0,0 +1,156 @@ +--Copyright 2021 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; + +entity audio is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + i2c_sclk_o : out std_ulogic; + i2c_dat_i : in std_ulogic; + i2c_dat_o : out std_ulogic; + aud_adclrck_o : out std_ulogic; + aud_adcdat_i : in std_ulogic; + aud_daclrck_o : out std_ulogic; + aud_dacdat_o : out std_ulogic; + aud_xck_o : out std_ulogic; + aud_bclk_o : out std_ulogic; + adc_data_o : out std_ulogic_vector(15 downto 0); + adc_valid_o : out std_ulogic; + dac_data_i : in std_ulogic_vector(15 downto 0); + dac_strobe_o : out std_ulogic); +end; + +architecture struct of audio is + + component i2c_sub is + port ( + clk_i: in std_ulogic; + reset_ni: in std_ulogic; + i2c_clk_o: out std_ulogic; + i2c_dat_o: out std_ulogic; + i2c_dat_i: in std_ulogic + ); + end component; + + component adcintf is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + en_i : in std_ulogic; + valid_o : out std_ulogic; + data_o : out std_ulogic_vector(15 downto 0); + start_i : in std_ulogic; + ser_dat_i : in std_ulogic); + end component; + + component dacintf is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + load_i : in std_ulogic; + data_i : in std_ulogic_vector(15 downto 0); + en_i : in std_ulogic; + ser_dat_o : out std_ulogic); + end component; + + component bclk is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + bclk_o : out std_ulogic; + bclk_falling_edge_en_o : out std_ulogic); + end component; + + component fsgen is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + bclk_falling_edge_en_i : in std_ulogic; + fs_o : out std_ulogic); + end component; + + component mclk is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + mclk_o : out std_ulogic); + end component; + + signal framesync : std_ulogic; + signal bclk_falling_edge_en : std_ulogic; + + signal adc_valid : std_ulogic; + signal dac_data, adc_data : std_ulogic_vector(15 downto 0); + +begin + + i2c_sub_i0 : i2c_sub + port map ( + clk_i => clk_i, + reset_ni => reset_ni, + i2c_clk_o => i2c_sclk_o, + i2c_dat_o => i2c_dat_o, + i2c_dat_i => i2c_dat_i); + + mclk_i0 : mclk + port map( + clk_i => clk_i, + reset_ni => reset_ni, + mclk_o => aud_xck_o); + + bclk_i0 : bclk + port map ( + clk_i => clk_i, + reset_ni => reset_ni, + bclk_o => aud_bclk_o, + bclk_falling_edge_en_o => bclk_falling_edge_en); + + fsgen_i0 : fsgen + port map ( + clk_i => clk_i, + reset_ni => reset_ni, + bclk_falling_edge_en_i => bclk_falling_edge_en, + fs_o => framesync); + + dacintf_i0 : dacintf + port map ( + clk_i => clk_i, + reset_ni => reset_ni, + load_i => framesync, + data_i => dac_data_i, + en_i => bclk_falling_edge_en, + ser_dat_o => aud_dacdat_o); + + adcintf_i0 : adcintf + port map ( + clk_i => clk_i, + reset_ni => reset_ni, + valid_o => adc_valid_o, + data_o => adc_data_o, + start_i => framesync, + en_i => bclk_falling_edge_en, + ser_dat_i => aud_adcdat_i); + + aud_daclrck_o <= framesync; + aud_adclrck_o <= framesync; + + dac_strobe_o <= framesync and bclk_falling_edge_en; + +end; -- architecture + + diff --git a/src/bclk.vhd b/src/bclk.vhd new file mode 100644 index 0000000..4d72539 --- /dev/null +++ b/src/bclk.vhd @@ -0,0 +1,79 @@ +--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- Bitclock generator + +entity bclk is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + bclk_o : out std_ulogic; + bclk_falling_edge_en_o : out std_ulogic); +end; + +architecture rtl of bclk is + constant max_count : integer := 7; + signal clk_counter : integer range 0 to max_count; + signal bclk_rising_edge_en : std_ulogic; + signal bclk_falling_edge_en : std_ulogic; +begin + + bclk_cnt_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + clk_counter <= 0; + elsif rising_edge(clk_i) then + if clk_counter = max_count then + clk_counter <= 0; + else + clk_counter <= clk_counter + 1; + end if; + end if; + end process bclk_cnt_p; + + edge_comb_p : process(clk_counter) + begin + bclk_rising_edge_en <= '0'; + bclk_falling_edge_en <= '0'; + if clk_counter = max_count then + bclk_rising_edge_en <= '1'; + end if; + if clk_counter = max_count / 2 then + bclk_falling_edge_en <= '1'; + end if; + end process edge_comb_p; + + bclk_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + bclk_o <= '0'; + elsif rising_edge(clk_i) then + if bclk_rising_edge_en = '1' then + bclk_o <= '1'; + elsif bclk_falling_edge_en = '1' then + bclk_o <= '0'; + end if; + end if; + end process bclk_p; + + bclk_falling_edge_en_o <= bclk_falling_edge_en; + +end; -- architecture + + diff --git a/src/binto7segment_truthtable.vhd b/src/binto7segment_truthtable.vhd new file mode 100644 index 0000000..e0be505 --- /dev/null +++ b/src/binto7segment_truthtable.vhd @@ -0,0 +1,63 @@ +------------------------------------------------------------------------------- +-- Module : binto7segment +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: binary-to-7-segment decoder +-- function modelled as a truth table +-- using a selected signal assignment +-- segments get illuminated by a low-active signal +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY binto7segment IS + PORT (bin_i : IN std_ulogic_vector(3 DOWNTO 0); + segments_o : OUT std_ulogic_vector(6 DOWNTO 0) + ); +END binto7segment; + +ARCHITECTURE truthtable OF binto7segment IS + + -- seven-segment positions + -- + -- segment positions input vector index segment name + -- a 0 => a + -- --- 1 => b + -- f | | b 2 => c + -- --- <- g 3 => d + -- e | | c 4 => e + -- --- 5 => f + -- d 6 => g + +BEGIN + + decoder : WITH bin_i SELECT + segments_o <= + -- outputs: | inputs: + -------------------------------------------- + -- index | number displayed + -- 6543210 | + -------------------------------------------- + "1000000" WHEN "0000", -- 0 + "1111001" WHEN "0001", -- 1 + "0100100" WHEN "0010", -- 2 + "0110000" WHEN "0011", -- 3 + "0001001" WHEN "0100", -- 4 + "0010010" WHEN "0101", -- 5 + "0000010" WHEN "0110", -- 6 + "0111000" WHEN "0111", -- 7 + "0000000" WHEN "1000", -- 8 + "0010000" WHEN "1001", -- 9 + "0000110" WHEN OTHERS; -- displays Symbol 'E' for ERROR + +END truthtable; +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- + diff --git a/src/cntdn_rtl.vhd b/src/cntdn_rtl.vhd new file mode 100644 index 0000000..7ce14ea --- /dev/null +++ b/src/cntdn_rtl.vhd @@ -0,0 +1,47 @@ +------------------------------------------------------------------------------- +-- Module : cntdn +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: Down-Counter +-- including a low-active asynchronous reset input rst_ni +-- a high-active enable input en_pi +-- and a terminal count output: tc = 1 when count = 0 +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY cntdn IS + PORT (clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + en_pi : IN std_ulogic; + count_o : OUT std_ulogic_vector(3 DOWNTO 0); + tc_o : OUT std_ulogic + ); +END cntdn; + +ARCHITECTURE rtl OF cntdn IS + + +BEGIN + + incrementer : + + state_register : + + counter_output : + + terminal_output : + +END rtl; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- + diff --git a/src/cntdnmodm_rtl.vhd b/src/cntdnmodm_rtl.vhd new file mode 100644 index 0000000..51809a4 --- /dev/null +++ b/src/cntdnmodm_rtl.vhd @@ -0,0 +1,54 @@ +------------------------------------------------------------------------------- +-- Module : cntdnmodm +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: Modulo-m n-Bit Down-Counter +-- including a low-active asynchronous reset input rst_ni +-- and a high-active enable input en_pi +-- additionally, a high_active output signal tc_o is produced, +-- when the counter reaches it's minimum value +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY cntdnmodm IS + GENERIC ( + n : natural := 4; -- counter width + m : natural := 10); -- modulo value + PORT (clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + en_pi : IN std_ulogic; + count_o : OUT std_ulogic_vector(n-1 DOWNTO 0); + tc_o : OUT std_ulogic + ); +END cntdnmodm; + +ARCHITECTURE rtl OF cntdnmodm IS + + SIGNAL next_state, current_state : unsigned(n-1 DOWNTO 0); + +BEGIN + + -- includes decrementer and modulo logic + next_state_logic : next_state <= to_unsigned(m-1, n) WHEN current_state = 0 ELSE + current_state - 1; + + state_register : + + counter_output : + + terminal_count : + +END rtl; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- + diff --git a/src/cntupdn_rtl.vhd b/src/cntupdn_rtl.vhd new file mode 100644 index 0000000..5f022e3 --- /dev/null +++ b/src/cntupdn_rtl.vhd @@ -0,0 +1,47 @@ +------------------------------------------------------------------------------- +-- Module : cntupdn +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: Up/Down-Counter +-- including a low-active asynchronous reset input rst_ni +-- a high-active enable input en_pi +-- mode_i = 0 -> count down +-- mode_i = 1 -> count up +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY cntupdn IS + PORT (clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + en_pi : IN std_ulogic; + mode_i : IN std_ulogic; -- mode_i = 0 -> count down + -- mode_i = 1 -> count up + count_o : OUT std_ulogic_vector(3 DOWNTO 0) + ); +END cntupdn; + +ARCHITECTURE rtl OF cntupdn IS + + +BEGIN + + de_incrementer : + + state_register : + + counter_output : + +END rtl; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- + diff --git a/src/cntupen_rtl.vhd b/src/cntupen_rtl.vhd new file mode 100644 index 0000000..2c68a73 --- /dev/null +++ b/src/cntupen_rtl.vhd @@ -0,0 +1,52 @@ +------------------------------------------------------------------------------- +-- Module : cntupen +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: Up-Counter +-- including a low-active asynchronous reset input rst_ni +-- and a high-active enable input en_pi +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY cntupen IS + PORT (clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + en_pi : IN std_ulogic; + count_o : OUT std_ulogic_vector(3 DOWNTO 0) + ); +END cntupen; + +ARCHITECTURE rtl OF cntupen IS + + -- datatype unsigned is defined in package numeric_std + SIGNAL next_state, current_state : unsigned(3 DOWNTO 0); + +BEGIN + + -- package numeric_std overloads operator '+' + -- for arguments of different types, here: unsigned and integer + incrementer : next_state <= current_state + 1; + + + -- synthesisable construct of a d-type register with synchronrous enable + state_register : current_state <= "0000" WHEN rst_ni = '0' ELSE + next_state WHEN rising_edge(clk_i) AND (en_pi = '1'); + + + -- type conversion from unsignd to std_ulogic_vector necessary + counter_output : count_o <= std_ulogic_vector(current_state); + +END rtl; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- + diff --git a/src/d_ff_rtl.vhd b/src/d_ff_rtl.vhd new file mode 100644 index 0000000..af06a3e --- /dev/null +++ b/src/d_ff_rtl.vhd @@ -0,0 +1,39 @@ +------------------------------------------------------------------------------- +-- Module : d_ff +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: D-Type Flip-Flop +-- including a low-active asynchronous reset input rst_ni +-- and a high-active enable input en_pi +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY d_ff IS + PORT ( + clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + d_i : IN std_ulogic; + q_o : OUT std_ulogic + ); +END d_ff; + +ARCHITECTURE rtl OF d_ff IS + +BEGIN + + dflipflop_p : q_o <= '0' WHEN (rst_ni = '0') ELSE + d_i WHEN rising_edge(clk_i); + +END rtl; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- + diff --git a/src/dacintf.vhd b/src/dacintf.vhd new file mode 100644 index 0000000..87c48fa --- /dev/null +++ b/src/dacintf.vhd @@ -0,0 +1,60 @@ +--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- DAC (Digital to Analog Converter) Interface +-- Loads a word in parallel and shifts it out as serial bit stream +-- The data needs to be shifted out twice. This is required as +-- the audio interface needs stereo data. + +entity dacintf is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + load_i : in std_ulogic; + data_i : in std_ulogic_vector(15 downto 0); + en_i : in std_ulogic; + ser_dat_o : out std_ulogic); +end; + +architecture rtl of dacintf is + signal idx : integer range 0 to 31; + signal data : unsigned(15 downto 0); +begin + + load_and_shift_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + idx <= 0; + data <= (others => '0'); + elsif rising_edge(clk_i) then + if load_i = '1' and en_i = '1' then + data <= unsigned(data_i); + idx <= 0; + elsif en_i = '1' and idx < 31 then + data <= rotate_left(data,1); + idx <= idx + 1; + end if; + end if; + end process load_and_shift_p; + + ser_dat_o <= data(15); + +end; -- architecture + + diff --git a/src/de1_adc_rtl.vhd b/src/de1_adc_rtl.vhd new file mode 100644 index 0000000..d82c892 --- /dev/null +++ b/src/de1_adc_rtl.vhd @@ -0,0 +1,111 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- PLL for 100 MHz speed +library altera_mf; +use altera_mf.all; + +entity de1_adc is + port ( CLOCK_50 : in std_ulogic; + SW : in std_ulogic_vector(9 downto 0); + KEY0 : in std_ulogic; + DAC_MODE : out std_ulogic; --1=dual port, 0=interleaved + DAC_WRT_A : out std_ulogic; + DAC_WRT_B : out std_ulogic; + DAC_CLK_A : out std_ulogic; -- PLL_OUT_DAC0 in User Manual + DAC_CLK_B : out std_ulogic; -- PLL_OUT_DAC1 in User Manual + DAC_DA : out std_ulogic_vector(13 downto 0); + DAC_DB : out std_ulogic_vector(13 downto 0); + ADC_CLK_A : out std_ulogic; + ADC_CLK_B : out std_ulogic; + POWER_ON : out std_ulogic; + ADC_OEB_A : out std_ulogic; + ADC_OEB_B : out std_ulogic; + ADC_DA : in std_ulogic_vector(13 downto 0); + ADC_DB : in std_ulogic_vector(13 downto 0); + ADC_OTR_A : in std_ulogic; + ADC_OTR_B : in std_ulogic; + LEDR : out std_ulogic_vector(9 downto 0)); -- red LEDs +end entity; + +architecture rtl of de1_adc is + + -- Altera PLL + component altpll + generic ( + clk0_divide_by : natural; + clk0_duty_cycle : natural; + clk0_multiply_by : natural; +-- clk0_phase_shift : STRING; +-- compensate_clock : STRING; + inclk0_input_frequency : natural; +-- intended_device_family : STRING; +-- lpm_hint : STRING; +-- lpm_type : STRING; + operation_mode : string; + port_inclk0 : string; + port_clk0 : string + ); + port ( + clk : out std_logic_vector (5 downto 0); + inclk : in std_logic_vector (1 downto 0) + ); + end component; + + signal pll_inclk : std_logic_vector(1 downto 0); + signal pll_outclk : std_logic_vector(5 downto 0); + + signal clk,rst_n : std_ulogic; + signal dac_a_dat, dac_b_dat, adc_a_dat, adc_b_dat : std_ulogic_vector(13 downto 0); + +begin + + pll_i0 : altpll + generic map ( + clk0_divide_by => 10, + clk0_duty_cycle => 50, + clk0_multiply_by => 13, +-- clk0_phase_shift => "0", +-- compensate_clock => "CLK0", + inclk0_input_frequency => 20000, + operation_mode => "NORMAL", + port_inclk0 => "PORT_USED", + port_clk0 => "PORT_USED" + ) + port map ( + inclk => pll_inclk, + clk => pll_outclk + ); + + pll_inclk(0) <= CLOCK_50; + pll_inclk(1) <= '0'; + clk <= pll_outclk(0); + --clk <= CLOCK_50; + + rst_n <= KEY0; + LEDR <= "00000000" & ADC_OTR_A & ADC_OTR_B when rising_edge(clk); + + DAC_MODE <= '1'; --dual port + DAC_CLK_A <= clk; + DAC_CLK_B <= clk; + DAC_WRT_A <= clk; + DAC_WRT_B <= clk; + + dac_a_dat <= (others => '0') when rst_n = '0' else adc_a_dat when falling_edge(clk); + dac_b_dat <= (others => '0') when rst_n = '0' else adc_b_dat when falling_edge(clk); + + DAC_DA <= dac_a_dat; + DAC_DB <= dac_b_dat; + + -- ADC Section + ADC_CLK_A <= clk; + ADC_CLK_B <= clk; + ADC_OEB_A <= '0'; + ADC_OEB_B <= '0'; + POWER_ON <= '1'; + + adc_a_dat <= (others => '0') when rst_n = '0' else ADC_DA when rising_edge(clk); + adc_b_dat <= (others => '0') when rst_n = '0' else ADC_DB when rising_edge(clk); + +end architecture rtl; diff --git a/src/de1_add1_structure.vhd b/src/de1_add1_structure.vhd new file mode 100644 index 0000000..5c12d59 --- /dev/null +++ b/src/de1_add1_structure.vhd @@ -0,0 +1,51 @@ +------------------------------------------------------------------------------- +-- Module : de1_add1 +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: test the module add1 on a DE1 prototype board +-- connecting device under test (DUT) add1 +-- to input/output signals of the DE1 prototype board +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY de1_add1 IS + PORT ( + SW : IN std_ulogic_vector(2 DOWNTO 0); -- Toggle Switch[2:0] + LEDR : OUT std_ulogic_vector(1 DOWNTO 0) -- LED Red[1:0] + ); +END de1_add1; + +ARCHITECTURE structure OF de1_add1 IS + + COMPONENT add1 + PORT ( + a_i : IN std_ulogic; + b_i : IN std_ulogic; + ci_i : IN std_ulogic; + sum_o : OUT std_ulogic; + co_o : OUT std_ulogic); + END COMPONENT; + +BEGIN + + -- connecting device under test with peripheral elements + DUT : add1 + PORT MAP ( + a_i => SW(0), + b_i => SW(1), + ci_i => SW(2), + sum_o => LEDR(0), + co_o => LEDR(1) + ); + +END structure; +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- diff --git a/src/de1_add4_structure.vhd b/src/de1_add4_structure.vhd new file mode 100644 index 0000000..bbd75ab --- /dev/null +++ b/src/de1_add4_structure.vhd @@ -0,0 +1,103 @@ +------------------------------------------------------------------------------- +-- Module : de1_add4 +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: test the module add4 on a DE1 prototype board +-- connecting device under test (DUT) add4 +-- to input/output signals of the DE1 prototype board +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY de1_add4 IS + PORT ( + SW : IN std_ulogic_vector(8 DOWNTO 0); -- Toggle Switch[8:0] + LEDR : OUT std_ulogic_vector(8 DOWNTO 0); -- LED Red[8:0] + LEDG : OUT std_ulogic_vector(4 DOWNTO 0); -- LED Green[3:0] + HEX0 : OUT std_ulogic_vector(6 DOWNTO 0); -- Seven Segment Digit 0 + HEX1 : OUT std_ulogic_vector(6 DOWNTO 0); -- Seven Segment Digit 1 + HEX2 : OUT std_ulogic_vector(6 DOWNTO 0); -- Seven Segment Digit 2 + + -- Ports for measurement of longest path through module + CLOCK_50 : IN std_ulogic; -- 50 MHz Clock + GPO_1 : OUT std_ulogic_vector(1 DOWNTO 0) -- Output Connector GPIO_1 + -- GPO_1[0] = CLOCK_50 + -- GPO_1[1] = co_o + + ); +END de1_add4; + +ARCHITECTURE structure OF de1_add4 IS + + COMPONENT binto7segment + PORT ( + bin_i : IN std_ulogic_vector(3 DOWNTO 0); + segments_o : OUT std_ulogic_vector(6 DOWNTO 0)); + END COMPONENT; + + COMPONENT add4 + PORT ( + a_i : IN std_ulogic_vector(3 DOWNTO 0); + b_i : IN std_ulogic_vector(3 DOWNTO 0); + ci_i : IN std_ulogic; + sum_o : OUT std_ulogic_vector(3 DOWNTO 0); + co_o : OUT std_ulogic); + END COMPONENT; + + SIGNAL a : std_ulogic_vector(3 DOWNTO 0); + SIGNAL b : std_ulogic_vector(3 DOWNTO 0); + SIGNAL ci : std_ulogic; + SIGNAL sum : std_ulogic_vector(3 DOWNTO 0); + SIGNAL co : std_ulogic; + +BEGIN + + -- Modifications for measurement of longest path through module + GPO_1(0) <= CLOCK_50; + GPO_1(1) <= co; + -- use the following line for Tpd measurement + -- ci <= CLOCK_50; -- tpd of add4 module only + + -- connecting switches to operands + ci <= SW(0); -- use this line, if connected by SW(0) + a <= SW(4 DOWNTO 1); + b <= SW(8 DOWNTO 5); + + -- connecting operands to LEDs + LEDR(0) <= SW(0); + LEDR(4 DOWNTO 1) <= SW(4 DOWNTO 1); + LEDR(8 DOWNTO 5) <= SW(8 DOWNTO 5); + + -- connecting device under test with peripheral elements + DUT : add4 + PORT MAP ( + a_i => a, + b_i => b, + ci_i => ci, + sum_o => sum, + co_o => co); + + -- connecting results to LEDs and HEX displays + LEDG(3 DOWNTO 0) <= sum; + LEDG(4) <= co; + + operand_a : binto7segment + PORT MAP ( + bin_i => a, + segments_o => HEX0); + + operand_b : binto7segment + PORT MAP ( -- fill in the missing components here ... + + + +END structure; +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- diff --git a/src/de1_audio.vhd b/src/de1_audio.vhd new file mode 100644 index 0000000..f01a9a7 --- /dev/null +++ b/src/de1_audio.vhd @@ -0,0 +1,118 @@ +--Copyright 2013,2021 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library altera; +use altera.altera_primitives_components.all; + +entity de1_audio is + port ( + CLOCK_50: in std_ulogic; + KEY0: in std_ulogic; + I2C_SCLK: out std_ulogic; + I2C_SDAT: inout std_logic; + AUD_ADCLRCK: out std_ulogic; + AUD_ADCDAT: in std_ulogic; + AUD_DACLRCK: out std_ulogic; + AUD_DACDAT: out std_ulogic; + AUD_XCK: out std_ulogic; + AUD_BCLK: out std_ulogic; + LEDR: out std_ulogic_vector(9 downto 0)); +end; + +architecture struct of de1_audio is + + component audio is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + i2c_sclk_o : out std_ulogic; + i2c_dat_i : in std_ulogic; + i2c_dat_o : out std_ulogic; + aud_adclrck_o : out std_ulogic; + aud_adcdat_i : in std_ulogic; + aud_daclrck_o : out std_ulogic; + aud_dacdat_o : out std_ulogic; + aud_xck_o : out std_ulogic; + aud_bclk_o : out std_ulogic; + adc_data_o : out std_ulogic_vector(15 downto 0); + adc_valid_o : out std_ulogic; + dac_data_i : in std_ulogic_vector(15 downto 0); + dac_strobe_o : out std_ulogic); + end component; + + component ringbuf is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + en_i : in std_ulogic; + data_i : in std_ulogic_vector(15 downto 0); + data_o : out std_ulogic_vector(15 downto 0)); + end component; + + signal clk, reset_n : std_ulogic; + + signal i2c_dat_o : std_ulogic; + signal i2c_dat_i : std_ulogic; + + + signal adc_valid : std_ulogic; + signal dac_strobe : std_ulogic; + signal dac_data, adc_data : std_ulogic_vector(15 downto 0); + +begin + + reset_n <= KEY0; + clk <= CLOCK_50; + + audio_i0 : audio + port map ( + clk_i => clk, + reset_ni => reset_n, + i2c_sclk_o => I2C_SCLK, + i2c_dat_i => i2c_dat_i, + i2c_dat_o => i2c_dat_o, + aud_adclrck_o => AUD_ADCLRCK, + aud_adcdat_i => AUD_ADCDAT, + aud_daclrck_o => AUD_DACLRCK, + aud_dacdat_o => AUD_DACDAT, + aud_xck_o => AUD_XCK, + aud_bclk_o => AUD_BCLK, + adc_data_o => adc_data, + adc_valid_o => adc_valid, + dac_data_i => dac_data, + dac_strobe_o => dac_strobe); + + ringbuf_i0 : ringbuf + port map ( + clk_i => clk, + reset_ni => reset_n, + en_i => adc_valid, + data_i => adc_data, + data_o => dac_data); + + LEDR(9 downto 0) <= std_ulogic_vector(abs(signed(dac_data(15 downto 6)))); + + -- i2c has an open-drain ouput + i2c_dat_i <= I2C_SDAT; + i2c_data_buffer_i : OPNDRN + port map (a_in => i2c_dat_o, a_out => I2C_SDAT); + +end; -- architecture + + diff --git a/src/de1_binto7segment_structure.vhd b/src/de1_binto7segment_structure.vhd new file mode 100644 index 0000000..b4fbd79 --- /dev/null +++ b/src/de1_binto7segment_structure.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- Module : de1_binto7segment +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: test the module binto7segment on a DE1 prototype board +-- connecting device under test (DUT) binto7segment +-- to input/output signals of the DE1 prototype board +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY de1_binto7segment IS + PORT ( + SW : IN std_ulogic_vector(3 DOWNTO 0); -- Toggle Switch[3:0] + LEDR : OUT std_ulogic_vector(3 DOWNTO 0); -- LED Red[3:0] + HEX0 : OUT std_ulogic_vector(6 DOWNTO 0) -- Seven Segment Digit 0 + ); +END de1_binto7segment; + +ARCHITECTURE structure OF de1_binto7segment IS + + COMPONENT binto7segment + PORT ( + bin_i : IN std_ulogic_vector(3 DOWNTO 0); + segments_o : OUT std_ulogic_vector(6 DOWNTO 0)); + END COMPONENT; + +BEGIN + + -- connecting device under test with peripheral elements + DUT : binto7segment + PORT MAP ( + bin_i => SW, + segments_o => HEX0); + + -- connect switches to red LEDs + LEDR <= SW; + +END structure; +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- diff --git a/src/de1_cntdn_structure.vhd b/src/de1_cntdn_structure.vhd new file mode 100644 index 0000000..d420996 --- /dev/null +++ b/src/de1_cntdn_structure.vhd @@ -0,0 +1,78 @@ +------------------------------------------------------------------------------- +-- Module : de1_cntdn +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: test the module cntdn on a DE1 prototype board +-- connecting device under test (DUT) cntdn +-- to input/output signals of the DE1 prototype board +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY de1_cntdn IS + PORT ( + CLOCK_50 : IN std_ulogic; -- 50 MHz Clock + KEY : IN std_ulogic_vector(1 DOWNTO 0); -- KEY[1:0] + -- KEY[0] = rst_ni + -- KEY[1] = en_pi + GPO_1 : OUT std_ulogic_vector(5 DOWNTO 0) -- Output Connector GPIO_1 + -- GPO_1[3:0] = count_o + -- GPO_1[4] = tc_o + -- GPO_1[5] = clk_i + ); +END de1_cntdn; + +ARCHITECTURE structure OF de1_cntdn IS + + COMPONENT cntdn + PORT ( + clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + en_pi : IN std_ulogic; + count_o : OUT std_ulogic_vector(3 DOWNTO 0); + tc_o : OUT std_ulogic); + END COMPONENT; + + SIGNAL clk_i : std_ulogic; + SIGNAL rst_ni : std_ulogic; + SIGNAL en_pi : std_ulogic; + SIGNAL count_o : std_ulogic_vector(3 DOWNTO 0); + SIGNAL tc_o : std_ulogic; + +BEGIN + + -- connecting clock generator master clock of synchronous system + clk_i <= CLOCK_50; + GPO_1(5) <= clk_i; -- to measure clk signal + + -- connecting asynchronous system reset to digital system + rst_ni <= KEY(0); + + -- count enable input is high-active, KEY(1) ist low-aktive, therefore ... + -- ... if KEY1 is released, high signal is produced + en_pi <= KEY(1); + + + -- connecting device under test with peripheral elements + DUT : ENTITY work.cntdn(rtl) + PORT MAP ( + clk_i => clk_i, + rst_ni => rst_ni, + en_pi => en_pi, + count_o => count_o, + tc_o => tc_o); + + -- connecting count value to GPIO1 + GPO_1(3 DOWNTO 0) <= count_o; + GPO_1(4) <= tc_o; + +END structure; +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- diff --git a/src/de1_cntdnmodm_structure.vhd b/src/de1_cntdnmodm_structure.vhd new file mode 100644 index 0000000..d76c5f3 --- /dev/null +++ b/src/de1_cntdnmodm_structure.vhd @@ -0,0 +1,111 @@ +------------------------------------------------------------------------------- +-- Module : de1_cntdnmodm +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: test the module cntdnmodm on a DE1 prototype board +-- connecting device under test (DUT) cntdnmodm +-- to input/output signals of the DE1 prototype board +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY de1_cntdnmodm IS + PORT ( + CLOCK_50 : IN std_ulogic; -- 50 MHz Clock + KEY : IN std_ulogic_vector(1 DOWNTO 0); -- KEY[1:0] + -- KEY[0] = rst_ni + -- KEY[1] = en_pi + GPO_1 : OUT std_ulogic_vector(7 DOWNTO 0) -- Output Connector GPIO_1 + -- GPO_1[3:0] = count_o + -- GPO_1[4] = tc_o + -- GPO_1[5] = clk_i + -- GPO_1[6] = tc_mod6_o + -- GPO_1[7] = tc_100hz_o + ); +END de1_cntdnmodm; + +ARCHITECTURE structure OF de1_cntdnmodm IS + + COMPONENT cntdn + PORT ( + clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + en_pi : IN std_ulogic; + count_o : OUT std_ulogic_vector(3 DOWNTO 0); + tc_o : OUT std_ulogic); + END COMPONENT; + + SIGNAL clk_i : std_ulogic; + SIGNAL rst_ni : std_ulogic; + SIGNAL en_pi : std_ulogic; + SIGNAL count_o : std_ulogic_vector(3 DOWNTO 0); + SIGNAL tc_o : std_ulogic; + + SIGNAL tc_mod6_o : std_ulogic; + SIGNAL tc_100hz_o : std_ulogic; + +BEGIN + + -- connecting clock generator master clock of synchronous system + clk_i <= CLOCK_50; + GPO_1(5) <= clk_i; -- to measure clk signal + + -- connecting asynchronous system reset to digital system + rst_ni <= KEY(0); + + -- count enable input is high-active, KEY(1) ist low-aktive, therefore ... + -- ... if KEY1 is released, high signal is produced + en_pi <= KEY(1); + + + -- connecting device under test with peripheral elements + DUT : ENTITY work.cntdnmodm + GENERIC MAP ( + n => 4, + m => 10) + PORT MAP ( + clk_i => clk_i, + rst_ni => rst_ni, + en_pi => en_pi, + count_o => count_o, + tc_o => tc_o); + + -- 3-bit modulo-6 down counter + mod6_count : ENTITY work.cntdnmodm + GENERIC MAP ( + n => 3, + m => 6) + PORT MAP ( + clk_i => clk_i, + rst_ni => rst_ni, + en_pi => en_pi, + count_o => OPEN, + tc_o => tc_mod6_o); + + -- instantiate and parameterise the generics to + -- create a frequency of 100 Hz at its output signal tc_100hz_o + -- declare the necessary signals count_modxxx_o and tc_100hz_o + ----------------------------------------------------------------------------- +-- prescaler : cntdnmodm +-- GENERIC MAP ( +-- n => +-- m => ) +-- PORT MAP ( + ----------------------------------------------------------------------------- + + -- connecting count value to GPIO1 + GPO_1(3 DOWNTO 0) <= count_o; + GPO_1(4) <= tc_o; + GPO_1(6) <= tc_mod6_o; + GPO_1(7) <= tc_100hz_o; + +END structure; +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- diff --git a/src/de1_dac_rtl.vhd b/src/de1_dac_rtl.vhd new file mode 100644 index 0000000..c1c90bf --- /dev/null +++ b/src/de1_dac_rtl.vhd @@ -0,0 +1,109 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- PLL for 100 MHz speed +library altera_mf; +use altera_mf.all; + +entity de1_dac is + port ( CLOCK_50 : in std_ulogic; + SW : in std_ulogic_vector(9 downto 0); + KEY0 : in std_ulogic; + DAC_MODE : out std_ulogic; --1=dual port, 0=interleaved + DAC_WRT_A : out std_ulogic; + DAC_WRT_B : out std_ulogic; + DAC_CLK_A : out std_ulogic; -- PLL_OUT_DAC0 in User Manual + DAC_CLK_B : out std_ulogic; -- PLL_OUT_DAC1 in User Manual + DAC_DA : out std_ulogic_vector(13 downto 0); + DAC_DB : out std_ulogic_vector(13 downto 0); + ADC_CLK_A : out std_ulogic; + ADC_CLK_B : out std_ulogic; + POWER_ON : out std_ulogic; + ADC_OEB_A : out std_ulogic; + ADC_OEB_B : out std_ulogic; + LEDR : out std_ulogic_vector(9 downto 0)); -- red LEDs +end entity; + +architecture rtl of de1_dac is + + -- Altera PLL + component altpll + generic ( + clk0_divide_by : natural; + clk0_duty_cycle : natural; + clk0_multiply_by : natural; +-- clk0_phase_shift : STRING; +-- compensate_clock : STRING; + inclk0_input_frequency : natural; +-- intended_device_family : STRING; +-- lpm_hint : STRING; +-- lpm_type : STRING; + operation_mode : string; + port_inclk0 : string; + port_clk0 : string + ); + port ( + clk : out std_logic_vector (5 downto 0); + inclk : in std_logic_vector (1 downto 0) + ); + end component; + + signal pll_inclk : std_logic_vector(1 downto 0); + signal pll_outclk : std_logic_vector(5 downto 0); + + signal clk,rst_n : std_ulogic; + signal cnt : unsigned(13 downto 0); + signal phase_inc : unsigned(9 downto 0); + signal dac_a_reg, dac_a_next, dac_b_reg : unsigned(13 downto 0); + +begin + + pll_i0 : altpll + generic map ( + clk0_divide_by => 1, + clk0_duty_cycle => 50, + clk0_multiply_by => 2, +-- clk0_phase_shift => "0", +-- compensate_clock => "CLK0", + inclk0_input_frequency => 20000, + operation_mode => "NORMAL", + port_inclk0 => "PORT_USED", + port_clk0 => "PORT_USED" + ) + port map ( + inclk => pll_inclk, + clk => pll_outclk + ); + + pll_inclk(0) <= CLOCK_50; + pll_inclk(1) <= '0'; + + clk <= pll_outclk(0); + rst_n <= '0' when KEY0 = '0' else '1' when rising_edge (clk); + LEDR <= SW; + + DAC_MODE <= '1'; --dual port + DAC_CLK_A <= clk; + DAC_CLK_B <= clk; + DAC_WRT_A <= clk; + DAC_WRT_B <= clk; + + phase_inc <= unsigned(SW(9 downto 1) & '0'); + + cnt <= (others => '0') when rst_n = '0' else cnt+phase_inc when rising_edge(clk); + + dac_a_next <= (others => '1') when cnt = 0 else (others => '0'); + dac_a_reg <= (others => '0') when rst_n = '0' else dac_a_next when falling_edge(clk); + dac_b_reg <= (others => '0') when rst_n = '0' else cnt when falling_edge(clk); + DAC_DA <= std_ulogic_vector(dac_a_reg); + DAC_DB <= std_ulogic_vector(dac_b_reg); + + -- ADC Section - switch off everything + ADC_CLK_A <= '0'; + ADC_CLK_B <= '0'; + ADC_OEB_A <= '1'; + ADC_OEB_B <= '1'; + POWER_ON <= '1'; + +end architecture rtl; diff --git a/src/de1_matlab_audio.vhd b/src/de1_matlab_audio.vhd new file mode 100644 index 0000000..4d7e613 --- /dev/null +++ b/src/de1_matlab_audio.vhd @@ -0,0 +1,126 @@ +--Copyright 2013,2021 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library altera; +use altera.altera_primitives_components.all; + +entity de1_matlab_audio is + port ( + CLOCK_50: in std_ulogic; + KEY0: in std_ulogic; + SW: in std_ulogic_vector(9 downto 0); + I2C_SCLK: out std_ulogic; + I2C_SDAT: inout std_logic; + AUD_ADCLRCK: out std_ulogic; + AUD_ADCDAT: in std_ulogic; + AUD_DACLRCK: out std_ulogic; + AUD_DACDAT: out std_ulogic; + AUD_XCK: out std_ulogic; + AUD_BCLK: out std_ulogic; + LEDR: out std_ulogic_vector(9 downto 0)); +end; + +architecture struct of de1_matlab_audio is + + -- Matlab generated toplevel + component ml_audio is + port (clk : in std_logic; + rst_n : in std_logic; + clk_enable : in std_logic; + ce_out : out std_logic; + switches_i : in std_logic_vector(9 downto 0); + audio_i : in std_logic_vector(15 downto 0); + audio_o : out std_logic_vector(15 downto 0)); + end component; + + -- Wolfson AudioCodec Interface block + component audio is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + i2c_sclk_o : out std_ulogic; + i2c_dat_i : in std_ulogic; + i2c_dat_o : out std_ulogic; + aud_adclrck_o : out std_ulogic; + aud_adcdat_i : in std_ulogic; + aud_daclrck_o : out std_ulogic; + aud_dacdat_o : out std_ulogic; + aud_xck_o : out std_ulogic; + aud_bclk_o : out std_ulogic; + adc_data_o : out std_ulogic_vector(15 downto 0); + adc_valid_o : out std_ulogic; + dac_data_i : in std_ulogic_vector(15 downto 0); + dac_strobe_o : out std_ulogic); + end component; + + signal clk, reset_n : std_ulogic; + + signal i2c_dat_o : std_ulogic; + signal i2c_dat_i : std_ulogic; + + signal adc_valid : std_ulogic; + signal dac_strobe : std_ulogic; + signal dac_data : std_logic_vector(15 downto 0); + signal adc_data, dac_data_reg : std_ulogic_vector(15 downto 0); + signal ml_audio_out_valid : std_ulogic; + +begin + + reset_n <= KEY0; + clk <= CLOCK_50; + + ml_audio_i0 : ml_audio + port map ( + clk => clk, + rst_n => reset_n, + clk_enable => adc_valid, + ce_out => ml_audio_out_valid, + switches_i => std_logic_vector(SW), + audio_i => std_logic_vector(adc_data), + audio_o => dac_data); + + dac_data_reg <= std_ulogic_vector(dac_data) when rising_edge(clk) and ml_audio_out_valid = '1'; + + -- Wolfson Audio Codec + audio_i0 : audio + port map ( + clk_i => clk, + reset_ni => reset_n, + i2c_sclk_o => I2C_SCLK, + i2c_dat_i => i2c_dat_i, + i2c_dat_o => i2c_dat_o, + aud_adclrck_o => AUD_ADCLRCK, + aud_adcdat_i => AUD_ADCDAT, + aud_daclrck_o => AUD_DACLRCK, + aud_dacdat_o => AUD_DACDAT, + aud_xck_o => AUD_XCK, + aud_bclk_o => AUD_BCLK, + adc_data_o => adc_data, + adc_valid_o => adc_valid, + dac_data_i => dac_data_reg, + dac_strobe_o => dac_strobe); + + LEDR <= SW; + + -- i2c has an open-drain ouput + i2c_dat_i <= I2C_SDAT; + i2c_data_buffer_i : OPNDRN + port map (a_in => i2c_dat_o, a_out => I2C_SDAT); + +end; -- architecture diff --git a/src/de1_mux2to1_structure.vhd b/src/de1_mux2to1_structure.vhd new file mode 100644 index 0000000..33c1257 --- /dev/null +++ b/src/de1_mux2to1_structure.vhd @@ -0,0 +1,48 @@ +------------------------------------------------------------------------------- +-- Module : de1_mux2to1 +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: test the module add1 on a DE1 prototype board +-- connecting device under test (DUT) add1 +-- to input/output signals of the DE1 prototype board +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY de1_mux2to1 IS + PORT ( + SW : IN std_ulogic_vector(2 DOWNTO 0); -- Toggle Switch[2:0] + LEDR : OUT std_ulogic -- LED Red[0] + ); +END de1_mux2to1; + +ARCHITECTURE structure OF de1_mux2to1 IS + + COMPONENT mux2to1 + PORT ( + a_i : IN std_ulogic; + b_i : IN std_ulogic; + sel_i : IN std_ulogic; + y_o : OUT std_ulogic); + END COMPONENT; + +BEGIN + + -- connecting device under test with peripheral elements + DUT : mux2to1 + PORT MAP ( + a_i => SW(0), + b_i => SW(1), + sel_i => SW(2), + y_o => LEDR); + +END structure; +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- diff --git a/src/de1_sta.vhd b/src/de1_sta.vhd new file mode 100644 index 0000000..91a93aa --- /dev/null +++ b/src/de1_sta.vhd @@ -0,0 +1,32 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity de1_sta is + port ( + CLOCK_50 : in std_ulogic; + x_i : in unsigned(7 downto 0); + y_o : out unsigned(x_i'range) + ); +end de1_sta; + +architecture rtl of de1_sta is + +signal a,b,c,d : unsigned(x_i'range); +signal sum : unsigned(x_i'range); +signal clk : std_ulogic; + +begin + +clk <= CLOCK_50; + +sum <= a + b + c + d; + +y_o <= sum when rising_edge(clk); + +a <= x_i when rising_edge(clk); +b <= a when rising_edge(clk); +c <= b when rising_edge(clk); +d <= c when rising_edge(clk); + +end architecture; diff --git a/src/de1_tone.vhd b/src/de1_tone.vhd new file mode 100644 index 0000000..eff30f9 --- /dev/null +++ b/src/de1_tone.vhd @@ -0,0 +1,119 @@ +--Copyright 2013,2021 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library altera; +use altera.altera_primitives_components.all; + +entity de1_tone is + port ( + CLOCK_50 : in std_ulogic; + KEY0 : in std_ulogic; + I2C_SCLK : out std_ulogic; + I2C_SDAT : inout std_logic; + AUD_ADCLRCK : out std_ulogic; + AUD_ADCDAT : in std_ulogic; + AUD_DACLRCK : out std_ulogic; + AUD_DACDAT : out std_ulogic; + AUD_XCK : out std_ulogic; + AUD_BCLK : out std_ulogic; + SW : in std_ulogic_vector(9 downto 0); + LEDR : out std_ulogic_vector(9 downto 0)); +end; + +architecture struct of de1_tone is + + component audio is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + i2c_sclk_o : out std_ulogic; + i2c_dat_i : in std_ulogic; + i2c_dat_o : out std_ulogic; + aud_adclrck_o : out std_ulogic; + aud_adcdat_i : in std_ulogic; + aud_daclrck_o : out std_ulogic; + aud_dacdat_o : out std_ulogic; + aud_xck_o : out std_ulogic; + aud_bclk_o : out std_ulogic; + adc_data_o : out std_ulogic_vector(15 downto 0); + adc_valid_o : out std_ulogic; + dac_data_i : in std_ulogic_vector(15 downto 0); + dac_strobe_o : out std_ulogic); + end component; + + component tone is + port (clk : in std_ulogic; + rst_n : in std_ulogic; + switches_i : in std_ulogic_vector(9 downto 0); + dv_i : in std_ulogic; + audio_i : in std_ulogic_vector(15 downto 0); + audio_o : out std_ulogic_vector(15 downto 0)); + end component; + + signal clk, reset_n : std_ulogic; + + signal i2c_dat_o : std_ulogic; + signal i2c_dat_i : std_ulogic; + + signal adc_valid : std_ulogic; + signal dac_strobe : std_ulogic; + signal dac_data, adc_data : std_ulogic_vector(15 downto 0); + +begin + + reset_n <= KEY0; + clk <= CLOCK_50; + + audio_i0 : audio + port map ( + clk_i => clk, + reset_ni => reset_n, + i2c_sclk_o => I2C_SCLK, + i2c_dat_i => i2c_dat_i, + i2c_dat_o => i2c_dat_o, + aud_adclrck_o => AUD_ADCLRCK, + aud_adcdat_i => AUD_ADCDAT, + aud_daclrck_o => AUD_DACLRCK, + aud_dacdat_o => AUD_DACDAT, + aud_xck_o => AUD_XCK, + aud_bclk_o => AUD_BCLK, + adc_data_o => adc_data, + adc_valid_o => adc_valid, + dac_data_i => dac_data, + dac_strobe_o => dac_strobe); + + tone_i0 : tone + port map ( + clk => clk, + rst_n => reset_n, + dv_i => adc_valid, + audio_i => adc_data, + audio_o => dac_data, + switches_i => SW); + + LEDR(9 downto 0) <= SW; + + -- i2c has an open-drain ouput + i2c_dat_i <= I2C_SDAT; + i2c_data_buffer_i : OPNDRN + port map (a_in => i2c_dat_o, a_out => I2C_SDAT); + +end; -- architecture + + diff --git a/src/e_falling_edge_detector.vhd b/src/e_falling_edge_detector.vhd new file mode 100644 index 0000000..db0cb16 --- /dev/null +++ b/src/e_falling_edge_detector.vhd @@ -0,0 +1,34 @@ +------------------------------------------------------------------------------- +-- Module : falling_edge_detector +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: detects a falling edge of input signal x_i +-- and produces a high-active signal for one clock period at +-- output fall_o +-- clk_i __|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--| +-- x_i -----|___________________________________|----------- +-- fall_o ________|-----|______________________________________ +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY falling_edge_detector IS + PORT ( + clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + x_i : IN std_ulogic; + fall_o : OUT std_ulogic + ); +END falling_edge_detector; + + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- + diff --git a/src/fsgen.vhd b/src/fsgen.vhd new file mode 100644 index 0000000..e15deca --- /dev/null +++ b/src/fsgen.vhd @@ -0,0 +1,56 @@ +--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- Frame Sync Generator +-- The framesync is active for one bitclock cycle + +entity fsgen is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + bclk_falling_edge_en_i : in std_ulogic; + fs_o : out std_ulogic); +end; + +architecture rtl of fsgen is + constant max_count : integer := 127; + signal counter : integer range 0 to max_count; +begin + + fs_cnt_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + counter <= 0; + fs_o <= '0'; + elsif rising_edge(clk_i) then + if bclk_falling_edge_en_i = '1' then + fs_o <= '0'; + if counter = max_count then + counter <= 0; + fs_o <= '1'; + else + counter <= counter + 1; + end if; + end if; + end if; + end process fs_cnt_p; + +end; -- architecture + + diff --git a/src/i2c.vhd b/src/i2c.vhd new file mode 100644 index 0000000..f60cdbe --- /dev/null +++ b/src/i2c.vhd @@ -0,0 +1,245 @@ +--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- I2C or 2-Wire Bus +-- To start a transaction, pull the data line to 'L' while the clock is still 'H' +-- 7 Bits Address +-- 1 Bit R/W (0 = Write, 1 = Read) +-- 1 Bit ACK (from Slave 0 if o.k.) +-- 8 Bits Data 15..8 +-- 1 Bit Ack from slave (0 if o.k.) +-- 8 Bits Data 7..0 +-- 1 Bit Ack from slave (0 if o.k.) + + +entity i2c is + port ( + clk_i: in std_ulogic; + reset_ni: in std_ulogic; + load_i: in std_ulogic; + data_i: in std_ulogic_vector(23 downto 0); + i2c_clk_o: out std_ulogic; + i2c_dat_o: out std_ulogic; + i2c_dat_i: in std_ulogic; + busy_o: out std_ulogic + ); +end; + +architecture rtl of i2c is + + -- Clock divider section + constant fd_c : integer := 50000000/20000/2; -- 50 MHz system clock, 20 kHz I2C clock + signal clk_cnt : integer range 0 to fd_c; + signal clk_cnt_reset, clk_cnt_done : std_ulogic; + + -- i2c data register index + signal idx : integer range 0 to 27; + signal idx_inc : std_ulogic; + signal idx_reset : std_ulogic; + + -- i2c registers with and without data for the acknowledgment section + -- In cycle 8, 17 and 26 there is an i2c acknowledgement cycle where the master + -- drives Z and the slave will drive "0" when everything is o.k. + -- The input data from the interface is without these acknowledgement bits + signal load_i2c_reg_without_ack : std_ulogic; + signal i2c_reg_without_ack : std_ulogic_vector(23 downto 0); + signal i2c_reg_with_ack : std_ulogic_vector(0 to 27); + + -- Statemachine + type state_t is (idle_s, start_s, data_hold_s, data_s, clock_high_s, stop_s); + signal state, next_state : state_t; + + -- Selection for the i2c output data + type i2c_dat_sel_t is (sel_old, sel_reg, sel_one, sel_zero); + signal i2c_dat_sel : i2c_dat_sel_t; + + type i2c_clk_sel_t is (sel_old, sel_one, sel_zero); + signal i2c_clk_sel : i2c_clk_sel_t; + + signal i2c_clk : std_ulogic; + signal i2c_clk_new : std_ulogic; + signal i2c_dat : std_ulogic; + signal i2c_dat_new : std_ulogic; + +begin + + -- i2c register with ack build from i2c without ack + -- i2c data is transmitted msb first, so bus direction is changed also + i2c_reg_with_ack(0 to 7) <= i2c_reg_without_ack(23 downto 16); + i2c_reg_with_ack(8) <= '1'; + i2c_reg_with_ack(9 to 16) <= i2c_reg_without_ack(15 downto 8); + i2c_reg_with_ack(17) <= '1'; + i2c_reg_with_ack(18 to 25) <= i2c_reg_without_ack(7 downto 0); + i2c_reg_with_ack(26) <= '1'; + i2c_reg_with_ack(27) <= '0'; + + -- This process counts the clocks for reducing the clock speed + -- of the i2c clock + clk_cnt_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + clk_cnt <= 0; + elsif rising_edge(clk_i) then + if clk_cnt < fd_c then + clk_cnt <= clk_cnt + 1; + end if; + if clk_cnt_reset = '1' then + clk_cnt <= 0; + end if; + end if; + end process clk_cnt_p; + + clk_cnt_done <= '1' when clk_cnt = fd_c else '0'; + + -- This is the index for the i2c register. + i2c_idx_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + idx <= 0; + elsif rising_edge(clk_i) then + if idx_inc = '1' and idx < 27 then + idx <= idx + 1; + end if; + if idx_reset = '1' then + idx <= 0; + end if; + end if; + end process i2c_idx_p; + + -- This are the registered outputs for the i2c clock and data + i2c_out_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + i2c_clk <= '1'; + i2c_dat <= '1'; + elsif rising_edge(clk_i) then + i2c_dat <= i2c_dat_new; + i2c_clk <= i2c_clk_new; + end if; + end process i2c_out_p; + + -- The i2c register without ack data + i2c_data_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + i2c_reg_without_ack <= (others => '0'); + elsif rising_edge(clk_i) then + if load_i2c_reg_without_ack = '1' then + i2c_reg_without_ack <= data_i; + end if; + end if; + end process i2c_data_p; + + -- i2c data selection process + i2c_dat_sel_p : process(i2c_dat_sel, i2c_reg_with_ack, i2c_dat, idx) + begin + case i2c_dat_sel is + when sel_old => i2c_dat_new <= i2c_dat; + when sel_reg => i2c_dat_new <= i2c_reg_with_ack(idx); + when sel_one => i2c_dat_new <= '1'; + when sel_zero => i2c_dat_new <= '0'; + when others => i2c_dat_new <= '0'; + end case; + end process i2c_dat_sel_p; + + -- i2c clock selection process + i2c_clk_sel_p : process(i2c_clk, i2c_clk_sel) + begin + case i2c_clk_sel is + when sel_old => i2c_clk_new <= i2c_clk; + when sel_one => i2c_clk_new <= '1'; + when sel_zero => i2c_clk_new <= '0'; + when others => i2c_clk_new <= '0'; + end case; + end process i2c_clk_sel_p; + + -- Sequential process for the statemachine + statem_seq_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + state <= idle_s; + elsif rising_edge(clk_i) then + state <= next_state; + end if; + end process statem_seq_p; + + statem_comb_p: process(state, load_i, idx, clk_cnt_done) + begin + load_i2c_reg_without_ack<= '0'; + idx_inc <= '0'; + idx_reset <= '0'; + clk_cnt_reset <= '0'; + busy_o <= '1'; + i2c_dat_sel <= sel_old; + i2c_clk_sel <= sel_old; + next_state <= state; + case state is + when idle_s => + busy_o <= '0'; + i2c_clk_sel <= sel_one; + i2c_dat_sel <= sel_one; + if load_i = '1' then + load_i2c_reg_without_ack <= '1'; + clk_cnt_reset <= '1'; + idx_reset <= '1'; + next_state <= start_s; + i2c_dat_sel <= sel_zero; + end if; + when start_s => + if clk_cnt_done = '1' then + next_state <= data_hold_s; + clk_cnt_reset <= '1'; + i2c_clk_sel <= sel_zero; + end if; + when data_hold_s => + next_state <= data_s; + i2c_dat_sel <= sel_reg; + when data_s => + if clk_cnt_done = '1' then + next_state <= clock_high_s; + i2c_clk_sel <= sel_one; + clk_cnt_reset <= '1'; + end if; + when clock_high_s => + if clk_cnt_done = '1' then + if idx = 27 then -- last bit transmitted + i2c_dat_sel <= sel_one; + next_state <= stop_s; + else + idx_inc <= '1'; + i2c_clk_sel <= sel_zero; + next_state <= data_hold_s; + end if; + clk_cnt_reset <= '1'; + end if; + when stop_s => + if clk_cnt_done = '1' then + next_state <= idle_s; + end if; + when others => + next_state <= idle_s; + end case; + end process statem_comb_p; + + i2c_clk_o <= i2c_clk; + i2c_dat_o <= i2c_dat; + +end; -- architecture + + diff --git a/src/i2c_sub.vhd b/src/i2c_sub.vhd new file mode 100644 index 0000000..e71ff39 --- /dev/null +++ b/src/i2c_sub.vhd @@ -0,0 +1,79 @@ +--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity i2c_sub is + port ( + clk_i: in std_ulogic; + reset_ni: in std_ulogic; + i2c_dat_o: out std_ulogic; + i2c_dat_i: in std_ulogic; + i2c_clk_o: out std_ulogic); +end; + +architecture struct of i2c_sub is + +component i2c is + port ( + clk_i: in std_ulogic; + reset_ni: in std_ulogic; + load_i: in std_ulogic; + data_i: in std_ulogic_vector(23 downto 0); + i2c_clk_o: out std_ulogic; + i2c_dat_o: out std_ulogic; + i2c_dat_i: in std_ulogic; + busy_o: out std_ulogic + ); +end component; + +component i2c_write is + port ( + clk_i: in std_ulogic; + reset_ni: in std_ulogic; + load_o: out std_ulogic; + data_o: out std_ulogic_vector(23 downto 0); + busy_i: in std_ulogic); +end component; + + signal load, busy : std_ulogic; + signal data : std_ulogic_vector(23 downto 0); + +begin + + i2c_i0 : i2c + port map ( + clk_i => clk_i, + reset_ni => reset_ni, + load_i => load, + data_i => data, + i2c_clk_o => i2c_clk_o, + i2c_dat_o => i2c_dat_o, + i2c_dat_i => i2c_dat_i, + busy_o => busy); + + i2_write_i0 : i2c_write + port map ( + clk_i => clk_i, + reset_ni => reset_ni, + load_o => load, + data_o => data, + busy_i => busy); + +end; -- architecture + + diff --git a/src/i2c_write.vhd b/src/i2c_write.vhd new file mode 100644 index 0000000..338a3a7 --- /dev/null +++ b/src/i2c_write.vhd @@ -0,0 +1,98 @@ +--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity i2c_write is + port ( + clk_i: in std_ulogic; + reset_ni: in std_ulogic; + load_o: out std_ulogic; + data_o: out std_ulogic_vector(23 downto 0); + busy_i: in std_ulogic); +end; + +architecture rtl of i2c_write is + constant num_regs_c : integer := 12; + type state_t is (start_s, wait_s, done_s); + signal state, next_state : state_t; + signal counter : integer range 0 to num_regs_c-1; + signal counter_enable : std_ulogic; + type data_array_t is array(0 to num_regs_c-1) of std_ulogic_vector(23 downto 0); + + constant data_array : data_array_t := ( + X"341200", -- Set Inactive + X"341E00", -- Reset the Device + X"34001A", -- Left Line In / Mute off / Volume + X"34021A", -- Right Line In + X"34046F", -- Headphone Left + X"34066F", -- Headphone Right + X"340815", -- Analog path control (MIC to ADC, DAC to output, MIC Boost) + X"340A00", -- Digital path control + X"340C61", -- Power Down Control (Everything switched on) + X"340E13", -- Digital Audio Interface Format (Slave Mode, DSP Mode, 16 Bit) + X"341000", -- Sampling Control (48 kHz Sampling frequency, Normal Mode) + X"341201"); -- Active Control (Activate) + +begin + + seq_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + state <= start_s; + counter <= 0; + elsif rising_edge(clk_i) then + state <= next_state; + if counter_enable = '1' then + if counter < num_regs_c - 1 then + counter <= counter + 1; + else + counter <= 0; + end if; + end if; + end if; + end process seq_p; + + data_o <= data_array(counter); + + process(state, counter, busy_i) + begin + load_o <= '0'; + counter_enable <= '0'; + next_state <= state; + case state is + when start_s => + load_o <= '1'; + next_state <= wait_s; + when wait_s => + if busy_i = '0' then + if counter = num_regs_c-1 then + next_state <= done_s; + --counter_enable <= '1'; + else + next_state <= start_s; + counter_enable <= '1'; + end if; + end if; + when others => + next_state <= state; + end case; + end process; + +end; -- architecture + + diff --git a/src/invgate_equation.vhd b/src/invgate_equation.vhd new file mode 100644 index 0000000..69e920e --- /dev/null +++ b/src/invgate_equation.vhd @@ -0,0 +1,34 @@ +------------------------------------------------------------------------------- +-- Module : invgate +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: Inverter Gate +-- function modelled by logic equation +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY invgate IS + PORT (a_i : IN std_ulogic; -- data input a + y_o : OUT std_ulogic -- data output y + ); +END invgate; + +ARCHITECTURE equation OF invgate IS + +BEGIN + + y_o <= NOT a_i; + +END equation; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- + diff --git a/src/mclk.vhd b/src/mclk.vhd new file mode 100644 index 0000000..5da923d --- /dev/null +++ b/src/mclk.vhd @@ -0,0 +1,48 @@ +--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- Master Clock Generator +-- Generate 12.5 MHz from 50 MHz by dividing by 4 +-- Audio Codec expects 12.288 MHz, so we are slightly higher + +entity mclk is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + mclk_o : out std_ulogic); +end; + +architecture rtl of mclk is + signal mclk : unsigned(1 downto 0); +begin + + mclk_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + mclk <= to_unsigned(0, mclk'length); + elsif rising_edge(clk_i) then + mclk <= mclk + 1; + end if; + end process mclk_p; + + mclk_o <= mclk(1); + +end; -- architecture + + diff --git a/src/memory.vhd b/src/memory.vhd new file mode 100644 index 0000000..e50d687 --- /dev/null +++ b/src/memory.vhd @@ -0,0 +1,54 @@ +--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- This VHDL memory description will result in FPGA memory usage. +-- The EPC2C20 series provides a total of 52 M4K memory blocks +-- Each M4K memory block contains 4608 Bits. The following configurations are supported: +-- 4K 1, 2K 2, 1K 4, 512 8, 512 9, 256 16, 256 18 +-- The maximum is therefore 52 x 256 = 13312 samples. + +entity memory is + port ( + clk_i : in std_ulogic; + we_i : in std_ulogic; + waddr_i : in unsigned(12 downto 0); + raddr_i : in unsigned(12 downto 0); + wdata_i : in std_ulogic_vector(15 downto 0); + rdata_o : out std_ulogic_vector(15 downto 0) + ); +end; + +architecture rtl of memory is + type ram_t is array(0 to 2 ** 13 - 1) of std_ulogic_vector(15 downto 0); + signal ram : ram_t; +begin + + mem_p : process(clk_i) + begin + if rising_edge(clk_i) then + if we_i = '1' then + ram(to_integer(waddr_i)) <= wdata_i; + end if; + rdata_o <= ram(to_integer(raddr_i)); + end if; + end process mem_p; + +end; -- architecture + + diff --git a/src/mux2to1_equation.vhd b/src/mux2to1_equation.vhd new file mode 100644 index 0000000..0fddb6a --- /dev/null +++ b/src/mux2to1_equation.vhd @@ -0,0 +1,40 @@ +------------------------------------------------------------------------------- +-- Module : mux2to1 +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: 2-to-1 multiplexer +-- function modelled by boolean equation +-- sel = '1': a -> y +-- sel = '0': b -> y +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY mux2to1 IS + PORT (a_i : IN std_ulogic; -- data input a + b_i : IN std_ulogic; -- data input b + sel_i : IN std_ulogic; -- select which input is connected to y + -- sel = '1': a -> y + -- sel = '0': b -> y + y_o : OUT std_ulogic -- data output y + ); +END mux2to1; + +ARCHITECTURE equation OF mux2to1 IS + +BEGIN + + y_o <= (sel_i AND a_i) OR (NOT sel_i AND b_i); + +END equation; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- + diff --git a/src/mux2to1_rtl.vhd b/src/mux2to1_rtl.vhd new file mode 100644 index 0000000..c6447dd --- /dev/null +++ b/src/mux2to1_rtl.vhd @@ -0,0 +1,42 @@ +------------------------------------------------------------------------------- +-- Module : mux2to1 +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: 2-to-1 multiplexer +-- function modelled by a conditional signal assignment +-- sel = '1': a -> y +-- sel = '0': b -> y +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY mux2to1 IS + PORT (a_i : IN std_ulogic; -- data input a + b_i : IN std_ulogic; -- data input b + sel_i : IN std_ulogic; -- select which input is connected to y + -- sel = '1': a -> y + -- sel = '0': b -> y + y_o : OUT std_ulogic -- data output y + ); +END mux2to1; + +ARCHITECTURE rtl OF mux2to1 IS + +BEGIN + + y_o <= a_i WHEN sel_i = '1' ELSE + b_i WHEN sel_i = '0' ELSE + 'X'; + +END rtl; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- + diff --git a/src/mux2to1_structure.vhd b/src/mux2to1_structure.vhd new file mode 100644 index 0000000..3ff0c97 --- /dev/null +++ b/src/mux2to1_structure.vhd @@ -0,0 +1,90 @@ +------------------------------------------------------------------------------- +-- Module : mux2to1 +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: 2-to-1 multiplexer +-- function modelled as structure of basic logic gates +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY mux2to1 IS + PORT (a_i : IN std_ulogic; -- data input a + b_i : IN std_ulogic; -- data input b + sel_i : IN std_ulogic; -- select which input is connected to y + -- sel = '1': a -> y + -- sel = '0': b -> y + y_o : OUT std_ulogic -- data output y + ); +END mux2to1; + +ARCHITECTURE structure OF mux2to1 IS + + COMPONENT invgate + PORT ( + a_i : IN std_ulogic; + y_o : OUT std_ulogic); + END COMPONENT; + + COMPONENT and2gate + PORT ( + a_i : IN std_ulogic; + b_i : IN std_ulogic; + y_o : OUT std_ulogic); + END COMPONENT; + + COMPONENT or2gate + PORT ( + a_i : IN std_ulogic; + b_i : IN std_ulogic; + y_o : OUT std_ulogic); + END COMPONENT; + + SIGNAL p0, p1 : std_ulogic; + SIGNAL p2 : std_ulogic; + +BEGIN + + inv_gate_1 : invgate + PORT MAP ( + a_i => sel_i, + y_o => p2); + + and2_gate_1 : and2gate + PORT MAP ( + a_i => a_i, + b_i => sel_i, + y_o => p0); + + and2_gate_2 : and2gate + PORT MAP ( + a_i => b_i, + b_i => p2, + y_o => p1); + + or2_gate_1 : or2gate + PORT MAP ( + a_i => p0, + b_i => p1, + y_o => y_o); + +-- inv_gate_1 : invgate PORT MAP (sel_i, p2); + +-- and2_gate_1 : and2gate PORT MAP (a_i, sel_i, p0); + +-- and2_gate_2 : and2gate PORT MAP (b_i, p2, p1); + +-- or2_gate_1 : or2gate PORT MAP (p0, p1, y_o); + +END structure; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- + diff --git a/src/mux2to1_structure_errors.vhd b/src/mux2to1_structure_errors.vhd new file mode 100644 index 0000000..0b33968 --- /dev/null +++ b/src/mux2to1_structure_errors.vhd @@ -0,0 +1,79 @@ +------------------------------------------------------------------------------- +-- Module : mux2to1 +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: 2-to-1 multiplexer +-- function modelled as structure of basic logic gates +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY mux2to1 IS + PORT (a_i : IN std_ulogic; + b_i : IN std_ulogic; + sel_i : IN std_ulogic; +-- y_o : OUT std_ulogic; -- kein ; nach letztem Signal + y_o : OUT std_ulogic + ); +END mux21; + + +ARCHITECTURE structure OF mux2to1 IS + + COMPONENT invgate + PORT ( + a_i : IN std_ulogic; + y_o : OUT std_ulogic); + END COMPONENT; + + COMPONENT or2gate + PORT ( + a_i : IN std_ulogic; + b_i : IN std_ulogic; + y_o : std_ulogic); + END COMPONENT; + + SIGNAL p1 : std_ulogic; + SIGNAL p2 : std_ulogic; + SIGNAL p3 : std_ulogic; + +BEGIN + + inv_gate_1 : invgate + PORT MAP ( + a_i => sel_i, + y_o <= p2); + + + and2_gate_1 : and2gate + PORT MAP ( + a_i => a_i, + b_i => p2 + y_o => p0); + + and2_gate_2 : and2gate + PORT MAP ( + a_i => b_i, + b_i => sel_i, + y_o => p1); + + or2_gate_1 : or2gate + PORT MAP ( + a_i => p0, + b_i => p1, + y_o => p3); + + +END struct + + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- + diff --git a/src/mux2to1_truthtable.vhd b/src/mux2to1_truthtable.vhd new file mode 100644 index 0000000..ff84c61 --- /dev/null +++ b/src/mux2to1_truthtable.vhd @@ -0,0 +1,54 @@ +------------------------------------------------------------------------------- +-- Module : mux2to1 +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: 2-to-1 multiplexer +-- function modelled by a truth table +-- sel = '1': a -> y +-- sel = '0': b -> y +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY mux2to1 IS + PORT (a_i : IN std_ulogic; -- data input a + b_i : IN std_ulogic; -- data input b + sel_i : IN std_ulogic; -- select which input is connected to y + -- sel = '1': a -> y + -- sel = '0': b -> y + y_o : OUT std_ulogic -- data output y + ); +END mux2to1; + +ARCHITECTURE truthtable OF mux2to1 IS + + SIGNAL inputs_s : std_ulogic_vector(2 DOWNTO 0); -- temp input vector + +BEGIN + + inputs_s <= (sel_i, b_i, a_i); -- concatenate single signals to a vector + + tt : WITH inputs_s SELECT -- truthtable + y_o <= + '0' WHEN "000", + '0' WHEN "001", + '1' WHEN "010", + '1' WHEN "011", + '0' WHEN "100", + '1' WHEN "101", + '0' WHEN "110", + '1' WHEN "111", + 'X' WHEN OTHERS; + +END truthtable; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- + diff --git a/src/or2gate_equation.vhd b/src/or2gate_equation.vhd new file mode 100644 index 0000000..13795fb --- /dev/null +++ b/src/or2gate_equation.vhd @@ -0,0 +1,18 @@ +------------------------------------------------------------------------------- +-- Module : or2gate +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: 2-input OR Gate +-- function modelled by logic equation +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- + + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- diff --git a/src/play_rtl.vhd b/src/play_rtl.vhd new file mode 100644 index 0000000..8452236 --- /dev/null +++ b/src/play_rtl.vhd @@ -0,0 +1,101 @@ +------------------------------------------------------------------ +-- module : play +------------------------------------------------------------------ +-- author : Friedrich Beckmann +-- company : university of applied sciences augsburg +------------------------------------------------------------------ +-- description: Statemachine for LED game +-- +------------------------------------------------------------------ +-- revisions : 0.1 - +------------------------------------------------------------------ + +-- 5 LED outputs +-- One one-second enable input +-- KEY input with preceding rising_edge detector + +-- step LED4 LED3 LED2 LED1 LED0 +-- 1 x - - - - +-- 2 - x - - - +-- 3 - - x - - +-- 4 - - - x - +-- 5 - - - - x +-- 6 x - - - - +-- ... this pattern continues +-- If LED2 is on and KEY is pressed then the pattern continues as follows +-- 1 x - - - - +-- 2 - - - - x +-- ... this pattern continues until +-- KEY is pressed again. Then the previous pattern restarts from LED 2 + +library ieee; +use ieee.std_logic_1164.all; + +entity play is + port (clk : in std_ulogic; + rst_n : in std_ulogic; + onesec_i : in std_ulogic; + key_i : in std_ulogic; + led_o : out std_ulogic_vector(4 downto 0)); +end play; + +architecture rtl of play is + + type state_t is (start_s,one_s,chance_s,four_s,last_s,hit0_s,hit1_s); + signal current_state,next_state : state_t; + +begin + + current_state <= start_s when rst_n = '0' else next_state when rising_edge(clk); + + next_p : process(current_state, onesec_i, key_i) + begin + next_state <= current_state; + led_o <= "00000"; + case current_state is + when start_s => + led_o <= "10000"; + if onesec_i = '1' then + next_state <= one_s; + end if; + when one_s => + led_o <= "01000"; + if onesec_i = '1' then + next_state <= chance_s; + end if; + when chance_s => + led_o <= "00100"; + if key_i = '1' then + next_state <= hit0_s; + elsif onesec_i = '1' then + next_state <= four_s; + end if; + when four_s => + led_o <= "00010"; + if onesec_i = '1' then + next_state <= last_s; + end if; + when last_s => + led_o <= "00001"; + if onesec_i = '1' then + next_state <= start_s; + end if; + when hit0_s => + led_o <= "10000"; + if key_i = '1' then + next_state <= chance_s; + elsif onesec_i = '1' then + next_state <= hit1_s; + end if; + when hit1_s => + led_o <= "00001"; + if key_i = '1' then + next_state <= chance_s; + elsif onesec_i = '1' then + next_state <= hit0_s; + end if; + when others => null; + end case; + end process; + +end architecture rtl; diff --git a/src/ringbuf.vhd b/src/ringbuf.vhd new file mode 100644 index 0000000..7c45815 --- /dev/null +++ b/src/ringbuf.vhd @@ -0,0 +1,74 @@ +--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- Ring Buffer stores samples in a circular buffer +-- The read buffer pointer is one buffer entry ahead +-- of the write buffer pointer. + +entity ringbuf is + port ( + clk_i : in std_ulogic; + reset_ni : in std_ulogic; + en_i : in std_ulogic; + data_i : in std_ulogic_vector(15 downto 0); + data_o : out std_ulogic_vector(15 downto 0)); +end; + +architecture rtl of ringbuf is + +component memory is + port ( + clk_i : in std_ulogic; + we_i : in std_ulogic; + waddr_i : in unsigned(12 downto 0); + raddr_i : in unsigned(12 downto 0); + wdata_i : in std_ulogic_vector(15 downto 0); + rdata_o : out std_ulogic_vector(15 downto 0) + ); +end component; + + signal raddr, waddr : unsigned(12 downto 0); + +begin + + mem_i0 : memory + port map ( + clk_i => clk_i, + we_i => en_i, + raddr_i => raddr, + waddr_i => waddr, + rdata_o => data_o, + wdata_i => data_i); + + buffer_pointer_p : process(clk_i, reset_ni) + begin + if reset_ni = '0' then + waddr <= to_unsigned(0, 13); + raddr <= to_unsigned(1, 13); + elsif rising_edge(clk_i) then + if en_i = '1' then + raddr <= raddr + 1; + waddr <= waddr + 1; + end if; + end if; + end process buffer_pointer_p; + +end; -- architecture + + diff --git a/src/t_cntdn.vhd b/src/t_cntdn.vhd new file mode 100644 index 0000000..42888c6 --- /dev/null +++ b/src/t_cntdn.vhd @@ -0,0 +1,123 @@ +------------------------------------------------------------------------------- +-- Module : t_cntdn +------------------------------------------------------------------------------- +-- Author : +-- Company : University of Applied Sciences Augsburg +-- Copyright (c) 2011 +------------------------------------------------------------------------------- +-- Description: Testbench for design "cntdn" +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +ENTITY t_cntdn IS +END t_cntdn; + +ARCHITECTURE tbench OF t_cntdn IS + + COMPONENT cntdn + PORT ( + clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + en_pi : IN std_ulogic; + count_o : OUT std_ulogic_vector(3 DOWNTO 0); + tc_o : OUT std_ulogic); + END COMPONENT; + + -- definition of a clock period + CONSTANT period : time := 10 ns; + -- switch for clock generator + SIGNAL clken_p : boolean := true; + + -- component ports + SIGNAL clk_i : std_ulogic; + SIGNAL rst_ni : std_ulogic; + SIGNAL en_pi : std_ulogic; + SIGNAL count_o : std_ulogic_vector(3 DOWNTO 0); + SIGNAL tc_o : std_ulogic; + +BEGIN -- tbench + + -- component instantiation + DUT : cntdn + PORT MAP ( + clk_i => clk_i, + rst_ni => rst_ni, + en_pi => en_pi, + count_o => count_o, + tc_o => tc_o); + + -- clock generation + clock_proc : PROCESS + BEGIN + WHILE clken_p LOOP + clk_i <= '0'; WAIT FOR period/2; + clk_i <= '1'; WAIT FOR period/2; + END LOOP; + WAIT; + END PROCESS; + + -- initial reset, always necessary at the beginning of a simulation + -- initial reset, always necessary at the beginning of a simulation + ----------------------------------------------------------------------------- + -- Following a verification plan: + -- ------------------------------ + -- 1. t = 0 ns: activate asynchronous reset + -- 2. t = 10 ns: deactivate asynchronous reset + ----------------------------------------------------------------------------- + reset : rst_ni <= '0', '1' AFTER period; + + stimuli_p : PROCESS + + BEGIN + + --------------------------------------------------------------------------- + -- ... continuing with the verification plan: + --------------------------------------------------------------------------- + WAIT UNTIL rising_edge(rst_ni); -- wait for reset + -- ... is deactivated + --------------------------------------------------------------------------- + + --------------------------------------------------------------------------- + -- 2. activate enable + -- 3. Wait for a full counting cycle + --------------------------------------------------------------------------- + + --------------------------------------------------------------------------- + + + --------------------------------------------------------------------------- + -- 4. After another five periods: Deactivate Enable + --------------------------------------------------------------------------- + + --------------------------------------------------------------------------- + + --------------------------------------------------------------------------- + -- 5. After another three periods: Activate Enable + -- 6. Simulate another complete counting cycle + --------------------------------------------------------------------------- + + --------------------------------------------------------------------------- + + --------------------------------------------------------------------------- + -- 7. Simulate until tc_o = 1 again + --------------------------------------------------------------------------- + + --------------------------------------------------------------------------- + + + clken_p <= false; -- switch clock generator off + + WAIT; -- suspend proces + END PROCESS; + +END tbench; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- diff --git a/src/t_cntdnmodm.vhd b/src/t_cntdnmodm.vhd new file mode 100644 index 0000000..5b3b9e3 --- /dev/null +++ b/src/t_cntdnmodm.vhd @@ -0,0 +1,157 @@ +------------------------------------------------------------------------------- +-- Module : t_cntdnmodm +------------------------------------------------------------------------------- +-- Author : +-- Company : University of Applied Sciences Augsburg +-- Copyright (c) 2013 +------------------------------------------------------------------------------- +-- Description: Testbench for design "cntdnmodm" +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +ENTITY t_cntdnmodm IS +END t_cntdnmodm; + +ARCHITECTURE tbench OF t_cntdnmodm IS + + COMPONENT cntdnmodm + GENERIC ( + n : natural; + m : natural); + PORT ( + clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + en_pi : IN std_ulogic; + count_o : OUT std_ulogic_vector(n-1 DOWNTO 0); + tc_o : OUT std_ulogic); + END COMPONENT; + + -- component generics + CONSTANT n : natural := 4; + CONSTANT m : natural := 10; + + -- component ports + SIGNAL clk_i : std_ulogic; + SIGNAL rst_ni : std_ulogic; + SIGNAL en_pi : std_ulogic; + SIGNAL count_o : std_ulogic_vector(n-1 DOWNTO 0); + SIGNAL tc_o : std_ulogic; + + SIGNAL count_mod6_o : std_ulogic_vector(2 DOWNTO 0); + SIGNAL tc_mod6_o : std_ulogic; + + SIGNAL count_mod500e3_o : std_ulogic_vector(18 DOWNTO 0); + SIGNAL tc_100hz_o : std_ulogic; + + + -- definition of a clock period + CONSTANT period : time := 20 ns; + -- switch for clock generator + SIGNAL clken_p : boolean := true; + +BEGIN -- tbench + + -- component instantiation + MUV : cntdnmodm + GENERIC MAP ( + n => n, + m => m) + PORT MAP ( + clk_i => clk_i, + rst_ni => rst_ni, + en_pi => en_pi, + count_o => count_o, + tc_o => tc_o); + + mod6_count : cntdnmodm + GENERIC MAP ( + n => 3, + m => 6) + PORT MAP ( + clk_i => clk_i, + rst_ni => rst_ni, + en_pi => en_pi, + count_o => count_mod6_o, + tc_o => tc_mod6_o); + + -- instantiate and parameterise the generics to + -- create a frequency of 100 Hz at its output signal tc_100hz_o + -- declare the necessary signals count_modxxx_o and tc_100hz_o + ----------------------------------------------------------------------------- +-- prescaler : cntdnmodm +-- GENERIC MAP ( +-- n => +-- m => ) +-- PORT MAP ( + ----------------------------------------------------------------------------- + + + -- clock generation + clock_p : PROCESS + BEGIN + WHILE clken_p LOOP + clk_i <= '0'; WAIT FOR period/2; + clk_i <= '1'; WAIT FOR period/2; + END LOOP; + WAIT; + END PROCESS; + + -- initial reset + reset : rst_ni <= '1', '0' AFTER period, + '1' AFTER 2 * period; + + -- process for stimuli generation + stimuli_p : PROCESS + + BEGIN + + WAIT UNTIL rising_edge(rst_ni); -- wait for reset + + en_pi <= '1'; -- activate counter + + + -- wait for a period of tc_o ---------------------------------------------- + WAIT UNTIL rising_edge(tc_o); + WAIT UNTIL falling_edge(tc_o); + + WAIT UNTIL count_o = X"5"; + + en_pi <= '0'; -- stop counter ... + WAIT FOR 3* period; -- ... for 3 periods + + en_pi <= '1'; -- activate counter + + -- wait for a period of tc_mod6_o ----------------------------------------- + WAIT UNTIL rising_edge(tc_mod6_o); + WAIT UNTIL falling_edge(tc_mod6_o); + --------------------------------------------------------------------------- + + + -- wait for a period of tc_100hz_o ---------------------------------------- + + --------------------------------------------------------------------------- + + + -- wait for a period of tc_100hz_o ---------------------------------------- + + --------------------------------------------------------------------------- + + + clken_p <= false; -- switch clock generator off + + WAIT; + END PROCESS; + + + +END tbench; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- diff --git a/src/t_de1_audio.vhd b/src/t_de1_audio.vhd new file mode 100644 index 0000000..bfa0f1f --- /dev/null +++ b/src/t_de1_audio.vhd @@ -0,0 +1,88 @@ +--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity t_de1_audio is +end; + +architecture tbench of t_de1_audio is + +component de1_audio is + port ( + CLOCK_50: in std_ulogic; + KEY0: in std_ulogic; + I2C_SCLK: out std_ulogic; + I2C_SDAT: inout std_ulogic; + AUD_ADCLRCK: out std_ulogic; + AUD_ADCDAT: in std_ulogic; + AUD_DACLRCK: out std_ulogic; + AUD_DACDAT: out std_ulogic; + AUD_XCK: out std_ulogic; + AUD_BCLK: out std_ulogic; + LEDR: out std_ulogic_vector(9 downto 0) + ); +end component; + + signal clk, reset_n : std_ulogic; + signal ledr : std_ulogic_vector(9 downto 0); + signal i2c_clk, i2c_dat : std_ulogic; + signal key0 : std_ulogic; + + signal aud_adclrck, aud_adcdat, aud_daclrck, aud_dacdat, aud_xck, aud_bclk : std_ulogic; + + signal simrun : boolean := true; + +begin + + de1_audio_i0 : de1_audio + port map ( + CLOCK_50 => clk, + KEY0 => reset_n, + I2C_SCLK => i2c_clk, + I2C_SDAT => i2c_dat, + AUD_ADCLRCK => aud_adclrck, + AUD_ADCDAT => aud_adcdat, + AUD_DACLRCK => aud_daclrck, + AUD_DACDAT => aud_dacdat, + AUD_XCK => aud_xck, + AUD_BCLK => aud_bclk, + LEDR => ledr); + + clock_p : process + begin + clk <= '0'; + wait for 10 ns; + clk <= '1'; + wait for 10 ns; + if not simrun then + wait; + end if; + end process clock_p; + + simrun <= false after 1 ms; + + reset_p : process + begin + reset_n <= '0'; + wait for 15 us; + reset_n <= '1'; + wait; + end process reset_p; + + aud_adcdat <= '1'; + +end; -- architecture diff --git a/src/t_de1_play.vhd b/src/t_de1_play.vhd new file mode 100644 index 0000000..8a2b739 --- /dev/null +++ b/src/t_de1_play.vhd @@ -0,0 +1,100 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +entity t_de1_play is +end t_de1_play; + +architecture tbench of t_de1_play is + +component de1_play is + port ( + CLOCK_50 : in std_ulogic; -- 50 mhz clock + KEY : in std_ulogic_vector(1 downto 0); -- key(1..0) + I2C_SCLK : out std_ulogic; + I2C_SDAT : inout std_logic; + AUD_ADCLRCK : out std_ulogic; + AUD_ADCDAT : in std_ulogic; + AUD_DACLRCK : out std_ulogic; + AUD_DACDAT : out std_ulogic; + AUD_XCK : out std_ulogic; + AUD_BCLK : out std_ulogic; + LEDR : out std_ulogic_vector(4 downto 0); -- red LED(4..0) + LEDG : out std_ulogic_vector(1 downto 0) -- green LED(1..0) + ); +end component; + + -- definition of a clock period + constant period : time := 10 ns; + -- switch for clock generator + signal clken_p : boolean := true; + + + signal clk_i : std_ulogic; + signal rst_ni : std_ulogic; + signal key : std_ulogic; + signal ledr : std_ulogic_vector(4 downto 0); + + signal i2c_clk, i2c_dat : std_ulogic; + signal aud_adclrck, aud_adcdat, aud_daclrck, aud_dacdat, aud_xck, aud_bclk : std_ulogic; + signal phase : real := 0.0; + signal test_tone : real; + signal test_tone_quantized : signed(15 downto 0); + signal bit_count : integer range 0 to 31; + +begin + + -- clock generation + clock_proc : process + begin + while clken_p loop + clk_i <= '0'; wait for period/2; + clk_i <= '1'; wait for period/2; + end loop; + wait; + end process; + + -- initial reset, always necessary at the beginning of a simulation + reset : rst_ni <= '0', '1' AFTER period; + + stimuli_p : process + begin + key <= '1'; + wait until rst_ni = '1'; + wait for 20*period; + key <= '0'; + wait for 10*period; + key <= '1'; + wait for 30*period; + clken_p <= false; + wait; + end process stimuli_p; + + + de1_play_i0 : de1_play + port map ( + CLOCK_50 => clk_i, + KEY(0) => rst_ni, + KEY(1) => key, + I2C_SCLK => i2c_clk, + I2C_SDAT => i2c_dat, + AUD_ADCLRCK => aud_adclrck, + AUD_ADCDAT => aud_adcdat, + AUD_DACLRCK => aud_daclrck, + AUD_DACDAT => aud_dacdat, + AUD_XCK => aud_xck, + AUD_BCLK => aud_bclk, + LEDR => ledr); + + aud_adcdat <= test_tone_quantized(bit_count mod 16); + + -- Test tone generator for simulating the ADC from the audio codec + phase <= phase + 1.0/48.0 when rising_edge(aud_daclrck); + test_tone <= sin(2*3.14*phase); + test_tone_quantized <= to_signed(integer(test_tone * real(2**15-1)), 16); + bit_count <= 31 when falling_edge(aud_daclrck) else + 0 when bit_count = 0 else + bit_count - 1 when falling_edge(aud_bclk); + +end tbench; diff --git a/src/t_de1_tone.vhd b/src/t_de1_tone.vhd new file mode 100644 index 0000000..37d9e6b --- /dev/null +++ b/src/t_de1_tone.vhd @@ -0,0 +1,108 @@ +--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +entity t_de1_tone is +end; + +architecture tbench of t_de1_tone is + + component de1_tone is + port ( + CLOCK_50 : in std_ulogic; + KEY0 : in std_ulogic; + I2C_SCLK : out std_ulogic; + I2C_SDAT : inout std_ulogic; + AUD_ADCLRCK : out std_ulogic; + AUD_ADCDAT : in std_ulogic; + AUD_DACLRCK : out std_ulogic; + AUD_DACDAT : out std_ulogic; + AUD_XCK : out std_ulogic; + AUD_BCLK : out std_ulogic; + SW : in std_ulogic_vector(9 downto 0); + LEDR : out std_ulogic_vector(9 downto 0) + ); + end component; + + signal clk, reset_n : std_ulogic; + signal ledr : std_ulogic_vector(9 downto 0); + signal i2c_clk, i2c_dat : std_ulogic; + signal key0 : std_ulogic; + + signal aud_adclrck, aud_adcdat, aud_daclrck, aud_dacdat, aud_xck, aud_bclk : std_ulogic; + + signal simrun : boolean := true; + + signal phase : real := 0.0; + signal test_tone : real; + signal test_tone_quantized : signed(15 downto 0); + signal bit_count : integer range 0 to 31; + signal switches : std_ulogic_vector(9 downto 0); + +begin + + de1_tone_i0 : de1_tone + port map ( + CLOCK_50 => clk, + KEY0 => reset_n, + I2C_SCLK => i2c_clk, + I2C_SDAT => i2c_dat, + AUD_ADCLRCK => aud_adclrck, + AUD_ADCDAT => aud_adcdat, + AUD_DACLRCK => aud_daclrck, + AUD_DACDAT => aud_dacdat, + AUD_XCK => aud_xck, + AUD_BCLK => aud_bclk, + SW => switches, + LEDR => ledr); + + clock_p : process + begin + clk <= '0'; + wait for 10 ns; + clk <= '1'; + wait for 10 ns; + if not simrun then + wait; + end if; + end process clock_p; + + simrun <= false after 5 ms; + + reset_p : process + begin + reset_n <= '0'; + wait for 15 us; + reset_n <= '1'; + wait; + end process reset_p; + + aud_adcdat <= test_tone_quantized(bit_count mod 16); + + -- Test tone generator for simulating the ADC from the audio codec + phase <= phase + 1.0/48.0 when rising_edge(aud_daclrck); + test_tone <= sin(2*3.14*phase); + test_tone_quantized <= to_signed(integer(test_tone * real(2**15-1)), 16); + bit_count <= 31 when falling_edge(aud_daclrck) else + 0 when bit_count = 0 else + bit_count - 1 when falling_edge(aud_bclk); + + + +end; -- architecture diff --git a/src/t_falling_edge_detector.vhd b/src/t_falling_edge_detector.vhd new file mode 100644 index 0000000..9fda089 --- /dev/null +++ b/src/t_falling_edge_detector.vhd @@ -0,0 +1,116 @@ +------------------------------------------------------------------------------- +-- Module : t_falling_edge_detector +------------------------------------------------------------------------------- +-- Author : +-- Company : University of Applied Sciences Augsburg +-- Copyright (c) 2011 +------------------------------------------------------------------------------- +-- Description: Testbench for design "falling_edge_detector" +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +------------------------------------------------------------------------------- + +ENTITY t_falling_edge_detector IS +END t_falling_edge_detector; + +------------------------------------------------------------------------------- + +ARCHITECTURE tbench OF t_falling_edge_detector IS + + COMPONENT falling_edge_detector + PORT ( + clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + x_i : IN std_ulogic; + fall_o : OUT std_ulogic); + END COMPONENT; + + -- definition of a clock period + CONSTANT period : time := 10 ns; + -- switch for clock generator + SIGNAL clken_p : boolean := true; + + -- component ports + SIGNAL clk_i : std_ulogic; + SIGNAL rst_ni : std_ulogic; + SIGNAL x_i : std_ulogic; + SIGNAL fall_o : std_ulogic; + +BEGIN -- tbench + + -- component instantiation + MUV : falling_edge_detector + PORT MAP ( + clk_i => clk_i, + rst_ni => rst_ni, + x_i => x_i, + fall_o => fall_o); + + -- clock generation + clock_p : PROCESS + BEGIN + WHILE clken_p LOOP + clk_i <= '0'; WAIT FOR period/2; + clk_i <= '1'; WAIT FOR period/2; + END LOOP; + WAIT; + END PROCESS; + + -- initial reset, always necessary at the beginning of a simulation + reset : rst_ni <= '0', '1' AFTER period; + + + stimuli_p : PROCESS + BEGIN + + WAIT UNTIL rst_ni = '1'; -- wait until asynchronous reset ... + -- ... is deactivated + --------------------------------------------------------------------------- + + -- create a low-active pulse over a no. of clock periods + --------------------------------------------------------------------------- + x_i <= '1'; -- assign a '1' to x_i + WAIT FOR period; + + x_i <= '0'; -- set input to '0' ... + WAIT UNTIL rising_edge(clk_i); + WAIT UNTIL falling_edge(clk_i); + -- Observer: check, if fall_o is assigned to '1' for one clock period + ASSERT fall_o = '1' REPORT "Error: Expected fall_o = '1' !" SEVERITY failure; + WAIT UNTIL falling_edge(clk_i); + ASSERT fall_o = '0' REPORT "Error: Expected fall_o = '0' !" SEVERITY failure; + WAIT FOR 6 * period; -- ... for a no. of periods + + x_i <= '1'; -- assign a '1' to form a + WAIT FOR 3 * period; -- low active input pulse + --------------------------------------------------------------------------- + + + -- add another low-active input pulse here ... + + + + + + + + + + clken_p <= false; -- switch clock generator off + + WAIT; -- suspend proces + END PROCESS; + + +END tbench; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- diff --git a/src/t_mux2to1.vhd b/src/t_mux2to1.vhd new file mode 100644 index 0000000..4d4d118 --- /dev/null +++ b/src/t_mux2to1.vhd @@ -0,0 +1,81 @@ +------------------------------------------------------------------------------- +-- Module : t_mux2to1 +------------------------------------------------------------------------------- +-- Author : +-- Company : University of Applied Sciences Augsburg +-- Copyright (c) 2011 +------------------------------------------------------------------------------- +-- Description: Testbench for design "mux2to1" +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +------------------------------------------------------------------------------- + +ENTITY t_mux2to1 IS +END t_mux2to1; + +------------------------------------------------------------------------------- + +ARCHITECTURE tbench OF t_mux2to1 IS + + COMPONENT mux2to1 + PORT ( + a_i : IN std_ulogic; + b_i : IN std_ulogic; + sel_i : IN std_ulogic; + y_o : OUT std_ulogic); + END COMPONENT; + + -- definition of a clock period + CONSTANT period : time := 10 ns; + + -- component ports + SIGNAL a_i : std_ulogic; + SIGNAL b_i : std_ulogic; + SIGNAL sel_i : std_ulogic; + SIGNAL y_o : std_ulogic; + +BEGIN -- tbench + + -- component instantiation + MUV : mux2to1 + PORT MAP ( + a_i => a_i, + b_i => b_i, + sel_i => sel_i, + y_o => y_o); + + stimuli_p : PROCESS + + BEGIN + a_i <= '0'; -- set a value to input a_i + b_i <= '0'; -- set a value to input b_i + sel_i <= '0'; -- set a value to input ci_i + WAIT FOR period; -- values are assigned here + + a_i <= '1'; -- change value of a_i + WAIT FOR period; + + a_i <= '0'; -- change value of a_i + b_i <= '1'; -- change value of b_i + WAIT FOR period; + + + -- add the missing stimuli here ... + + + + WAIT; + END PROCESS; + +END tbench; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- diff --git a/src/tone_rtl.vhd b/src/tone_rtl.vhd new file mode 100644 index 0000000..815ebb8 --- /dev/null +++ b/src/tone_rtl.vhd @@ -0,0 +1,19 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity tone is + port (clk : in std_ulogic; + rst_n : in std_ulogic; + switches_i : in std_ulogic_vector(9 downto 0); + dv_i : in std_ulogic; + audio_i : in std_ulogic_vector(15 downto 0); + audio_o : out std_ulogic_vector(15 downto 0)); +end entity; + +architecture rtl of tone is + +begin + +audio_o <= audio_i when rising_edge(clk) and dv_i = '1'; + +end architecture rtl; -- cgit v1.2.3