From a04bbf15b0f51696894e37f3e566998108aefd74 Mon Sep 17 00:00:00 2001
From: Johann Faerber <johann.faerber@hs-augsburg.de>
Date: Wed, 9 Mar 2022 09:48:43 +0100
Subject: added basic design directory structure

---
 pnr/de1_audio/makefile | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
 create mode 100644 pnr/de1_audio/makefile

(limited to 'pnr/de1_audio/makefile')

diff --git a/pnr/de1_audio/makefile b/pnr/de1_audio/makefile
new file mode 100644
index 0000000..0a8636c
--- /dev/null
+++ b/pnr/de1_audio/makefile
@@ -0,0 +1,16 @@
+SIM_PROJECT_NAME = de1_audio
+PROJECT = $(SIM_PROJECT_NAME)
+
+# Here the VHDL files for synthesis are defined. 
+include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
+
+# Add the toplevel fpga vhdl file
+SOURCE_FILES = $(SYN_SOURCE_FILES)
+
+FAMILY = "Cyclone II"
+DEVICE = EP2C20F484C7
+PROGFILEEXT = sof
+
+include ../makefile
+
+
-- 
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