From 9b7fdebd9319e3e6560ff5b3a7ad750a6957a1da Mon Sep 17 00:00:00 2001 From: Matthias Kamuf Date: Mon, 16 May 2022 16:46:04 +0200 Subject: Added FIR design files for DE1 top level --- pnr/de1_fir/makefile | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100755 pnr/de1_fir/makefile (limited to 'pnr/de1_fir/makefile') diff --git a/pnr/de1_fir/makefile b/pnr/de1_fir/makefile new file mode 100755 index 0000000..7a271a4 --- /dev/null +++ b/pnr/de1_fir/makefile @@ -0,0 +1,27 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with Quartus, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +SIM_PROJECT_NAME = fir +PROJECT = de1_$(SIM_PROJECT_NAME) + +# Prototype Board FPGA family and device settings +FAMILY = "Cyclone II" +DEVICE = EP2C20F484C7 +PROGFILEEXT = sof + +# Here the VHDL files for synthesis are defined. +include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources + +# Add the toplevel fpga vhdl file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/$(PROJECT)_structure.vhd + +include ../makefile -- cgit v1.2.3