From a04bbf15b0f51696894e37f3e566998108aefd74 Mon Sep 17 00:00:00 2001
From: Johann Faerber <johann.faerber@hs-augsburg.de>
Date: Wed, 9 Mar 2022 09:48:43 +0100
Subject: added basic design directory structure

---
 pnr/de1_tone/makefile | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
 create mode 100644 pnr/de1_tone/makefile

(limited to 'pnr/de1_tone/makefile')

diff --git a/pnr/de1_tone/makefile b/pnr/de1_tone/makefile
new file mode 100644
index 0000000..e9cf6e6
--- /dev/null
+++ b/pnr/de1_tone/makefile
@@ -0,0 +1,14 @@
+SIM_PROJECT_NAME = de1_tone
+PROJECT = $(SIM_PROJECT_NAME)
+
+# Here the VHDL files for synthesis are defined. 
+include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
+
+# Add the toplevel fpga vhdl file
+SOURCE_FILES = $(SYN_SOURCE_FILES)
+
+FAMILY = "Cyclone II"
+DEVICE = EP2C20F484C7
+PROGFILEEXT = sof
+
+include ../makefile
-- 
cgit v1.2.3