From a04bbf15b0f51696894e37f3e566998108aefd74 Mon Sep 17 00:00:00 2001 From: Johann Faerber Date: Wed, 9 Mar 2022 09:48:43 +0100 Subject: added basic design directory structure --- scripts/create_quartus_project_settings.tcl | 84 +++++++ scripts/de1_pin_assignments_minimumio.tcl | 282 ++++++++++++++++++++++ scripts/modelsim.ini | 351 ++++++++++++++++++++++++++++ scripts/quartus_project_flow.tcl | 84 +++++++ 4 files changed, 801 insertions(+) create mode 100644 scripts/create_quartus_project_settings.tcl create mode 100644 scripts/de1_pin_assignments_minimumio.tcl create mode 100644 scripts/modelsim.ini create mode 100644 scripts/quartus_project_flow.tcl (limited to 'scripts') diff --git a/scripts/create_quartus_project_settings.tcl b/scripts/create_quartus_project_settings.tcl new file mode 100644 index 0000000..ab55593 --- /dev/null +++ b/scripts/create_quartus_project_settings.tcl @@ -0,0 +1,84 @@ +## ---------------------------------------------------------------------------- +## Script : create_quartus_project_settings.tcl +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, F. Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: create a quartus project with default settings for device, +## unused pins, ... +## expects project name as command line parameter +## e.g. +## quartus_sh -t create_quartus_project_settings.tcl -projectname de1_mux2to1 +## -family "Cyclone II" -device EP2C20F484C7 +## ---------------------------------------------------------------------------- +## Revisions : see end of file +## ---------------------------------------------------------------------------- + +package require cmdline +# Load Quartus II Tcl Project package +package require ::quartus::project + +# ---------------------------------------------------------------------------- +# Declare command line parameters +# ---------------------------------------------------------------------------- +set parameters { + {projectname.arg "" "Project Name"} + {family.arg "" "FPGA Family"} + {device.arg "" "FPGA Device"} +} +array set arg [::cmdline::getoptions argv $parameters] + +# ---------------------------------------------------------------------------- +# Verify required paramters +# ---------------------------------------------------------------------------- +set requiredParameters {projectname family device} +foreach parameter $requiredParameters { + if {$arg($parameter) == ""} { + puts stderr "Missing required parameter: -$parameter" + exit 1 + } +} + + + # ---------------------------------------------------------------------------- + # Create project + # ---------------------------------------------------------------------------- + project_new $arg(projectname) -overwrite + + # ---------------------------------------------------------------------------- + # Assign family, device, and top-level file + # ---------------------------------------------------------------------------- + set_global_assignment -name FAMILY $arg(family) + set_global_assignment -name DEVICE $arg(device) + + # ---------------------------------------------------------------------------- + # Default settings + # ---------------------------------------------------------------------------- + set_global_assignment -name USE_CONFIGURATION_DEVICE ON + set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" + set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 + + # ---------------------------------------------------------------------------- + # Design files + # ---------------------------------------------------------------------------- + #set_global_assignment -name VHDL_FILE ../src/e_cntdnmodm.vhd + #set_global_assignment -name VHDL_FILE ../src/a_cntdnmodm_rtl.vhd + source quartus_vhdl_source_files.tcl + + # ---------------------------------------------------------------------------- + # Pin Assignments + # ---------------------------------------------------------------------------- + # set_location_assignment PIN_L1 -to CLOCK_50 + source $arg(projectname)_pins.tcl + + # ---------------------------------------------------------------------------- + # Close project + # ---------------------------------------------------------------------------- + project_close + + +## ---------------------------------------------------------------------------- +## Revisions: +## ---------- +## $Id:$ +## ---------------------------------------------------------------------------- diff --git a/scripts/de1_pin_assignments_minimumio.tcl b/scripts/de1_pin_assignments_minimumio.tcl new file mode 100644 index 0000000..d9d3470 --- /dev/null +++ b/scripts/de1_pin_assignments_minimumio.tcl @@ -0,0 +1,282 @@ +set_location_assignment PIN_D12 -to CLOCK_27[0] +set_location_assignment PIN_E12 -to CLOCK_27[1] +set_location_assignment PIN_B12 -to CLOCK_24[0] +set_location_assignment PIN_A12 -to CLOCK_24[1] +set_location_assignment PIN_L1 -to CLOCK_50 +set_location_assignment PIN_M21 -to EXT_CLOCK +set_location_assignment PIN_R22 -to KEY[0] +set_location_assignment PIN_R21 -to KEY[1] +set_location_assignment PIN_T22 -to KEY[2] +set_location_assignment PIN_T21 -to KEY[3] +set_location_assignment PIN_L22 -to SW[0] +set_location_assignment PIN_L21 -to SW[1] +set_location_assignment PIN_M22 -to SW[2] +set_location_assignment PIN_V12 -to SW[3] +set_location_assignment PIN_W12 -to SW[4] +set_location_assignment PIN_U12 -to SW[5] +set_location_assignment PIN_U11 -to SW[6] +set_location_assignment PIN_M2 -to SW[7] +set_location_assignment PIN_M1 -to SW[8] +set_location_assignment PIN_L2 -to SW[9] +set_location_assignment PIN_R20 -to LEDR[0] +set_location_assignment PIN_R19 -to LEDR[1] +set_location_assignment PIN_U19 -to LEDR[2] +set_location_assignment PIN_Y19 -to LEDR[3] +set_location_assignment PIN_T18 -to LEDR[4] +set_location_assignment PIN_V19 -to LEDR[5] +set_location_assignment PIN_Y18 -to LEDR[6] +set_location_assignment PIN_U18 -to LEDR[7] +set_location_assignment PIN_R18 -to LEDR[8] +set_location_assignment PIN_R17 -to LEDR[9] +set_location_assignment PIN_U22 -to LEDG[0] +set_location_assignment PIN_U21 -to LEDG[1] +set_location_assignment PIN_V22 -to LEDG[2] +set_location_assignment PIN_V21 -to LEDG[3] +set_location_assignment PIN_W22 -to LEDG[4] +set_location_assignment PIN_W21 -to LEDG[5] +set_location_assignment PIN_Y22 -to LEDG[6] +set_location_assignment PIN_Y21 -to LEDG[7] +set_location_assignment PIN_J2 -to HEX0[0] +set_location_assignment PIN_J1 -to HEX0[1] +set_location_assignment PIN_H2 -to HEX0[2] +set_location_assignment PIN_H1 -to HEX0[3] +set_location_assignment PIN_F2 -to HEX0[4] +set_location_assignment PIN_F1 -to HEX0[5] +set_location_assignment PIN_E2 -to HEX0[6] +set_location_assignment PIN_E1 -to HEX1[0] +set_location_assignment PIN_H6 -to HEX1[1] +set_location_assignment PIN_H5 -to HEX1[2] +set_location_assignment PIN_H4 -to HEX1[3] +set_location_assignment PIN_G3 -to HEX1[4] +set_location_assignment PIN_D2 -to HEX1[5] +set_location_assignment PIN_D1 -to HEX1[6] +set_location_assignment PIN_G5 -to HEX2[0] +set_location_assignment PIN_G6 -to HEX2[1] +set_location_assignment PIN_C2 -to HEX2[2] +set_location_assignment PIN_C1 -to HEX2[3] +set_location_assignment PIN_E3 -to HEX2[4] +set_location_assignment PIN_E4 -to HEX2[5] +set_location_assignment PIN_D3 -to HEX2[6] +set_location_assignment PIN_F4 -to HEX3[0] +set_location_assignment PIN_D5 -to HEX3[1] +set_location_assignment PIN_D6 -to HEX3[2] +set_location_assignment PIN_J4 -to HEX3[3] +set_location_assignment PIN_L8 -to HEX3[4] +set_location_assignment PIN_F3 -to HEX3[5] +set_location_assignment PIN_D4 -to HEX3[6] +set_location_assignment PIN_A13 -to GPI_0[0] +set_location_assignment PIN_B13 -to GPI_0[1] +set_location_assignment PIN_A14 -to GPI_0[2] +set_location_assignment PIN_B14 -to GPI_0[3] +set_location_assignment PIN_A15 -to GPI_0[4] +set_location_assignment PIN_B15 -to GPI_0[5] +set_location_assignment PIN_A16 -to GPI_0[6] +set_location_assignment PIN_B16 -to GPI_0[7] +set_location_assignment PIN_A17 -to GPI_0[8] +set_location_assignment PIN_B17 -to GPI_0[9] +set_location_assignment PIN_A18 -to GPI_0[10] +set_location_assignment PIN_B18 -to GPI_0[11] +set_location_assignment PIN_A19 -to GPI_0[12] +set_location_assignment PIN_B19 -to GPI_0[13] +set_location_assignment PIN_A20 -to GPI_0[14] +set_location_assignment PIN_B20 -to GPI_0[15] +set_location_assignment PIN_C21 -to GPI_0[16] +set_location_assignment PIN_C22 -to GPI_0[17] +set_location_assignment PIN_D21 -to GPI_0[18] +set_location_assignment PIN_D22 -to GPI_0[19] +set_location_assignment PIN_E21 -to GPI_0[20] +set_location_assignment PIN_E22 -to GPI_0[21] +set_location_assignment PIN_F21 -to GPI_0[22] +set_location_assignment PIN_F22 -to GPI_0[23] +set_location_assignment PIN_G21 -to GPI_0[24] +set_location_assignment PIN_G22 -to GPI_0[25] +set_location_assignment PIN_J21 -to GPI_0[26] +set_location_assignment PIN_J22 -to GPI_0[27] +set_location_assignment PIN_K21 -to GPI_0[28] +set_location_assignment PIN_K22 -to GPI_0[29] +set_location_assignment PIN_J19 -to GPI_0[30] +set_location_assignment PIN_J20 -to GPI_0[31] +set_location_assignment PIN_J18 -to GPI_0[32] +set_location_assignment PIN_K20 -to GPI_0[33] +set_location_assignment PIN_L19 -to GPI_0[34] +set_location_assignment PIN_L18 -to GPI_0[35] +set_location_assignment PIN_H12 -to GPI_1[0] +set_location_assignment PIN_H13 -to GPI_1[1] +set_location_assignment PIN_H14 -to GPI_1[2] +set_location_assignment PIN_G15 -to GPI_1[3] +set_location_assignment PIN_E14 -to GPI_1[4] +set_location_assignment PIN_E15 -to GPI_1[5] +set_location_assignment PIN_F15 -to GPI_1[6] +set_location_assignment PIN_G16 -to GPI_1[7] +set_location_assignment PIN_F12 -to GPI_1[8] +set_location_assignment PIN_F13 -to GPI_1[9] +set_location_assignment PIN_C14 -to GPI_1[10] +set_location_assignment PIN_D14 -to GPI_1[11] +set_location_assignment PIN_D15 -to GPI_1[12] +set_location_assignment PIN_D16 -to GPI_1[13] +set_location_assignment PIN_C17 -to GPI_1[14] +set_location_assignment PIN_C18 -to GPI_1[15] +set_location_assignment PIN_C19 -to GPI_1[16] +set_location_assignment PIN_C20 -to GPI_1[17] +set_location_assignment PIN_D19 -to GPI_1[18] +set_location_assignment PIN_D20 -to GPI_1[19] +set_location_assignment PIN_E20 -to GPI_1[20] +set_location_assignment PIN_F20 -to GPI_1[21] +set_location_assignment PIN_E19 -to GPI_1[22] +set_location_assignment PIN_E18 -to GPI_1[23] +set_location_assignment PIN_G20 -to GPI_1[24] +set_location_assignment PIN_G18 -to GPI_1[25] +set_location_assignment PIN_G17 -to GPI_1[26] +set_location_assignment PIN_H17 -to GPI_1[27] +set_location_assignment PIN_J15 -to GPI_1[28] +set_location_assignment PIN_H18 -to GPI_1[29] +set_location_assignment PIN_N22 -to GPI_1[30] +set_location_assignment PIN_N21 -to GPI_1[31] +set_location_assignment PIN_P15 -to GPI_1[32] +set_location_assignment PIN_N15 -to GPI_1[33] +set_location_assignment PIN_P17 -to GPI_1[34] +set_location_assignment PIN_P18 -to GPI_1[35] +set_location_assignment PIN_A13 -to GPO_0[0] +set_location_assignment PIN_B13 -to GPO_0[1] +set_location_assignment PIN_A14 -to GPO_0[2] +set_location_assignment PIN_B14 -to GPO_0[3] +set_location_assignment PIN_A15 -to GPO_0[4] +set_location_assignment PIN_B15 -to GPO_0[5] +set_location_assignment PIN_A16 -to GPO_0[6] +set_location_assignment PIN_B16 -to GPO_0[7] +set_location_assignment PIN_A17 -to GPO_0[8] +set_location_assignment PIN_B17 -to GPO_0[9] +set_location_assignment PIN_A18 -to GPO_0[10] +set_location_assignment PIN_B18 -to GPO_0[11] +set_location_assignment PIN_A19 -to GPO_0[12] +set_location_assignment PIN_B19 -to GPO_0[13] +set_location_assignment PIN_A20 -to GPO_0[14] +set_location_assignment PIN_B20 -to GPO_0[15] +set_location_assignment PIN_C21 -to GPO_0[16] +set_location_assignment PIN_C22 -to GPO_0[17] +set_location_assignment PIN_D21 -to GPO_0[18] +set_location_assignment PIN_D22 -to GPO_0[19] +set_location_assignment PIN_E21 -to GPO_0[20] +set_location_assignment PIN_E22 -to GPO_0[21] +set_location_assignment PIN_F21 -to GPO_0[22] +set_location_assignment PIN_F22 -to GPO_0[23] +set_location_assignment PIN_G21 -to GPO_0[24] +set_location_assignment PIN_G22 -to GPO_0[25] +set_location_assignment PIN_J21 -to GPO_0[26] +set_location_assignment PIN_J22 -to GPO_0[27] +set_location_assignment PIN_K21 -to GPO_0[28] +set_location_assignment PIN_K22 -to GPO_0[29] +set_location_assignment PIN_J19 -to GPO_0[30] +set_location_assignment PIN_J20 -to GPO_0[31] +set_location_assignment PIN_J18 -to GPO_0[32] +set_location_assignment PIN_K20 -to GPO_0[33] +set_location_assignment PIN_L19 -to GPO_0[34] +set_location_assignment PIN_L18 -to GPO_0[35] +set_location_assignment PIN_H12 -to GPO_1[0] +set_location_assignment PIN_H13 -to GPO_1[1] +set_location_assignment PIN_H14 -to GPO_1[2] +set_location_assignment PIN_G15 -to GPO_1[3] +set_location_assignment PIN_E14 -to GPO_1[4] +set_location_assignment PIN_E15 -to GPO_1[5] +set_location_assignment PIN_F15 -to GPO_1[6] +set_location_assignment PIN_G16 -to GPO_1[7] +set_location_assignment PIN_F12 -to GPO_1[8] +set_location_assignment PIN_F13 -to GPO_1[9] +set_location_assignment PIN_C14 -to GPO_1[10] +set_location_assignment PIN_D14 -to GPO_1[11] +set_location_assignment PIN_D15 -to GPO_1[12] +set_location_assignment PIN_D16 -to GPO_1[13] +set_location_assignment PIN_C17 -to GPO_1[14] +set_location_assignment PIN_C18 -to GPO_1[15] +set_location_assignment PIN_C19 -to GPO_1[16] +set_location_assignment PIN_C20 -to GPO_1[17] +set_location_assignment PIN_D19 -to GPO_1[18] +set_location_assignment PIN_D20 -to GPO_1[19] +set_location_assignment PIN_E20 -to GPO_1[20] +set_location_assignment PIN_F20 -to GPO_1[21] +set_location_assignment PIN_E19 -to GPO_1[22] +set_location_assignment PIN_E18 -to GPO_1[23] +set_location_assignment PIN_G20 -to GPO_1[24] +set_location_assignment PIN_G18 -to GPO_1[25] +set_location_assignment PIN_G17 -to GPO_1[26] +set_location_assignment PIN_H17 -to GPO_1[27] +set_location_assignment PIN_J15 -to GPO_1[28] +set_location_assignment PIN_H18 -to GPO_1[29] +set_location_assignment PIN_N22 -to GPO_1[30] +set_location_assignment PIN_N21 -to GPO_1[31] +set_location_assignment PIN_P15 -to GPO_1[32] +set_location_assignment PIN_N15 -to GPO_1[33] +set_location_assignment PIN_P17 -to GPO_1[34] +set_location_assignment PIN_P18 -to GPO_1[35] +set_location_assignment PIN_A13 -to GPIO_0[0] +set_location_assignment PIN_B13 -to GPIO_0[1] +set_location_assignment PIN_A14 -to GPIO_0[2] +set_location_assignment PIN_B14 -to GPIO_0[3] +set_location_assignment PIN_A15 -to GPIO_0[4] +set_location_assignment PIN_B15 -to GPIO_0[5] +set_location_assignment PIN_A16 -to GPIO_0[6] +set_location_assignment PIN_B16 -to GPIO_0[7] +set_location_assignment PIN_A17 -to GPIO_0[8] +set_location_assignment PIN_B17 -to GPIO_0[9] +set_location_assignment PIN_A18 -to GPIO_0[10] +set_location_assignment PIN_B18 -to GPIO_0[11] +set_location_assignment PIN_A19 -to GPIO_0[12] +set_location_assignment PIN_B19 -to GPIO_0[13] +set_location_assignment PIN_A20 -to GPIO_0[14] +set_location_assignment PIN_B20 -to GPIO_0[15] +set_location_assignment PIN_C21 -to GPIO_0[16] +set_location_assignment PIN_C22 -to GPIO_0[17] +set_location_assignment PIN_D21 -to GPIO_0[18] +set_location_assignment PIN_D22 -to GPIO_0[19] +set_location_assignment PIN_E21 -to GPIO_0[20] +set_location_assignment PIN_E22 -to GPIO_0[21] +set_location_assignment PIN_F21 -to GPIO_0[22] +set_location_assignment PIN_F22 -to GPIO_0[23] +set_location_assignment PIN_G21 -to GPIO_0[24] +set_location_assignment PIN_G22 -to GPIO_0[25] +set_location_assignment PIN_J21 -to GPIO_0[26] +set_location_assignment PIN_J22 -to GPIO_0[27] +set_location_assignment PIN_K21 -to GPIO_0[28] +set_location_assignment PIN_K22 -to GPIO_0[29] +set_location_assignment PIN_J19 -to GPIO_0[30] +set_location_assignment PIN_J20 -to GPIO_0[31] +set_location_assignment PIN_J18 -to GPIO_0[32] +set_location_assignment PIN_K20 -to GPIO_0[33] +set_location_assignment PIN_L19 -to GPIO_0[34] +set_location_assignment PIN_L18 -to GPIO_0[35] +set_location_assignment PIN_H12 -to GPIO_1[0] +set_location_assignment PIN_H13 -to GPIO_1[1] +set_location_assignment PIN_H14 -to GPIO_1[2] +set_location_assignment PIN_G15 -to GPIO_1[3] +set_location_assignment PIN_E14 -to GPIO_1[4] +set_location_assignment PIN_E15 -to GPIO_1[5] +set_location_assignment PIN_F15 -to GPIO_1[6] +set_location_assignment PIN_G16 -to GPIO_1[7] +set_location_assignment PIN_F12 -to GPIO_1[8] +set_location_assignment PIN_F13 -to GPIO_1[9] +set_location_assignment PIN_C14 -to GPIO_1[10] +set_location_assignment PIN_D14 -to GPIO_1[11] +set_location_assignment PIN_D15 -to GPIO_1[12] +set_location_assignment PIN_D16 -to GPIO_1[13] +set_location_assignment PIN_C17 -to GPIO_1[14] +set_location_assignment PIN_C18 -to GPIO_1[15] +set_location_assignment PIN_C19 -to GPIO_1[16] +set_location_assignment PIN_C20 -to GPIO_1[17] +set_location_assignment PIN_D19 -to GPIO_1[18] +set_location_assignment PIN_D20 -to GPIO_1[19] +set_location_assignment PIN_E20 -to GPIO_1[20] +set_location_assignment PIN_F20 -to GPIO_1[21] +set_location_assignment PIN_E19 -to GPIO_1[22] +set_location_assignment PIN_E18 -to GPIO_1[23] +set_location_assignment PIN_G20 -to GPIO_1[24] +set_location_assignment PIN_G18 -to GPIO_1[25] +set_location_assignment PIN_G17 -to GPIO_1[26] +set_location_assignment PIN_H17 -to GPIO_1[27] +set_location_assignment PIN_J15 -to GPIO_1[28] +set_location_assignment PIN_H18 -to GPIO_1[29] +set_location_assignment PIN_N22 -to GPIO_1[30] +set_location_assignment PIN_N21 -to GPIO_1[31] +set_location_assignment PIN_P15 -to GPIO_1[32] +set_location_assignment PIN_N15 -to GPIO_1[33] +set_location_assignment PIN_P17 -to GPIO_1[34] +set_location_assignment PIN_P18 -to GPIO_1[35] \ No newline at end of file diff --git a/scripts/modelsim.ini b/scripts/modelsim.ini new file mode 100644 index 0000000..d3412fe --- /dev/null +++ b/scripts/modelsim.ini @@ -0,0 +1,351 @@ +;; ---------------------------------------------------------------------------- +;; Script : modelsim.ini +;; ---------------------------------------------------------------------------- +;; Author : Johann Faerber +;; Company : University of Applied Sciences Augsburg +;; ---------------------------------------------------------------------------- +;; Description: original version modified +;; - deleted all VHDL and Verilog device libraries +;; - modified compiler standard to VHDL93 = 2008 +;; ---------------------------------------------------------------------------- +;; Revisions : see end of file +;; ---------------------------------------------------------------------------- + +; Copyright 1991-2009 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +std = $MODEL_TECH/../std +ieee = $MODEL_TECH/../ieee +verilog = $MODEL_TECH/../verilog +vital2000 = $MODEL_TECH/../vital2000 +std_developerskit = $MODEL_TECH/../std_developerskit +synopsys = $MODEL_TECH/../synopsys +modelsim_lib = $MODEL_TECH/../modelsim_lib +sv_std = $MODEL_TECH/../sv_std + +; Altera Primitive libraries +; +; VHDL Section +; +altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf +altera = $MODEL_TECH/../altera/vhdl/altera +altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim +lpm = $MODEL_TECH/../altera/vhdl/220model +220model = $MODEL_TECH/../altera/vhdl/220model + +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Default or value of 3 or 2008 for VHDL-2008. +VHDL93 = 2008 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +[vlog] + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Turn on incremental compilation of modules. Default is off. +; Incremental = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +[vsim] +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ns + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 100 + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Directive to license manager: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; nomgc Do not look for Mentor Graphics Licenses +; nomti Do not look for Model Technology Licenses +; noqueue Do not wait in the license queue when a license isn't available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license +; License = plus + +; Stop the simulator after a VHDL/Verilog assertion message +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Assertion Message Format +; %S - Severity Level +; %R - Report Message +; %T - Time of assertion +; %D - Delta +; %I - Instance or Region pathname (if available) +; %% - print '%' character +; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Assertion File - alternate file for storing VHDL/Verilog assertion messages +; AssertFile = assert.log + +; Default radix for all windows and commands... +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example, sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings from the std_logic_arith, std_logic_unsigned +; and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from the IEEE numeric_std and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Control the format of the (VHDL) FOR generate statement label +; for each iteration. Do not quote it. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate_label; the %d represents the generate parameter value +; at a particular generate iteration (this is the position number if +; the generate parameter is of an enumeration type). Embedded whitespace +; is allowed (but discouraged); leading and trailing whitespace is ignored. +; Application of the format must result in a unique scope name over all +; such names in the design so that name lookup can function properly. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave +; DefaultRestartOptions = -force + +; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs +; (> 500 megabyte memory footprint). Default is disabled. +; Specify number of megabytes to lock. +; LockedMemory = 1000 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Automatic SDF compilation +; Disables automatic compilation of SDF files in flows that support it. +; Default is on, uncomment to turn off. +; NoAutoSDFCompile = 1 + +[lmc] + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; Examples: +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of elaboration/runtime messages. +; The default is to have messages appear in the transcript and +; recorded in the wlf file (messages that are recorded in the +; wlf file can be viewed in the MsgViewer). The other settings +; are to send messages only to the transcript or only to the +; wlf file. The valid values are +; both {default} +; tran {transcript only} +; wlf {wlf file only} +; msgmode = both + +;; ---------------------------------------------------------------------------- +;; Revisions: +;; ---------- +;; $Id:$ +;; ---------------------------------------------------------------------------- diff --git a/scripts/quartus_project_flow.tcl b/scripts/quartus_project_flow.tcl new file mode 100644 index 0000000..2894685 --- /dev/null +++ b/scripts/quartus_project_flow.tcl @@ -0,0 +1,84 @@ +## ---------------------------------------------------------------------------- +## Script : quartus_project_flow.tcl +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, F. Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: executes process steps in a quartus project +## depending on the parameter process +## expects project name as command line parameter +## e.g. +## quartus_sh -t quartus_project_flow.tcl -projectname de1_mux2to1 +## -process compile +## ---------------------------------------------------------------------------- +## Revisions : see end of file +## ---------------------------------------------------------------------------- + +package require cmdline +# Load Quartus II Tcl Project package +package require ::quartus::project + +# ---------------------------------------------------------------------------- +# Declare command line parameters +# ---------------------------------------------------------------------------- +set parameters { + {projectname.arg "" "Project Name"} + {process.arg "" "Process Step"} +} +array set arg [::cmdline::getoptions argv $parameters] + +# ---------------------------------------------------------------------------- +# Verify required paramters +# ---------------------------------------------------------------------------- +set requiredParameters {projectname process} +foreach parameter $requiredParameters { + if {$arg($parameter) == ""} { + puts stderr "Missing required parameter: -$parameter" + exit 1 + } +} + +# ---------------------------------------------------------------------------- +# Check, if project exists +# ---------------------------------------------------------------------------- +if { ![project_exists $arg(projectname)] } { + post_message -type error "Project $arg(projectname) does not exist" + exit +} + # ---------------------------------------------------------------------------- + # Open project + # ---------------------------------------------------------------------------- + project_open $arg(projectname) + + # ---------------------------------------------------------------------------- + # Run specified design flow by parameter -process + # ---------------------------------------------------------------------------- + load_package flow + + if { $arg(process) == "compile" } { + execute_flow -compile + } elseif { $arg(process) == "analysis_and_elaboration" } { + execute_flow -analysis_and_elaboration + } else { + post_message -type error "Process step $arg(process) not allowed !" + exit + } + + # ---------------------------------------------------------------------------- + # Write Reports + # ---------------------------------------------------------------------------- + load_package report + load_report $arg(projectname) + write_report_panel -file flowsummary.log "Flow Summary" + + # ---------------------------------------------------------------------------- + # Close project + # ---------------------------------------------------------------------------- + project_close + + +## ---------------------------------------------------------------------------- +## Revisions: +## ---------- +## $Id:$ +## ---------------------------------------------------------------------------- -- cgit v1.2.3