From a04bbf15b0f51696894e37f3e566998108aefd74 Mon Sep 17 00:00:00 2001 From: Johann Faerber Date: Wed, 9 Mar 2022 09:48:43 +0100 Subject: added basic design directory structure --- sim/and2gate/makefile.sources | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 sim/and2gate/makefile.sources (limited to 'sim/and2gate/makefile.sources') diff --git a/sim/and2gate/makefile.sources b/sim/and2gate/makefile.sources new file mode 100644 index 0000000..cac390c --- /dev/null +++ b/sim/and2gate/makefile.sources @@ -0,0 +1,17 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/and2gate_equation.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- -- cgit v1.2.3