From df418208aa0570a99f6ab6657d54ee65d6162168 Mon Sep 17 00:00:00 2001
From: Friedrich Beckmann <friedrich.beckmann@hs-augsburg.de>
Date: Wed, 15 Mar 2023 22:30:08 +0100
Subject: added de1_sine sinewave generator for ADC/DAC board

I added a sinewave generator based on DDS in VHDL to
generate a sinewave with the ADC/DAC board. This can
be used to demonstrate the Aliasing Lowpass filter.
---
 sim/de1_sine/makefile         | 8 ++++++++
 sim/de1_sine/makefile.sources | 4 ++++
 2 files changed, 12 insertions(+)
 create mode 100644 sim/de1_sine/makefile
 create mode 100644 sim/de1_sine/makefile.sources

(limited to 'sim/de1_sine')

diff --git a/sim/de1_sine/makefile b/sim/de1_sine/makefile
new file mode 100644
index 0000000..e662da8
--- /dev/null
+++ b/sim/de1_sine/makefile
@@ -0,0 +1,8 @@
+PROJECT = de1_sine
+
+include ./makefile.sources
+
+SOURCE_FILES = $(SYN_SOURCE_FILES) \
+../../src/t_$(PROJECT).vhd
+
+include ../makefile
diff --git a/sim/de1_sine/makefile.sources b/sim/de1_sine/makefile.sources
new file mode 100644
index 0000000..5117d72
--- /dev/null
+++ b/sim/de1_sine/makefile.sources
@@ -0,0 +1,4 @@
+SYN_SOURCE_FILES = \
+../../src/de1_sine.vhd \
+../../src/sine_rtl.vhd 
+
-- 
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