From a04bbf15b0f51696894e37f3e566998108aefd74 Mon Sep 17 00:00:00 2001 From: Johann Faerber Date: Wed, 9 Mar 2022 09:48:43 +0100 Subject: added basic design directory structure --- sim/falling_edge_detector/makefile_structure.sources | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 sim/falling_edge_detector/makefile_structure.sources (limited to 'sim/falling_edge_detector/makefile_structure.sources') diff --git a/sim/falling_edge_detector/makefile_structure.sources b/sim/falling_edge_detector/makefile_structure.sources new file mode 100644 index 0000000..f644c26 --- /dev/null +++ b/sim/falling_edge_detector/makefile_structure.sources @@ -0,0 +1,19 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/d_ff_rtl.vhd \ +../../src/e_falling_edge_detector.vhd \ +../../src/a_falling_edge_detector_structure.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- -- cgit v1.2.3