From a04bbf15b0f51696894e37f3e566998108aefd74 Mon Sep 17 00:00:00 2001 From: Johann Faerber Date: Wed, 9 Mar 2022 09:48:43 +0100 Subject: added basic design directory structure --- sim/falling_edge_detector/makefile | 67 ++++++++++++++++++++++ sim/falling_edge_detector/makefile.sources | 18 ++++++ sim/falling_edge_detector/makefile_qfsm.sources | 17 ++++++ sim/falling_edge_detector/makefile_rtl.sources | 18 ++++++ .../makefile_structure.sources | 19 ++++++ 5 files changed, 139 insertions(+) create mode 100644 sim/falling_edge_detector/makefile create mode 100644 sim/falling_edge_detector/makefile.sources create mode 100644 sim/falling_edge_detector/makefile_qfsm.sources create mode 100644 sim/falling_edge_detector/makefile_rtl.sources create mode 100644 sim/falling_edge_detector/makefile_structure.sources (limited to 'sim/falling_edge_detector') diff --git a/sim/falling_edge_detector/makefile b/sim/falling_edge_detector/makefile new file mode 100644 index 0000000..48792e4 --- /dev/null +++ b/sim/falling_edge_detector/makefile @@ -0,0 +1,67 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with ModelSim, +## it is based on a design directory structure described in +## ../makefile +## ---------------------------------------------------------------------------- + +################################################################### +# Project Configuration: +# +# assign variable PROJECT with the top level project name +# +# Prerequisite: +# - mandatory design directory structure (see end of file) +# - assumes file name of testbench t_$(PROJECT).vhd +################################################################### + +PROJECT = falling_edge_detector + +include ./makefile.sources + +# Add here the testbench file +SOURCE_FILES = $(SYN_SOURCE_FILES) \ +../../src/t_$(PROJECT).vhd + +include ../makefile + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## DigitaltechnikPraktikum +## | +## +---src +## | and2gate_equation.vhd +## | invgate_equation.vhd +## | mux2to1_structure.vhd +## | or2gate_equation.vhd +## | t_mux2to1.vhd +## | de1_mux2to1_structure.vhd +## | +## +---sim +## | | makefile +## | | +## | \---mux2to1 +## | makefile +## | makefile.sources +## | +## +---pnr +## | | makefile +## | | +## | \---de1_mux2to1 +## | de1_mux2to1_pins.tcl +## | makefile +## | +## \---scripts +## de1_pin_assignments_minimumio.csv +## de1_pin_assignments_minimumio.tcl +## modelsim.ini +## quartus_project_settings.tcl +## ---------------------------------------------------------------------------- + diff --git a/sim/falling_edge_detector/makefile.sources b/sim/falling_edge_detector/makefile.sources new file mode 100644 index 0000000..03b2cd7 --- /dev/null +++ b/sim/falling_edge_detector/makefile.sources @@ -0,0 +1,18 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/e_falling_edge_detector.vhd \ +../../src/a_falling_edge_detector_rtl.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/falling_edge_detector/makefile_qfsm.sources b/sim/falling_edge_detector/makefile_qfsm.sources new file mode 100644 index 0000000..5b3eeec --- /dev/null +++ b/sim/falling_edge_detector/makefile_qfsm.sources @@ -0,0 +1,17 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/falling_edge_detector_qfsm.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/falling_edge_detector/makefile_rtl.sources b/sim/falling_edge_detector/makefile_rtl.sources new file mode 100644 index 0000000..03b2cd7 --- /dev/null +++ b/sim/falling_edge_detector/makefile_rtl.sources @@ -0,0 +1,18 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/e_falling_edge_detector.vhd \ +../../src/a_falling_edge_detector_rtl.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- diff --git a/sim/falling_edge_detector/makefile_structure.sources b/sim/falling_edge_detector/makefile_structure.sources new file mode 100644 index 0000000..f644c26 --- /dev/null +++ b/sim/falling_edge_detector/makefile_structure.sources @@ -0,0 +1,19 @@ +## ---------------------------------------------------------------------------- +## Script : makefile.sources +## ---------------------------------------------------------------------------- +## Author : Johann Faerber +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES +## Attention !!! +## ------------- +## Do not forget a new line after the final source file ! +## ---------------------------------------------------------------------------- + +SYN_SOURCE_FILES = \ +../../src/d_ff_rtl.vhd \ +../../src/e_falling_edge_detector.vhd \ +../../src/a_falling_edge_detector_structure.vhd \ + +# do not delete this line +# ----------------------------------------------------------------------------- -- cgit v1.2.3