From a04bbf15b0f51696894e37f3e566998108aefd74 Mon Sep 17 00:00:00 2001
From: Johann Faerber <johann.faerber@hs-augsburg.de>
Date: Wed, 9 Mar 2022 09:48:43 +0100
Subject: added basic design directory structure

---
 src/and2gate_equation.vhd | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 src/and2gate_equation.vhd

(limited to 'src/and2gate_equation.vhd')

diff --git a/src/and2gate_equation.vhd b/src/and2gate_equation.vhd
new file mode 100644
index 0000000..9c7f0f2
--- /dev/null
+++ b/src/and2gate_equation.vhd
@@ -0,0 +1,35 @@
+-------------------------------------------------------------------------------
+-- Module     : and2gate
+-------------------------------------------------------------------------------
+-- Author     : Johann Faerber
+-- Company    : University of Applied Sciences Augsburg
+-------------------------------------------------------------------------------
+-- Description: 2-input AND Gate
+--              function modelled by logic equation
+-------------------------------------------------------------------------------
+-- Revisions  : see end of file
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY and2gate IS
+  PORT (a_i : IN  std_ulogic;           -- data input a
+        b_i : IN  std_ulogic;           -- data input b
+        y_o : OUT std_ulogic            -- data output y
+        );
+END and2gate;
+
+ARCHITECTURE equation OF and2gate IS
+
+BEGIN
+
+  y_o <= a_i AND b_i;
+
+END equation;
+
+-------------------------------------------------------------------------------
+-- Revisions:
+-- ----------
+-- $Id:$
+-------------------------------------------------------------------------------
+
-- 
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