From a04bbf15b0f51696894e37f3e566998108aefd74 Mon Sep 17 00:00:00 2001 From: Johann Faerber Date: Wed, 9 Mar 2022 09:48:43 +0100 Subject: added basic design directory structure --- src/cntupdn_rtl.vhd | 47 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 src/cntupdn_rtl.vhd (limited to 'src/cntupdn_rtl.vhd') diff --git a/src/cntupdn_rtl.vhd b/src/cntupdn_rtl.vhd new file mode 100644 index 0000000..5f022e3 --- /dev/null +++ b/src/cntupdn_rtl.vhd @@ -0,0 +1,47 @@ +------------------------------------------------------------------------------- +-- Module : cntupdn +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: Up/Down-Counter +-- including a low-active asynchronous reset input rst_ni +-- a high-active enable input en_pi +-- mode_i = 0 -> count down +-- mode_i = 1 -> count up +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY cntupdn IS + PORT (clk_i : IN std_ulogic; + rst_ni : IN std_ulogic; + en_pi : IN std_ulogic; + mode_i : IN std_ulogic; -- mode_i = 0 -> count down + -- mode_i = 1 -> count up + count_o : OUT std_ulogic_vector(3 DOWNTO 0) + ); +END cntupdn; + +ARCHITECTURE rtl OF cntupdn IS + + +BEGIN + + de_incrementer : + + state_register : + + counter_output : + +END rtl; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- + -- cgit v1.2.3