From f37b864e1b943984739931b0950c45c6f705c679 Mon Sep 17 00:00:00 2001
From: Johann Faerber <johann.faerber@hs-augsburg.de>
Date: Wed, 16 Mar 2022 12:18:05 +0100
Subject: added t_and2gate.vhd and de1_and2gate_structure.vhd

---
 src/de1_and2gate_structure.vhd | 50 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)
 create mode 100644 src/de1_and2gate_structure.vhd

(limited to 'src/de1_and2gate_structure.vhd')

diff --git a/src/de1_and2gate_structure.vhd b/src/de1_and2gate_structure.vhd
new file mode 100644
index 0000000..fcab62a
--- /dev/null
+++ b/src/de1_and2gate_structure.vhd
@@ -0,0 +1,50 @@
+-------------------------------------------------------------------------------
+-- Module     : de1_and2gate
+-------------------------------------------------------------------------------
+-- Author     : Johann Faerber
+-- Company    : University of Applied Sciences Augsburg
+-------------------------------------------------------------------------------
+-- Description: test the module and2gate on a DE1 prototype board
+--              connecting device under test (DUT) and2gate
+--              to input/output signals of the DE1 prototype board
+-------------------------------------------------------------------------------
+-- Revisions  : see end of file
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY de1_and2gate IS
+  PORT (
+    SW   : IN  std_ulogic_vector(1 DOWNTO 0);  -- Toggle Switch[2:0]
+    LEDR : OUT std_ulogic_vector(2 DOWNTO 0)   -- LED Red[2:0]  
+    );
+END de1_and2gate;
+
+ARCHITECTURE structure OF de1_and2gate IS
+
+  COMPONENT and2gate IS
+    PORT (
+      a_i : IN  std_ulogic;
+      b_i : IN  std_ulogic;
+      y_o : OUT std_ulogic);
+  END COMPONENT and2gate;
+
+BEGIN
+
+  -- assigning input signals to LEDs
+  LEDR(0) <= SW(0);
+  LEDR(1) <= SW(1);
+
+  -- connecting device under test with peripheral elements
+  DUT : and2gate
+    PORT MAP (
+      a_i => SW(0),
+      b_i => SW(1),
+      y_o => LEDR(2));
+
+END structure;
+-------------------------------------------------------------------------------
+-- Revisions:
+-- ----------
+-- $Id:$
+-------------------------------------------------------------------------------
-- 
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