From 941aeaad5be56c905b4f38f3d07b0a0cbc1bd07f Mon Sep 17 00:00:00 2001 From: Matthias Kamuf Date: Wed, 15 Jun 2022 17:31:01 +0200 Subject: Created stub for DDS test with ADDA-board using Simulink flow --- src/de1_matlab_dds_adda.vhd | 104 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) create mode 100644 src/de1_matlab_dds_adda.vhd (limited to 'src/de1_matlab_dds_adda.vhd') diff --git a/src/de1_matlab_dds_adda.vhd b/src/de1_matlab_dds_adda.vhd new file mode 100644 index 0000000..a6546f6 --- /dev/null +++ b/src/de1_matlab_dds_adda.vhd @@ -0,0 +1,104 @@ +------------------------------------------------------------------------------- +-- Module : de1_matlab_dds_adda +------------------------------------------------------------------------------- +-- Author : Matthias Kamuf +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: Top-level of module de1_matlab_dds_adda +-- +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY de1_matlab_dds_adda IS + PORT ( + CLOCK_50 : IN std_ulogic; + KEY0 : IN std_ulogic; + DAC_MODE : OUT std_ulogic; + DAC_WRT_A : OUT std_ulogic; + DAC_WRT_B : OUT std_ulogic; + DAC_CLK_A : OUT std_ulogic; + DAC_CLK_B : OUT std_ulogic; + DAC_DA : OUT std_ulogic_vector(13 DOWNTO 0); + DAC_DB : OUT std_ulogic_vector(13 DOWNTO 0); + POWER_ON : OUT std_ulogic; + ADC_CLK_A : OUT std_ulogic; + ADC_CLK_B : OUT std_ulogic; + ADC_OEB_A : OUT std_ulogic; + ADC_OEB_B : OUT std_ulogic; + LEDR : OUT std_ulogic); +END de1_matlab_dds_adda; + +ARCHITECTURE structure OF de1_matlab_dds_adda IS + + -- Matlab-generated toplevel + COMPONENT ml_dds_adda IS + PORT ( + clk : IN std_ulogic; + rst_n : IN std_ulogic; + valid_o : OUT std_ulogic; + sample_o : OUT std_ulogic_vector(13 DOWNTO 0)); + END COMPONENT ml_dds_adda; + + -- component ports + SIGNAL clk : std_ulogic; + SIGNAL rst_n : std_ulogic; + SIGNAL valid : std_ulogic; + SIGNAL sample : std_ulogic_vector(13 DOWNTO 0); + +BEGIN + + sinegen : ml_dds_adda + PORT MAP ( + clk_ => clk, + rst_n => rst_n, + valid_o => valid, + sample_o => sample); + + -- clock and reset signal + clk <= CLOCK_50; + rst_n <= KEY0; + + -- valid indicator + LEDR <= valid; + + -- DAC in dual-port mode + DAC_MODE <= '1'; + + DAC_WRT_A <= clk; + DAC_WRT_B <= clk; + DAC_CLK_A <= clk; + DAC_CLK_B <= clk; + + -- DAC on board has 00000000000000 as minimum value + -- and 11111111111111 as maximum value + -- therefore the conversion has to look like this + -- input signed value output DAC value + -- minimum 10000000000000 00000000000000 + -- zero 00000000000000 10000000000000 + -- maximum 01111111111111 11111111111111 + + -- assign to DAC channels + DAC_DA <= "10000000000000" WHEN rst_n = '0' ELSE (NOT(sample(13)) & sample(12 DOWNTO 0)) WHEN falling_edge(clk); + DAC_DB <= "10000000000000" WHEN rst_n = '0' ELSE "10000000000000" WHEN falling_edge(clk); + + -- ADC section all off! + ADC_CLK_A <= '0'; + ADC_CLK_B <= '0'; + ADC_OEB_A <= '0'; + ADC_OEB_B <= '0'; + + -- switch on DAC/ADC + POWER_ON <= '1'; + +END structure; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- + -- cgit v1.2.3