From df418208aa0570a99f6ab6657d54ee65d6162168 Mon Sep 17 00:00:00 2001 From: Friedrich Beckmann Date: Wed, 15 Mar 2023 22:30:08 +0100 Subject: added de1_sine sinewave generator for ADC/DAC board I added a sinewave generator based on DDS in VHDL to generate a sinewave with the ADC/DAC board. This can be used to demonstrate the Aliasing Lowpass filter. --- src/de1_sine.vhd | 99 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) create mode 100644 src/de1_sine.vhd (limited to 'src/de1_sine.vhd') diff --git a/src/de1_sine.vhd b/src/de1_sine.vhd new file mode 100644 index 0000000..d3073f2 --- /dev/null +++ b/src/de1_sine.vhd @@ -0,0 +1,99 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity de1_sine is + port ( + CLOCK_50 : in std_ulogic; + KEY0 : in std_ulogic; + SW : in std_ulogic_vector(9 downto 0); + DAC_MODE : out std_ulogic; + DAC_WRT_A : out std_ulogic; + DAC_WRT_B : out std_ulogic; + DAC_CLK_A : out std_ulogic; + DAC_CLK_B : out std_ulogic; + DAC_DA : out std_ulogic_vector(13 downto 0); + DAC_DB : out std_ulogic_vector(13 downto 0); + POWER_ON : out std_ulogic; + ADC_CLK_A : out std_ulogic; + ADC_CLK_B : out std_ulogic; + ADC_OEB_A : out std_ulogic; + ADC_OEB_B : out std_ulogic; + LEDR : out std_ulogic_vector(9 downto 0)); +end de1_sine; + +architecture rtl of de1_sine is + + component sine is + port ( + clk : in std_ulogic; + rst_n : in std_ulogic; + phase_inc_i : in std_ulogic_vector(9 downto 0); + phase_o : out std_ulogic_vector(9 downto 0); + sample_o : out std_ulogic_vector(13 downto 0)); + end component sine; + + -- component ports + signal clk : std_ulogic; + signal rst_n : std_ulogic; + signal phase_inc_reg : std_ulogic_vector(9 downto 0); + signal sample : std_ulogic_vector(13 downto 0); + signal daca_reg1, daca_reg2 : std_ulogic_vector(13 downto 0); + signal dacb_reg1, dacb_reg2 : std_ulogic_vector(13 downto 0); + signal phase : std_ulogic_vector(9 downto 0); + +begin + + phase_inc_reg <= "0000000000" when rst_n = '0' else SW when rising_edge(clk); + + sinegen : sine + port map ( + clk => clk, + rst_n => rst_n, + phase_inc_i => phase_inc_reg, + phase_o => phase, + sample_o => sample); + + -- clock and reset signal + clk <= CLOCK_50; + rst_n <= KEY0; + + LEDR <= SW; + + -- DAC in dual-port mode + DAC_MODE <= '1'; + DAC_WRT_A <= clk; + DAC_WRT_B <= clk; + DAC_CLK_A <= clk; + DAC_CLK_B <= clk; + + -- Register to sinegen outputs to relax timing + daca_reg1 <= sample when rising_edge(clk); + daca_reg2 <= daca_reg1 when rising_edge(clk); + dacb_reg1 <= phase & "0000" when rising_edge(clk); + dacb_reg2 <= dacb_reg1 when rising_edge(clk); + + -- DAC on board has 00000000000000 as minimum value + -- and 11111111111111 as maximum value + -- therefore the conversion has to look like this + -- input signed value output DAC value + -- minimum 10000000000000 00000000000000 + -- zero 00000000000000 10000000000000 + -- maximum 01111111111111 11111111111111 + + -- assign to DAC channels + DAC_DA <= "10000000000000" WHEN rst_n = '0' ELSE + (NOT(daca_reg2(13)) & daca_reg2(12 downto 0)) WHEN falling_edge(clk); + DAC_DB <= "10000000000000" when rst_n = '0' else + dacb_reg2 when falling_edge(clk); + + -- ADC section all off! + ADC_CLK_A <= '0'; + ADC_CLK_B <= '0'; + ADC_OEB_A <= '0'; + ADC_OEB_B <= '0'; + + -- switch on DAC/ADC + POWER_ON <= '1'; + +end architecture; -- cgit v1.2.3