From a04bbf15b0f51696894e37f3e566998108aefd74 Mon Sep 17 00:00:00 2001 From: Johann Faerber Date: Wed, 9 Mar 2022 09:48:43 +0100 Subject: added basic design directory structure --- src/de1_sta.vhd | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 src/de1_sta.vhd (limited to 'src/de1_sta.vhd') diff --git a/src/de1_sta.vhd b/src/de1_sta.vhd new file mode 100644 index 0000000..91a93aa --- /dev/null +++ b/src/de1_sta.vhd @@ -0,0 +1,32 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity de1_sta is + port ( + CLOCK_50 : in std_ulogic; + x_i : in unsigned(7 downto 0); + y_o : out unsigned(x_i'range) + ); +end de1_sta; + +architecture rtl of de1_sta is + +signal a,b,c,d : unsigned(x_i'range); +signal sum : unsigned(x_i'range); +signal clk : std_ulogic; + +begin + +clk <= CLOCK_50; + +sum <= a + b + c + d; + +y_o <= sum when rising_edge(clk); + +a <= x_i when rising_edge(clk); +b <= a when rising_edge(clk); +c <= b when rising_edge(clk); +d <= c when rising_edge(clk); + +end architecture; -- cgit v1.2.3