From a04bbf15b0f51696894e37f3e566998108aefd74 Mon Sep 17 00:00:00 2001 From: Johann Faerber Date: Wed, 9 Mar 2022 09:48:43 +0100 Subject: added basic design directory structure --- src/mux2to1_rtl.vhd | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 src/mux2to1_rtl.vhd (limited to 'src/mux2to1_rtl.vhd') diff --git a/src/mux2to1_rtl.vhd b/src/mux2to1_rtl.vhd new file mode 100644 index 0000000..c6447dd --- /dev/null +++ b/src/mux2to1_rtl.vhd @@ -0,0 +1,42 @@ +------------------------------------------------------------------------------- +-- Module : mux2to1 +------------------------------------------------------------------------------- +-- Author : Johann Faerber +-- Company : University of Applied Sciences Augsburg +------------------------------------------------------------------------------- +-- Description: 2-to-1 multiplexer +-- function modelled by a conditional signal assignment +-- sel = '1': a -> y +-- sel = '0': b -> y +------------------------------------------------------------------------------- +-- Revisions : see end of file +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; + +ENTITY mux2to1 IS + PORT (a_i : IN std_ulogic; -- data input a + b_i : IN std_ulogic; -- data input b + sel_i : IN std_ulogic; -- select which input is connected to y + -- sel = '1': a -> y + -- sel = '0': b -> y + y_o : OUT std_ulogic -- data output y + ); +END mux2to1; + +ARCHITECTURE rtl OF mux2to1 IS + +BEGIN + + y_o <= a_i WHEN sel_i = '1' ELSE + b_i WHEN sel_i = '0' ELSE + 'X'; + +END rtl; + +------------------------------------------------------------------------------- +-- Revisions: +-- ---------- +-- $Id:$ +------------------------------------------------------------------------------- + -- cgit v1.2.3