From a04bbf15b0f51696894e37f3e566998108aefd74 Mon Sep 17 00:00:00 2001
From: Johann Faerber <johann.faerber@hs-augsburg.de>
Date: Wed, 9 Mar 2022 09:48:43 +0100
Subject: added basic design directory structure

---
 src/mux2to1_structure_errors.vhd | 79 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 79 insertions(+)
 create mode 100644 src/mux2to1_structure_errors.vhd

(limited to 'src/mux2to1_structure_errors.vhd')

diff --git a/src/mux2to1_structure_errors.vhd b/src/mux2to1_structure_errors.vhd
new file mode 100644
index 0000000..0b33968
--- /dev/null
+++ b/src/mux2to1_structure_errors.vhd
@@ -0,0 +1,79 @@
+-------------------------------------------------------------------------------
+-- Module     : mux2to1
+-------------------------------------------------------------------------------
+-- Author     : Johann Faerber
+-- Company    : University of Applied Sciences Augsburg
+-------------------------------------------------------------------------------
+-- Description: 2-to-1 multiplexer
+--              function modelled as structure of basic logic gates
+-------------------------------------------------------------------------------
+-- Revisions  : see end of file
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY mux2to1 IS
+  PORT (a_i   : IN  std_ulogic;
+        b_i   : IN  std_ulogic;
+        sel_i : IN  std_ulogic;
+--        y_o   : OUT std_ulogic; -- kein ; nach letztem Signal
+        y_o   : OUT std_ulogic
+        );
+END mux21;
+
+
+ARCHITECTURE structure OF mux2to1 IS
+
+  COMPONENT invgate
+    PORT (
+      a_i : IN  std_ulogic;
+      y_o : OUT std_ulogic);
+  END COMPONENT;
+
+  COMPONENT or2gate
+    PORT (
+      a_i : IN  std_ulogic;
+      b_i : IN  std_ulogic;
+      y_o : std_ulogic);
+  END COMPONENT;
+
+  SIGNAL p1  : std_ulogic;
+  SIGNAL p2 : std_ulogic;
+  SIGNAL p3 : std_ulogic;
+  
+BEGIN
+
+  inv_gate_1 : invgate
+    PORT MAP (
+      a_i => sel_i,
+      y_o <= p2);
+
+
+  and2_gate_1 : and2gate
+    PORT MAP (
+      a_i => a_i,
+      b_i => p2
+      y_o => p0);
+
+  and2_gate_2 : and2gate
+    PORT MAP (
+      a_i => b_i,
+      b_i => sel_i,
+      y_o => p1);
+
+  or2_gate_1 : or2gate
+    PORT MAP (
+      a_i => p0,
+      b_i => p1,
+      y_o => p3);
+
+
+END struct
+
+
+-------------------------------------------------------------------------------
+-- Revisions:
+-- ----------
+-- $Id:$
+-------------------------------------------------------------------------------
+
-- 
cgit v1.2.3