From f37b864e1b943984739931b0950c45c6f705c679 Mon Sep 17 00:00:00 2001
From: Johann Faerber <johann.faerber@hs-augsburg.de>
Date: Wed, 16 Mar 2022 12:18:05 +0100
Subject: added t_and2gate.vhd and de1_and2gate_structure.vhd

---
 src/t_and2gate.vhd | 75 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 75 insertions(+)
 create mode 100644 src/t_and2gate.vhd

(limited to 'src/t_and2gate.vhd')

diff --git a/src/t_and2gate.vhd b/src/t_and2gate.vhd
new file mode 100644
index 0000000..e0cdec2
--- /dev/null
+++ b/src/t_and2gate.vhd
@@ -0,0 +1,75 @@
+-------------------------------------------------------------------------------
+-- Module     : t_and2gate
+-------------------------------------------------------------------------------
+-- Author     :   <haf@fh-augsburg.de>
+-- Company    : University of Applied Sciences Augsburg
+-- Copyright (c) 2011   <haf@fh-augsburg.de>
+-------------------------------------------------------------------------------
+-- Description: Testbench for design "and2gate"
+-------------------------------------------------------------------------------
+-- Revisions  : see end of file
+-------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-------------------------------------------------------------------------------
+
+ENTITY t_and2gate IS
+END t_and2gate;
+
+-------------------------------------------------------------------------------
+
+ARCHITECTURE tbench OF t_and2gate IS
+
+  COMPONENT and2gate IS
+    PORT (
+      a_i : IN  std_ulogic;
+      b_i : IN  std_ulogic;
+      y_o : OUT std_ulogic);
+  END COMPONENT and2gate;
+
+  -- definition of a clock period
+  CONSTANT period : time := 10 ns;
+
+  -- component ports
+  SIGNAL a_i : std_ulogic;
+  SIGNAL b_i : std_ulogic;
+  SIGNAL y_o : std_ulogic;
+
+BEGIN  -- tbench
+
+  -- component instantiation
+  MUV : and2gate
+    PORT MAP (
+      a_i => a_i,
+      b_i => b_i,
+      y_o => y_o);
+
+  stimuli_p : PROCESS
+
+  BEGIN
+    a_i <= '0';                         -- set a value to input a_i 
+    b_i <= '0';                         -- set a value to input b_i 
+    WAIT FOR period;                    -- values are assigned here
+
+    a_i <= '1';                         -- change value of a_i
+    WAIT FOR period;
+
+    a_i <= '0';                         -- change value of a_i
+    b_i <= '1';                         -- change value of b_i
+    WAIT FOR period;
+
+    a_i <= '1';                         -- change value of a_i
+    WAIT FOR period;
+
+    WAIT;
+  END PROCESS;
+
+END tbench;
+
+-------------------------------------------------------------------------------
+-- Revisions:
+-- ----------
+-- $Id:$
+-------------------------------------------------------------------------------
-- 
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