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-- Module     : de1_and2gate
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-- Author     : Johann Faerber
-- Company    : University of Applied Sciences Augsburg
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-- Description: test the module and2gate on a DE1 prototype board
--              connecting device under test (DUT) and2gate
--              to input/output signals of the DE1 prototype board
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-- Revisions  : see end of file
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LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY de1_and2gate IS
  PORT (
    SW   : IN  std_ulogic_vector(1 DOWNTO 0);  -- Toggle Switch[2:0]
    LEDR : OUT std_ulogic_vector(2 DOWNTO 0)   -- LED Red[2:0]  
    );
END de1_and2gate;

ARCHITECTURE structure OF de1_and2gate IS

  COMPONENT and2gate IS
    PORT (
      a_i : IN  std_ulogic;
      b_i : IN  std_ulogic;
      y_o : OUT std_ulogic);
  END COMPONENT and2gate;

BEGIN

  -- assigning input signals to LEDs
  LEDR(0) <= SW(0);
  LEDR(1) <= SW(1);

  -- connecting device under test with peripheral elements
  DUT : and2gate
    PORT MAP (
      a_i => SW(0),
      b_i => SW(1),
      y_o => LEDR(2));

END structure;
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-- Revisions:
-- ----------
-- $Id:$
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