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-- Module     : de1_fir
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-- Author     : Matthias Kamuf
-- Company    : University of Applied Sciences Augsburg
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-- Description: Top-level of module de1_fir
--              
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-- Revisions  : see end of file
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LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;

ENTITY de1_fir IS
  PORT (
    CLOCK_50  : IN  std_ulogic;
    KEY0      : IN  std_ulogic;
    DAC_MODE  : OUT std_ulogic;
    DAC_WRT_A : OUT std_ulogic;
    DAC_WRT_B : OUT std_ulogic;
    DAC_CLK_A : OUT std_ulogic;
    DAC_CLK_B : OUT std_ulogic;
    DAC_DA    : OUT std_ulogic_vector(13 DOWNTO 0);
    DAC_DB    : OUT std_ulogic_vector(13 DOWNTO 0);
    POWER_ON  : OUT std_ulogic;
    ADC_CLK_A : OUT std_ulogic;
    ADC_CLK_B : OUT std_ulogic;
    ADC_OEB_A : OUT std_ulogic;
    ADC_OEB_B : OUT std_ulogic;
    ADC_DA    : IN  std_ulogic_vector(13 DOWNTO 0);
    ADC_DB    : IN  std_ulogic_vector(13 DOWNTO 0);
    ADC_OTR_A : IN  std_ulogic;
    ADC_OTR_B : IN  std_ulogic;
    LEDR      : OUT std_ulogic_vector(9 DOWNTO 0));
END de1_fir;

ARCHITECTURE structure OF de1_fir IS

  COMPONENT fir IS
    PORT (
      clk_i    : IN  std_ulogic;
      rst_ni   : IN  std_ulogic;
      valid_i  : IN  std_ulogic;
      sample_i : IN  std_ulogic_vector(13 DOWNTO 0);
      valid_o  : OUT std_ulogic;
      sample_o : OUT std_ulogic_vector(13 DOWNTO 0));
  END COMPONENT fir;

  -- component ports
  SIGNAL clk                  : std_ulogic;
  SIGNAL rst_n                : std_ulogic;
  SIGNAL adc_a_dat, adc_b_dat : std_ulogic_vector(13 DOWNTO 0);

BEGIN

  filter : fir
    PORT MAP (
      clk_i    => clk,
      rst_ni   => rst_n,
      valid_i  => ,
      sample_i => ,
      valid_o  => ,
      sample_o => );

  -- clock and reset signal
  clk   <= CLOCK_50;
  rst_n <= KEY0;

  -- valid and overflow indicator
  LEDR <= valid & ADC_OTR_B & ADC_OTR_A & "0000000";

  -- DAC in dual port mode
  DAC_MODE <= '1';

  DAC_WRT_A <= clk;
  DAC_WRT_B <= clk;
  DAC_CLK_A <= clk;
  DAC_CLK_B <= clk;

  -- DAC on board has 00000000000000 as minimum value
  -- and              11111111111111 as maximum value
  -- therefore the conversion has to look like this
  --             input signed value              output DAC value
  -- minimum     10000000000000                  00000000000000
  -- zero        00000000000000                  10000000000000
  -- maximum     01111111111111                  11111111111111

  -- assign to DAC channels
  DAC_DA <= "10000000000000" WHEN rst_n = '0' ELSE adc_a_dat WHEN falling_edge(clk);
  DAC_DB <= "10000000000000" WHEN rst_n = '0' ELSE adc_b_dat WHEN falling_edge(clk);

  -- ADC section
  ADC_CLK_A <= clk;
  ADC_CLK_B <= clk;
  ADC_OEB_A <= '0';
  ADC_OEB_B <= '0';

  adc_a_dat <= (OTHERS => '0') WHEN rst_n = '0' ELSE ADC_DA WHEN rising_edge(clk);
  adc_b_dat <= (OTHERS => '0') WHEN rst_n = '0' ELSE ADC_DB WHEN rising_edge(clk);

  -- switch on DAC/ADC
  POWER_ON <= '1';

END structure;

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-- Revisions:
-- ----------
-- $Id:$
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