-------------------------------------------------------------------------------
-- Module     : fir
-------------------------------------------------------------------------------
-- Author     : Matthias Kamuf
-- Company    : University of Applied Sciences Augsburg
-------------------------------------------------------------------------------
-- Description: Top-level of module fir
--              
-------------------------------------------------------------------------------
-- Revisions  : see end of file
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;

ENTITY fir IS
  PORT (
    clk_i    : IN  std_ulogic;
    rst_ni   : IN  std_ulogic;
    valid_i  : IN  std_ulogic;
    sample_i : IN  std_ulogic_vector(13 DOWNTO 0);
    valid_o  : OUT std_ulogic;
    sample_o : OUT std_ulogic_vector(13 DOWNTO 0));
END fir;

ARCHITECTURE structure OF fir IS

  -- coefficient wordlength
  CONSTANT W_C : natural := 12;

  -- type definition for coefficients
  TYPE COEFFS_TYPE IS ARRAY (0 TO 7) OF integer;

  -- HERE SHALL BE THE CONTENT OF hqi.txt --->

  -- <---

  COMPONENT fir_mac IS
    GENERIC (
      gen_w_in : natural := 14;
      gen_w_c  : natural := 12);
    PORT (
      clk_i  : IN  std_ulogic;
      rst_ni : IN  std_ulogic;
      hl_i   : IN  std_ulogic_vector(gen_w_c-1 DOWNTO 0);  -- left coefficient
      hr_i   : IN  std_ulogic_vector(gen_w_c-1 DOWNTO 0);  -- right coefficient
      d_i    : IN  std_ulogic_vector(gen_w_in-1 DOWNTO 0);  -- data input first register
      d_o    : OUT std_ulogic_vector(gen_w_in-1 DOWNTO 0);  -- data output second register
      sum_o  : OUT std_ulogic_vector(gen_w_in+gen_w_c DOWNTO 0));  -- registered output sum_o
  END COMPONENT fir_mac;

  -- dynamic range of sum given coefficients above
  CONSTANT W_DYN : natural := 1;

BEGIN

  -- component instantiation  
  mac0 : fir_mac
    GENERIC MAP (
      gen_w_in => sample_i'length,
      gen_w_c  => W_C)
    PORT MAP (
      clk_i  => clk_i,
      rst_ni => rst_ni,
      hl_i   => ,
      hr_i   => ,
      d_i    => ,
      d_o    => , 
      sum_o  => );

  mac1 : fir_mac
    GENERIC MAP (
      gen_w_in => sample_i'length,
      gen_w_c  => W_C)
    PORT MAP (
      clk_i  => clk_i,
      rst_ni => rst_ni,
      hl_i   => ,
      hr_i   => ,
      d_i    => ,
      d_o    => , 
      sum_o  => );

  mac2 : fir_mac
    GENERIC MAP (
      gen_w_in => sample_i'length,
      gen_w_c  => W_C)
    PORT MAP (
      clk_i  => clk_i,
      rst_ni => rst_ni,
      hl_i   => ,
      hr_i   => ,
      d_i    => ,
      d_o    => , 
      sum_o  => );

  mac3 : fir_mac
    GENERIC MAP (
      gen_w_in => sample_i'length,
      gen_w_c  => W_C)
    PORT MAP (
      clk_i  => clk_i,
      rst_ni => rst_ni,
      hl_i   => ,
      hr_i   => ,
      d_i    => ,
      d_o    => , 
      sum_o  => );

  -- combining sums of individual fir_mac

  -- final sum

  -- truncated final sum (registered) at sample rate

  -- (registered and delayed due to pipeline stage in fir_mac) valid signal at sample rate

END structure;

-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------