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-- Module     : t_and2gate
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-- Author     :   <haf@fh-augsburg.de>
-- Company    : University of Applied Sciences Augsburg
-- Copyright (c) 2011   <haf@fh-augsburg.de>
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-- Description: Testbench for design "and2gate"
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-- Revisions  : see end of file
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

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ENTITY t_and2gate IS
END t_and2gate;

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ARCHITECTURE tbench OF t_and2gate IS

  COMPONENT and2gate IS
    PORT (
      a_i : IN  std_ulogic;
      b_i : IN  std_ulogic;
      y_o : OUT std_ulogic);
  END COMPONENT and2gate;

  -- definition of a clock period
  CONSTANT period : time := 10 ns;

  -- component ports
  SIGNAL a_i : std_ulogic;
  SIGNAL b_i : std_ulogic;
  SIGNAL y_o : std_ulogic;

BEGIN  -- tbench

  -- component instantiation
  MUV : and2gate
    PORT MAP (
      a_i => a_i,
      b_i => b_i,
      y_o => y_o);

  stimuli_p : PROCESS

  BEGIN
    a_i <= '0';                         -- set a value to input a_i 
    b_i <= '0';                         -- set a value to input b_i 
    WAIT FOR period;                    -- values are assigned here

    a_i <= '1';                         -- change value of a_i
    WAIT FOR period;

    a_i <= '0';                         -- change value of a_i
    b_i <= '1';                         -- change value of b_i
    WAIT FOR period;

    a_i <= '1';                         -- change value of a_i
    WAIT FOR period;

    WAIT;
  END PROCESS;

END tbench;

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-- Revisions:
-- ----------
-- $Id:$
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