-------------------------------------------------------------------------------
-- Module     : t_fir_fileio
-------------------------------------------------------------------------------
-- Author     : Matthias Kamuf
-- Company    : University of Applied Sciences Augsburg
-------------------------------------------------------------------------------
-- Description: Testbench for module fir
--              
------------------------------------------------------------------------------
-- Revisions  : see end of file
------------------------------------------------------------------------------- 
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE STD.textio.ALL;

ENTITY t_fir IS

END t_fir;

ARCHITECTURE tbench OF t_fir IS

  COMPONENT fir IS
    PORT (
      clk_i    : IN  std_ulogic;
      rst_ni   : IN  std_ulogic;
      valid_i  : IN  std_ulogic;
      sample_i : IN  std_ulogic_vector(13 DOWNTO 0);
      valid_o  : OUT std_ulogic;
      sample_o : OUT std_ulogic_vector(13 DOWNTO 0));
  END COMPONENT fir;

  -- component ports
  SIGNAL clk        : std_ulogic;
  SIGNAL rst_n      : std_ulogic;
  SIGNAL valid_in   : std_ulogic;
  SIGNAL sample_in  : std_ulogic_vector(13 DOWNTO 0);
  SIGNAL valid_out  : std_ulogic;
  SIGNAL sample_out : std_ulogic_vector(13 DOWNTO 0);

  -- definition of a clock period
  CONSTANT period : time    := 20 ns;
  -- switch for clock generator
  SIGNAL clken_p  : boolean := true;

BEGIN

  -- component instantiation
  DUT : fir
    PORT MAP (
      clk_i    => clk,
      rst_ni   => rst_n,
      valid_i  => valid_in,
      sample_i => sample_in,
      valid_o  => valid_out,
      sample_o => sample_out);

  -- clock generation
  clock_proc : PROCESS
  BEGIN
    WHILE clken_p LOOP
      clk <= '0'; WAIT FOR period/2;
      clk <= '1'; WAIT FOR period/2;
    END LOOP;
    WAIT;
  END PROCESS;

  reset : rst_n <= '0', '1' AFTER period;

  stimuli_observer : PROCESS
    VARIABLE Li      : line;            -- pointer to file input buffer
    VARIABLE Vi      : integer;
    FILE stimulifile : text OPEN read_mode IS "stimuli/fir_stimuli.dat";

    VARIABLE Lo     : line;             -- pointer to file output buffer
    VARIABLE Vo     : integer;
    FILE resultfile : text OPEN write_mode IS "log/fir_result.dat";

  BEGIN

    valid_in  <= '1';
    sample_in <= (OTHERS => '0');

    WAIT UNTIL rst_n = '1';             -- wait for reset

    WHILE (NOT endfile(stimulifile)) LOOP
      IF valid_in = '1' THEN
        readline(stimulifile, Li);
        read(Li, Vi);
        sample_in <= std_ulogic_vector(to_signed(Vi, sample_in'length));
      END IF;
      IF valid_out = '1' THEN
        Vo := to_integer(signed(sample_out));
        write(Lo, Vo);
        writeline(resultfile, Lo);
      END IF;
      WAIT UNTIL clk = '1';
    END LOOP;

    clken_p <= false;                   -- switch off clock generator

    WAIT;
  END PROCESS;
END tbench;


-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------