SoC Lab
This lab uses SpinalHDL for the System-on-Chip course. The build system is based on mill.
Install dependencies
You need to install quartus and the spinalhdl environment. I assume you have the virtual cae environment with user caeuser such that you can become root via sudo.
sudo apt install ansible
git clone https://github.com/fredowski/vcae.git
cd vcae/ansible
ansible-playbook quartus-package.yaml
ansible-playbook spinalhdl.yaml
How to use this
The getting started module is "top_simple". The Scala source code is in "top_simple/src/top_simple.scala". The module directly uses the toplevel FPGA pins, i.e. no module hierachy.
Generate VHDL from Scala
mill top_simple.generateVhdl
This generates the VHDL file from top_simple.scala. As the VHDL file is generated, mill stores it in "out/top_simple/generateVhdl.dest/top_simple.vhd".
Generate a Quartus project file and open Quartus GUI
The Quartus project file "top_simple.qpf" contains the project definitions for synthesis like the vhdl source file, pin definitions, FPGA device and some other settings.
mill top_simple.quartusgui
This will
- Generate the VHDL file from the scala file
- Build a Quartus Project File (top_simple.qpf)
- Open the Quartus GUI with that project file
The quartus project directory is generated and located at "out/top_simple/qproject.dest" and contains the "top_simple.qpf" file.
Run the Quartus synthesis and create the .sof file
The .sof file is the "SRAM-object file" which contains the FPGA configuration for the Intel/Altera FPGA. That will then be downloaded to the FPGA with the USB-Blaster programmer.
mill top_simple.synthesis
This will take the following files
- Generated VHDL file
- Generated Quartus Project file "top_simple.qpf"
- SDC file in "top_simple/pnr/top_simple.sdc"
- Pin Configuration file in "top_simple/pnr/top_simple_pins.tcl"
and produce the top_simple.sof file in "out/top_simple/qproject.dest"
Program the FPGA with USB-Blaster
mill top_simple.prog
This will take the .sof file and download it to the FPGA. You need to attach the USB cable to the FPGA board for this to work. Make sure that the usb device is visible inside your virtual machine if you run this in a virtual machine.