diff options
| -rw-r--r-- | build.mill | 1 | ||||
| -rw-r--r-- | top_count/pnr/top_count.sdc | 1 | ||||
| -rw-r--r-- | top_count/pnr/top_count_pins.tcl | 47 | ||||
| -rw-r--r-- | top_count/src/Config.scala | 17 | ||||
| -rw-r--r-- | top_count/src/counter.scala | 19 | ||||
| -rw-r--r-- | top_count/src/top_count.scala | 47 |
6 files changed, 132 insertions, 0 deletions
@@ -70,3 +70,4 @@ trait SpinalModule extends ScalaModule { } object top_simple extends SpinalModule +object top_count extends SpinalModule diff --git a/top_count/pnr/top_count.sdc b/top_count/pnr/top_count.sdc new file mode 100644 index 0000000..5ac173d --- /dev/null +++ b/top_count/pnr/top_count.sdc @@ -0,0 +1 @@ +create_clock -period 20.000 -name CLOCK_50 CLOCK_50
\ No newline at end of file diff --git a/top_count/pnr/top_count_pins.tcl b/top_count/pnr/top_count_pins.tcl new file mode 100644 index 0000000..84f817e --- /dev/null +++ b/top_count/pnr/top_count_pins.tcl @@ -0,0 +1,47 @@ +# assign pin locations to a quartus project + +set_location_assignment PIN_L22 -to SW[0] +set_location_assignment PIN_L21 -to SW[1] +set_location_assignment PIN_M22 -to SW[2] +set_location_assignment PIN_V12 -to SW[3] +set_location_assignment PIN_W12 -to SW[4] +set_location_assignment PIN_U12 -to SW[5] +set_location_assignment PIN_U11 -to SW[6] +set_location_assignment PIN_M2 -to SW[7] +set_location_assignment PIN_M1 -to SW[8] +set_location_assignment PIN_L2 -to SW[9] +set_location_assignment PIN_R20 -to LEDR[0] +set_location_assignment PIN_R19 -to LEDR[1] +set_location_assignment PIN_U19 -to LEDR[2] +set_location_assignment PIN_Y19 -to LEDR[3] +set_location_assignment PIN_T18 -to LEDR[4] +set_location_assignment PIN_V19 -to LEDR[5] +set_location_assignment PIN_Y18 -to LEDR[6] +set_location_assignment PIN_U18 -to LEDR[7] +set_location_assignment PIN_R18 -to LEDR[8] +set_location_assignment PIN_R17 -to LEDR[9] +set_location_assignment PIN_R22 -to KEY[0] +set_location_assignment PIN_R21 -to KEY[1] +set_location_assignment PIN_T22 -to KEY[2] +set_location_assignment PIN_T21 -to KEY[3] +set_location_assignment PIN_L1 -to CLOCK_50 +set_location_assignment PIN_U22 -to LEDG[0] +set_location_assignment PIN_U21 -to LEDG[1] +set_location_assignment PIN_V22 -to LEDG[2] +set_location_assignment PIN_V21 -to LEDG[3] +# This is expansion port 1 GPI_1 from scripts/de1_pin_assignments_minimumio.tcl +set_location_assignment PIN_H12 -to EXP[0] +set_location_assignment PIN_H13 -to EXP[1] +set_location_assignment PIN_H14 -to EXP[2] +set_location_assignment PIN_G15 -to EXP[3] +set_location_assignment PIN_E14 -to EXP[4] +set_location_assignment PIN_E15 -to EXP[5] +set_location_assignment PIN_F15 -to EXP[6] +set_location_assignment PIN_G16 -to EXP[7] +set_location_assignment PIN_J2 -to HEX0[0] +set_location_assignment PIN_J1 -to HEX0[1] +set_location_assignment PIN_H2 -to HEX0[2] +set_location_assignment PIN_H1 -to HEX0[3] +set_location_assignment PIN_F2 -to HEX0[4] +set_location_assignment PIN_F1 -to HEX0[5] +set_location_assignment PIN_E2 -to HEX0[6]
\ No newline at end of file diff --git a/top_count/src/Config.scala b/top_count/src/Config.scala new file mode 100644 index 0000000..c498303 --- /dev/null +++ b/top_count/src/Config.scala @@ -0,0 +1,17 @@ +package top_count + +import spinal.core._ +import spinal.core.sim._ + +object Config { + def spinal = SpinalConfig( + targetDirectory = sys.props.getOrElse("spinalTargetDir", "top_count/gen"), + defaultConfigForClockDomains = ClockDomainConfig( + resetKind = ASYNC, + resetActiveLevel = LOW + ), + onlyStdLogicVectorAtTopLevelIo = false + ) + + def sim = SimConfig.withGhdl.withConfig(spinal).withFstWave +} diff --git a/top_count/src/counter.scala b/top_count/src/counter.scala new file mode 100644 index 0000000..d8dc06e --- /dev/null +++ b/top_count/src/counter.scala @@ -0,0 +1,19 @@ +package top_count + +import spinal.core._ + +case class counter() extends Component { + val io = new Bundle { + val en_i = in Bool() + val cnt_o = out UInt(4 bits) + } + + // The counter register + val cnt = Reg(UInt(4 bits)) init 0 + + when (io.en_i) { + cnt := cnt + 1 + } + // Map the register content to the output + io.cnt_o := cnt +} diff --git a/top_count/src/top_count.scala b/top_count/src/top_count.scala new file mode 100644 index 0000000..ff2e54a --- /dev/null +++ b/top_count/src/top_count.scala @@ -0,0 +1,47 @@ +package top_count + +import spinal.core._ + +// Hardware definition +case class top_count() extends Component { + val io = new Bundle { + val SW = in Bits(10 bits) + val CLOCK_50 = in Bool() + val KEY = in Bits(4 bits) + val HEX0 = out Bits(7 bits) + val EXP = out Bits(8 bits) + val LEDR = out Bits(10 bits) + val LEDG = out Bits(4 bits) + } + // Remove io_ from the port names in generated vhdl code + noIoPrefix() + + val clk = new Bool() + val rst_n = new Bool() + clk := io.CLOCK_50 + rst_n := io.KEY(0) + val coreclockdomain = ClockDomain(clk, rst_n) + val coreArea = new ClockingArea(coreclockdomain) { + val counter = new counter() + counter.io.en_i := io.KEY(1) + + io.LEDR := io.SW + io.EXP(7 downto 4) := counter.io.cnt_o.asBits + io.EXP(3) := io.KEY(1) + io.EXP(2) := False + io.EXP(1) := rst_n + io.EXP(0) := clk + + io.LEDG := io.KEY + io.HEX0 := "0000000" + } +} + +// The following defines the vhdl and verilog code generation +object genverilog extends App { + Config.spinal.generateVerilog(top_count()) +} + +object genvhdl extends App { + Config.spinal.generateVhdl(top_count()) +} |