From 9d8b7ca4eaf712a3251f985fd1e93a0f0e568c16 Mon Sep 17 00:00:00 2001
From: Friedrich Beckmann <friedrich.beckmann@tha.de>
Date: Sat, 28 Mar 2026 07:59:30 +0100
Subject: init

---
 .gitignore                      |  4 ++++
 README.md                       |  3 +++
 build.mill                      | 17 +++++++++++++++++
 top_simple/src/Config.scala     | 16 ++++++++++++++++
 top_simple/src/top_simple.scala | 27 +++++++++++++++++++++++++++
 5 files changed, 67 insertions(+)
 create mode 100644 .gitignore
 create mode 100644 README.md
 create mode 100644 build.mill
 create mode 100644 top_simple/src/Config.scala
 create mode 100644 top_simple/src/top_simple.scala

diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..1251d7e
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,4 @@
+out/
+.metals/
+.vscode/
+gen/
\ No newline at end of file
diff --git a/README.md b/README.md
new file mode 100644
index 0000000..73a5267
--- /dev/null
+++ b/README.md
@@ -0,0 +1,3 @@
+# SoC Lab
+
+This lab uses [SpinalHDL](https://spinalhdl.github.io/SpinalDoc-RTD/master/index.html) for the System-on-Chip course.
\ No newline at end of file
diff --git a/build.mill b/build.mill
new file mode 100644
index 0000000..4b60b5f
--- /dev/null
+++ b/build.mill
@@ -0,0 +1,17 @@
+//| mvnDeps:
+//| - com.typesafe:config:1.4.3
+import mill._
+import mill.scalalib._
+
+object top_simple extends ScalaModule {
+  def scalaVersion = "2.13.14"
+
+  //override def sources = Task.Sources(moduleDir / os.up / "src")
+
+  override def mvnDeps = Seq(
+    mvn"com.github.spinalhdl::spinalhdl-core:1.12.3",
+    mvn"com.github.spinalhdl::spinalhdl-lib:1.12.3"
+  )
+
+  override def scalacPluginMvnDeps = Seq(mvn"com.github.spinalhdl::spinalhdl-idsl-plugin:1.12.3")
+}
diff --git a/top_simple/src/Config.scala b/top_simple/src/Config.scala
new file mode 100644
index 0000000..dbfe54b
--- /dev/null
+++ b/top_simple/src/Config.scala
@@ -0,0 +1,16 @@
+package top_simple
+
+import spinal.core._
+import spinal.core.sim._
+
+object Config {
+  def spinal = SpinalConfig(
+    targetDirectory = "top_simple/gen",
+    defaultConfigForClockDomains = ClockDomainConfig(
+      resetActiveLevel = HIGH
+    ),
+    onlyStdLogicVectorAtTopLevelIo = false
+  )
+
+  def sim = SimConfig.withGhdl.withConfig(spinal).withFstWave
+}
diff --git a/top_simple/src/top_simple.scala b/top_simple/src/top_simple.scala
new file mode 100644
index 0000000..ec43fe8
--- /dev/null
+++ b/top_simple/src/top_simple.scala
@@ -0,0 +1,27 @@
+package top_simple
+
+import spinal.core._
+
+// Hardware definition
+case class top_simple() extends Component {
+  val io = new Bundle {
+    val SW = in  Bits(10 bits)
+    val LEDR = out  Bits(10 bits)
+    val LEDG  = out Bits(8 bits)
+  }
+  // Remove io_ from the port names in generated vhdl code
+  noIoPrefix()
+
+  io.LEDR := io.SW
+  io.LEDG := "00000000"
+
+}
+
+// The following defines the vhdl and verilog code generation
+object verilog extends App {
+  Config.spinal.generateVerilog(top_simple())
+}
+
+object vhdl extends App {
+  Config.spinal.generateVhdl(top_simple())
+}
-- 
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