package top_count

import spinal.core._

// Hardware definition
case class top_count() extends Component {
  val io = new Bundle {
    val SW       = in  Bits(10 bits)
    val CLOCK_50 = in Bool()
    val KEY      = in Bits(4 bits)
    val HEX0     = out Bits(7 bits)
    val EXP      = out Bits(8 bits)
    val LEDR     = out  Bits(10 bits)
    val LEDG     = out Bits(4 bits)
  }
  // Remove io_ from the port names in generated vhdl code
  noIoPrefix()

  val clk = new Bool()
  val rst_n = new Bool()
  clk := io.CLOCK_50
  rst_n := io.KEY(0)
  val coreclockdomain = ClockDomain(clk, rst_n)
  val coreArea = new ClockingArea(coreclockdomain) {
    val counter = new counter()
    counter.io.en_i := io.KEY(1)
    
    io.LEDR := io.SW
    io.EXP(7 downto 4) := counter.io.cnt_o.asBits
    io.EXP(3) := io.KEY(1)
    io.EXP(2) := False
    io.EXP(1) := rst_n
    io.EXP(0) := clk

    io.LEDG := io.KEY
    io.HEX0 := "0000000"
  }
}

// The following defines the vhdl and verilog code generation
object genverilog extends App {
  Config.spinal.generateVerilog(top_count())
}

object genvhdl extends App {
  Config.spinal.generateVhdl(top_count())
}