Initial Commit

6 files changed, 1095 insertions, 0 deletions

diff --git a/scripts/create_quartus_project_settings.tcl b/scripts/create_quartus_project_settings.tcl
new file mode 100644
index 0000000..40c50ee
--- /dev/null
+++ b/scripts/create_quartus_project_settings.tcl
@@ -0,0 +1,77 @@
+## ----------------------------------------------------------------------------
+## Script     : create_quartus_project_settings.tcl
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber, F. Beckmann
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: create a quartus project with default settings for device, 
+##              unused pins, ...
+##              expects project name as command line parameter 
+##              It expects one file containing the vhdl source files and
+##              one file containing the pin constraints. 
+##              Start with
+##              quartus_sh -t create_quartus_project_settings.tcl -projectname de1_mux2to1
+
+package require cmdline
+# Load Quartus II Tcl Project package
+package require ::quartus::project
+
+# ----------------------------------------------------------------------------
+# Declare command line parameters
+# ----------------------------------------------------------------------------
+set parameters {
+    {projectname.arg ""   "Project Name"}
+}
+array set arg [::cmdline::getoptions argv $parameters]
+
+# ----------------------------------------------------------------------------
+# Verify required paramters
+# ----------------------------------------------------------------------------
+set requiredParameters {projectname}
+foreach parameter $requiredParameters {
+    if {$arg($parameter) == ""} {
+        puts stderr "Missing required parameter: -$parameter"
+        exit 1
+    }
+}
+
+
+	# ----------------------------------------------------------------------------
+	# Create project
+	# ----------------------------------------------------------------------------
+	project_new $arg(projectname) -overwrite
+	
+	# ----------------------------------------------------------------------------
+	# Assign family, device, and top-level file
+	# ----------------------------------------------------------------------------
+	set_global_assignment -name FAMILY "Cyclone II"
+	set_global_assignment -name DEVICE EP2C20F484C7
+	
+	# ----------------------------------------------------------------------------
+	# Default settings
+	# ----------------------------------------------------------------------------
+	set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+	set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
+	set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
+	
+	# ----------------------------------------------------------------------------
+	# Design files
+	# ----------------------------------------------------------------------------
+	#set_global_assignment -name VHDL_FILE ../src/e_cntdnmodm.vhd
+	#set_global_assignment -name VHDL_FILE ../src/a_cntdnmodm_rtl.vhd
+        # The following file is generated by the make process and contains
+        # the vhdl files which belong to the project
+        source quartus_vhdl_source_files.tcl
+	
+	# ----------------------------------------------------------------------------
+	# Pin Assignments
+	# ----------------------------------------------------------------------------
+	# set_location_assignment PIN_L1 -to CLOCK_50
+	source $arg(projectname)_pins.tcl 
+
+	# ----------------------------------------------------------------------------
+	# Close project
+	# ----------------------------------------------------------------------------
+	project_close
+
+
diff --git a/scripts/de1_pin_assignments_minimumio.csv b/scripts/de1_pin_assignments_minimumio.csv
new file mode 100644
index 0000000..97cfcd8
--- /dev/null
+++ b/scripts/de1_pin_assignments_minimumio.csv
@@ -0,0 +1,282 @@
+# This are all pin location assignments derived from the CDROM file

+# Friedrich Beckmann, 27.3.2014

+

+To,Location

+GPIO_0[0],PIN_A13

+GPIO_0[1],PIN_B13

+GPIO_0[2],PIN_A14

+GPIO_0[3],PIN_B14

+GPIO_0[4],PIN_A15

+GPIO_0[5],PIN_B15

+GPIO_0[6],PIN_A16

+GPIO_0[7],PIN_B16

+GPIO_0[8],PIN_A17

+GPIO_0[9],PIN_B17

+GPIO_0[10],PIN_A18

+GPIO_0[11],PIN_B18

+GPIO_0[12],PIN_A19

+GPIO_0[13],PIN_B19

+GPIO_0[14],PIN_A20

+GPIO_0[15],PIN_B20

+GPIO_0[16],PIN_C21

+GPIO_0[17],PIN_C22

+GPIO_0[18],PIN_D21

+GPIO_0[19],PIN_D22

+GPIO_0[20],PIN_E21

+GPIO_0[21],PIN_E22

+GPIO_0[22],PIN_F21

+GPIO_0[23],PIN_F22

+GPIO_0[24],PIN_G21

+GPIO_0[25],PIN_G22

+GPIO_0[26],PIN_J21

+GPIO_0[27],PIN_J22

+GPIO_0[28],PIN_K21

+GPIO_0[29],PIN_K22

+GPIO_0[30],PIN_J19

+GPIO_0[31],PIN_J20

+GPIO_0[32],PIN_J18

+GPIO_0[33],PIN_K20

+GPIO_0[34],PIN_L19

+GPIO_0[35],PIN_L18

+GPIO_1[0],PIN_H12

+GPIO_1[1],PIN_H13

+GPIO_1[2],PIN_H14

+GPIO_1[3],PIN_G15

+GPIO_1[4],PIN_E14

+GPIO_1[5],PIN_E15

+GPIO_1[6],PIN_F15

+GPIO_1[7],PIN_G16

+GPIO_1[8],PIN_F12

+GPIO_1[9],PIN_F13

+GPIO_1[10],PIN_C14

+GPIO_1[11],PIN_D14

+GPIO_1[12],PIN_D15

+GPIO_1[13],PIN_D16

+GPIO_1[14],PIN_C17

+GPIO_1[15],PIN_C18

+GPIO_1[16],PIN_C19

+GPIO_1[17],PIN_C20

+GPIO_1[18],PIN_D19

+GPIO_1[19],PIN_D20

+GPIO_1[20],PIN_E20

+GPIO_1[21],PIN_F20

+GPIO_1[22],PIN_E19

+GPIO_1[23],PIN_E18

+GPIO_1[24],PIN_G20

+GPIO_1[25],PIN_G18

+GPIO_1[26],PIN_G17

+GPIO_1[27],PIN_H17

+GPIO_1[28],PIN_J15

+GPIO_1[29],PIN_H18

+GPIO_1[30],PIN_N22

+GPIO_1[31],PIN_N21

+GPIO_1[32],PIN_P15

+GPIO_1[33],PIN_N15

+GPIO_1[34],PIN_P17

+GPIO_1[35],PIN_P18

+SW[0],PIN_L22

+SW[1],PIN_L21

+SW[2],PIN_M22

+SW[3],PIN_V12

+SW[4],PIN_W12

+SW[5],PIN_U12

+SW[6],PIN_U11

+SW[7],PIN_M2

+SW[8],PIN_M1

+SW[9],PIN_L2

+HEX0[0],PIN_J2

+HEX0[1],PIN_J1

+HEX0[2],PIN_H2

+HEX0[3],PIN_H1

+HEX0[4],PIN_F2

+HEX0[5],PIN_F1

+HEX0[6],PIN_E2

+HEX1[0],PIN_E1

+HEX1[1],PIN_H6

+HEX1[2],PIN_H5

+HEX1[3],PIN_H4

+HEX1[4],PIN_G3

+HEX1[5],PIN_D2

+HEX1[6],PIN_D1

+HEX2[0],PIN_G5

+HEX2[1],PIN_G6

+HEX2[2],PIN_C2

+HEX2[3],PIN_C1

+HEX2[4],PIN_E3

+HEX2[5],PIN_E4

+HEX2[6],PIN_D3

+HEX3[0],PIN_F4

+HEX3[1],PIN_D5

+HEX3[2],PIN_D6

+HEX3[3],PIN_J4

+HEX3[4],PIN_L8

+HEX3[5],PIN_F3

+HEX3[6],PIN_D4

+KEY[0],PIN_R22

+KEY[1],PIN_R21

+KEY[2],PIN_T22

+KEY[3],PIN_T21

+LEDR[0],PIN_R20

+LEDR[1],PIN_R19

+LEDR[2],PIN_U19

+LEDR[3],PIN_Y19

+LEDR[4],PIN_T18

+LEDR[5],PIN_V19

+LEDR[6],PIN_Y18

+LEDR[7],PIN_U18

+LEDR[8],PIN_R18

+LEDR[9],PIN_R17

+LEDG[0],PIN_U22

+LEDG[1],PIN_U21

+LEDG[2],PIN_V22

+LEDG[3],PIN_V21

+LEDG[4],PIN_W22

+LEDG[5],PIN_W21

+LEDG[6],PIN_Y22

+LEDG[7],PIN_Y21

+CLOCK_27[0],PIN_D12

+CLOCK_27[1],PIN_E12

+CLOCK_24[0],PIN_B12

+CLOCK_24[1],PIN_A12

+CLOCK_50,PIN_L1

+EXT_CLOCK,PIN_M21

+PS2_CLK,PIN_H15

+PS2_DAT,PIN_J14

+UART_RXD,PIN_F14

+UART_TXD,PIN_G12

+TDI,PIN_E8

+TCS,PIN_D8

+TCK,PIN_C7

+TDO,PIN_D7

+VGA_R[0],PIN_D9

+VGA_R[1],PIN_C9

+VGA_R[2],PIN_A7

+VGA_R[3],PIN_B7

+VGA_G[0],PIN_B8

+VGA_G[1],PIN_C10

+VGA_G[2],PIN_B9

+VGA_G[3],PIN_A8

+VGA_B[0],PIN_A9

+VGA_B[1],PIN_D11

+VGA_B[2],PIN_A10

+VGA_B[3],PIN_B10

+VGA_HS,PIN_A11

+VGA_VS,PIN_B11

+I2C_SCLK,PIN_A3

+I2C_SDAT,PIN_B3

+AUD_ADCLRCK,PIN_A6

+AUD_ADCDAT,PIN_B6

+AUD_DACLRCK,PIN_A5

+AUD_DACDAT,PIN_B5

+AUD_XCK,PIN_B4

+AUD_BCLK,PIN_A4

+DRAM_ADDR[0],PIN_W4

+DRAM_ADDR[1],PIN_W5

+DRAM_ADDR[2],PIN_Y3

+DRAM_ADDR[3],PIN_Y4

+DRAM_ADDR[4],PIN_R6

+DRAM_ADDR[5],PIN_R5

+DRAM_ADDR[6],PIN_P6

+DRAM_ADDR[7],PIN_P5

+DRAM_ADDR[8],PIN_P3

+DRAM_ADDR[9],PIN_N4

+DRAM_ADDR[10],PIN_W3

+DRAM_ADDR[11],PIN_N6

+DRAM_BA_0,PIN_U3

+DRAM_BA_1,PIN_V4

+DRAM_CAS_N,PIN_T3

+DRAM_CKE,PIN_N3

+DRAM_CLK,PIN_U4

+DRAM_CS_N,PIN_T6

+DRAM_DQ[0],PIN_U1

+DRAM_DQ[1],PIN_U2

+DRAM_DQ[2],PIN_V1

+DRAM_DQ[3],PIN_V2

+DRAM_DQ[4],PIN_W1

+DRAM_DQ[5],PIN_W2

+DRAM_DQ[6],PIN_Y1

+DRAM_DQ[7],PIN_Y2

+DRAM_DQ[8],PIN_N1

+DRAM_DQ[9],PIN_N2

+DRAM_DQ[10],PIN_P1

+DRAM_DQ[11],PIN_P2

+DRAM_DQ[12],PIN_R1

+DRAM_DQ[13],PIN_R2

+DRAM_DQ[14],PIN_T1

+DRAM_DQ[15],PIN_T2

+DRAM_LDQM,PIN_R7

+DRAM_RAS_N,PIN_T5

+DRAM_UDQM,PIN_M5

+DRAM_WE_N,PIN_R8

+FL_ADDR[0],PIN_AB20

+FL_ADDR[1],PIN_AA14

+FL_ADDR[2],PIN_Y16

+FL_ADDR[3],PIN_R15

+FL_ADDR[4],PIN_T15

+FL_ADDR[5],PIN_U15

+FL_ADDR[6],PIN_V15

+FL_ADDR[7],PIN_W15

+FL_ADDR[8],PIN_R14

+FL_ADDR[9],PIN_Y13

+FL_ADDR[10],PIN_R12

+FL_ADDR[11],PIN_T12

+FL_ADDR[12],PIN_AB14

+FL_ADDR[13],PIN_AA13

+FL_ADDR[14],PIN_AB13

+FL_ADDR[15],PIN_AA12

+FL_ADDR[16],PIN_AB12

+FL_ADDR[17],PIN_AA20

+FL_ADDR[18],PIN_U14

+FL_ADDR[19],PIN_V14

+FL_ADDR[20],PIN_U13

+FL_ADDR[21],PIN_R13

+FL_DQ[0],PIN_AB16

+FL_DQ[1],PIN_AA16

+FL_DQ[2],PIN_AB17

+FL_DQ[3],PIN_AA17

+FL_DQ[4],PIN_AB18

+FL_DQ[5],PIN_AA18

+FL_DQ[6],PIN_AB19

+FL_DQ[7],PIN_AA19

+FL_OE_N,PIN_AA15

+FL_RST_N,PIN_W14

+FL_WE_N,PIN_Y14

+SRAM_ADDR[0],PIN_AA3

+SRAM_ADDR[1],PIN_AB3

+SRAM_ADDR[2],PIN_AA4

+SRAM_ADDR[3],PIN_AB4

+SRAM_ADDR[4],PIN_AA5

+SRAM_ADDR[5],PIN_AB10

+SRAM_ADDR[6],PIN_AA11

+SRAM_ADDR[7],PIN_AB11

+SRAM_ADDR[8],PIN_V11

+SRAM_ADDR[9],PIN_W11

+SRAM_ADDR[10],PIN_R11

+SRAM_ADDR[11],PIN_T11

+SRAM_ADDR[12],PIN_Y10

+SRAM_ADDR[13],PIN_U10

+SRAM_ADDR[14],PIN_R10

+SRAM_ADDR[15],PIN_T7

+SRAM_ADDR[16],PIN_Y6

+SRAM_ADDR[17],PIN_Y5

+SRAM_CE_N,PIN_AB5

+SRAM_DQ[0],PIN_AA6

+SRAM_DQ[1],PIN_AB6

+SRAM_DQ[2],PIN_AA7

+SRAM_DQ[3],PIN_AB7

+SRAM_DQ[4],PIN_AA8

+SRAM_DQ[5],PIN_AB8

+SRAM_DQ[6],PIN_AA9

+SRAM_DQ[7],PIN_AB9

+SRAM_DQ[8],PIN_Y9

+SRAM_DQ[9],PIN_W9

+SRAM_DQ[10],PIN_V9

+SRAM_DQ[11],PIN_U9

+SRAM_DQ[12],PIN_R9

+SRAM_DQ[13],PIN_W8

+SRAM_DQ[14],PIN_V8

+SRAM_DQ[15],PIN_U8

+SRAM_LB_N,PIN_Y7

+SRAM_OE_N,PIN_T8

+SRAM_UB_N,PIN_W7

+SRAM_WE_N,PIN_AA10

diff --git a/scripts/de1_pin_assignments_minimumio.tcl b/scripts/de1_pin_assignments_minimumio.tcl
new file mode 100644
index 0000000..21b1109
--- /dev/null
+++ b/scripts/de1_pin_assignments_minimumio.tcl
@@ -0,0 +1,279 @@
+# All pin assignments from CDROM as tcl script

+set_location_assignment PIN_A13 -to GPIO_0[0] 

+set_location_assignment PIN_B13 -to GPIO_0[1] 

+set_location_assignment PIN_A14 -to GPIO_0[2] 

+set_location_assignment PIN_B14 -to GPIO_0[3] 

+set_location_assignment PIN_A15 -to GPIO_0[4] 

+set_location_assignment PIN_B15 -to GPIO_0[5] 

+set_location_assignment PIN_A16 -to GPIO_0[6] 

+set_location_assignment PIN_B16 -to GPIO_0[7] 

+set_location_assignment PIN_A17 -to GPIO_0[8] 

+set_location_assignment PIN_B17 -to GPIO_0[9] 

+set_location_assignment PIN_A18 -to GPIO_0[10]

+set_location_assignment PIN_B18 -to GPIO_0[11]

+set_location_assignment PIN_A19 -to GPIO_0[12]

+set_location_assignment PIN_B19 -to GPIO_0[13]

+set_location_assignment PIN_A20 -to GPIO_0[14]

+set_location_assignment PIN_B20 -to GPIO_0[15]

+set_location_assignment PIN_C21 -to GPIO_0[16]

+set_location_assignment PIN_C22 -to GPIO_0[17]

+set_location_assignment PIN_D21 -to GPIO_0[18]

+set_location_assignment PIN_D22 -to GPIO_0[19]

+set_location_assignment PIN_E21 -to GPIO_0[20]

+set_location_assignment PIN_E22 -to GPIO_0[21]

+set_location_assignment PIN_F21 -to GPIO_0[22]

+set_location_assignment PIN_F22 -to GPIO_0[23]

+set_location_assignment PIN_G21 -to GPIO_0[24]

+set_location_assignment PIN_G22 -to GPIO_0[25]

+set_location_assignment PIN_J21 -to GPIO_0[26]

+set_location_assignment PIN_J22 -to GPIO_0[27]

+set_location_assignment PIN_K21 -to GPIO_0[28]

+set_location_assignment PIN_K22 -to GPIO_0[29]

+set_location_assignment PIN_J19 -to GPIO_0[30]

+set_location_assignment PIN_J20 -to GPIO_0[31]

+set_location_assignment PIN_J18 -to GPIO_0[32]

+set_location_assignment PIN_K20 -to GPIO_0[33]

+set_location_assignment PIN_L19 -to GPIO_0[34]

+set_location_assignment PIN_L18 -to GPIO_0[35]

+set_location_assignment PIN_H12 -to GPIO_1[0] 

+set_location_assignment PIN_H13 -to GPIO_1[1] 

+set_location_assignment PIN_H14 -to GPIO_1[2] 

+set_location_assignment PIN_G15 -to GPIO_1[3] 

+set_location_assignment PIN_E14 -to GPIO_1[4] 

+set_location_assignment PIN_E15 -to GPIO_1[5] 

+set_location_assignment PIN_F15 -to GPIO_1[6] 

+set_location_assignment PIN_G16 -to GPIO_1[7] 

+set_location_assignment PIN_F12 -to GPIO_1[8] 

+set_location_assignment PIN_F13 -to GPIO_1[9] 

+set_location_assignment PIN_C14 -to GPIO_1[10]

+set_location_assignment PIN_D14 -to GPIO_1[11]

+set_location_assignment PIN_D15 -to GPIO_1[12]

+set_location_assignment PIN_D16 -to GPIO_1[13]

+set_location_assignment PIN_C17 -to GPIO_1[14]

+set_location_assignment PIN_C18 -to GPIO_1[15]

+set_location_assignment PIN_C19 -to GPIO_1[16]

+set_location_assignment PIN_C20 -to GPIO_1[17]

+set_location_assignment PIN_D19 -to GPIO_1[18]

+set_location_assignment PIN_D20 -to GPIO_1[19]

+set_location_assignment PIN_E20 -to GPIO_1[20]

+set_location_assignment PIN_F20 -to GPIO_1[21]

+set_location_assignment PIN_E19 -to GPIO_1[22]

+set_location_assignment PIN_E18 -to GPIO_1[23]

+set_location_assignment PIN_G20 -to GPIO_1[24]

+set_location_assignment PIN_G18 -to GPIO_1[25]

+set_location_assignment PIN_G17 -to GPIO_1[26]

+set_location_assignment PIN_H17 -to GPIO_1[27]

+set_location_assignment PIN_J15 -to GPIO_1[28]

+set_location_assignment PIN_H18 -to GPIO_1[29]

+set_location_assignment PIN_N22 -to GPIO_1[30]

+set_location_assignment PIN_N21 -to GPIO_1[31]

+set_location_assignment PIN_P15 -to GPIO_1[32]

+set_location_assignment PIN_N15 -to GPIO_1[33]

+set_location_assignment PIN_P17 -to GPIO_1[34]

+set_location_assignment PIN_P18 -to GPIO_1[35]

+set_location_assignment PIN_L22 -to SW[0]

+set_location_assignment PIN_L21 -to SW[1]

+set_location_assignment PIN_M22 -to SW[2]

+set_location_assignment PIN_V12 -to SW[3]

+set_location_assignment PIN_W12 -to SW[4]

+set_location_assignment PIN_U12 -to SW[5]

+set_location_assignment PIN_U11 -to SW[6]

+set_location_assignment PIN_M2  -to SW[7]

+set_location_assignment PIN_M1  -to SW[8]

+set_location_assignment PIN_L2  -to SW[9]

+set_location_assignment PIN_J2  -to HEX0[0]

+set_location_assignment PIN_J1  -to HEX0[1]

+set_location_assignment PIN_H2  -to HEX0[2]

+set_location_assignment PIN_H1  -to HEX0[3]

+set_location_assignment PIN_F2  -to HEX0[4]

+set_location_assignment PIN_F1  -to HEX0[5]

+set_location_assignment PIN_E2  -to HEX0[6]

+set_location_assignment PIN_E1  -to HEX1[0]

+set_location_assignment PIN_H6  -to HEX1[1]

+set_location_assignment PIN_H5  -to HEX1[2]

+set_location_assignment PIN_H4  -to HEX1[3]

+set_location_assignment PIN_G3  -to HEX1[4]

+set_location_assignment PIN_D2  -to HEX1[5]

+set_location_assignment PIN_D1  -to HEX1[6]

+set_location_assignment PIN_G5  -to HEX2[0]

+set_location_assignment PIN_G6  -to HEX2[1]

+set_location_assignment PIN_C2  -to HEX2[2]

+set_location_assignment PIN_C1  -to HEX2[3]

+set_location_assignment PIN_E3  -to HEX2[4]

+set_location_assignment PIN_E4  -to HEX2[5]

+set_location_assignment PIN_D3  -to HEX2[6]

+set_location_assignment PIN_F4  -to HEX3[0]

+set_location_assignment PIN_D5  -to HEX3[1]

+set_location_assignment PIN_D6  -to HEX3[2]

+set_location_assignment PIN_J4  -to HEX3[3]

+set_location_assignment PIN_L8  -to HEX3[4]

+set_location_assignment PIN_F3  -to HEX3[5]

+set_location_assignment PIN_D4  -to HEX3[6]

+set_location_assignment PIN_R22 -to KEY[0] 

+set_location_assignment PIN_R21 -to KEY[1] 

+set_location_assignment PIN_T22 -to KEY[2] 

+set_location_assignment PIN_T21 -to KEY[3] 

+set_location_assignment PIN_R20 -to LEDR[0]

+set_location_assignment PIN_R19 -to LEDR[1]

+set_location_assignment PIN_U19 -to LEDR[2]

+set_location_assignment PIN_Y19 -to LEDR[3]

+set_location_assignment PIN_T18 -to LEDR[4]

+set_location_assignment PIN_V19 -to LEDR[5]

+set_location_assignment PIN_Y18 -to LEDR[6]

+set_location_assignment PIN_U18 -to LEDR[7]

+set_location_assignment PIN_R18 -to LEDR[8]

+set_location_assignment PIN_R17 -to LEDR[9]

+set_location_assignment PIN_U22 -to LEDG[0]

+set_location_assignment PIN_U21 -to LEDG[1]

+set_location_assignment PIN_V22 -to LEDG[2]

+set_location_assignment PIN_V21 -to LEDG[3]

+set_location_assignment PIN_W22 -to LEDG[4]

+set_location_assignment PIN_W21 -to LEDG[5]

+set_location_assignment PIN_Y22 -to LEDG[6]

+set_location_assignment PIN_Y21 -to LEDG[7]

+set_location_assignment PIN_D12 -to CLOCK_27[0]

+set_location_assignment PIN_E12 -to CLOCK_27[1]

+set_location_assignment PIN_B12 -to CLOCK_24[0]

+set_location_assignment PIN_A12 -to CLOCK_24[1]

+set_location_assignment PIN_L1  -to CLOCK_50   

+set_location_assignment PIN_M21 -to EXT_CLOCK  

+set_location_assignment PIN_H15 -to PS2_CLK    

+set_location_assignment PIN_J14 -to PS2_DAT    

+set_location_assignment PIN_F14 -to UART_RXD   

+set_location_assignment PIN_G12 -to UART_TXD   

+set_location_assignment PIN_E8  -to TDI        

+set_location_assignment PIN_D8  -to TCS        

+set_location_assignment PIN_C7  -to TCK        

+set_location_assignment PIN_D7  -to TDO         

+set_location_assignment PIN_D9  -to VGA_R[0]

+set_location_assignment PIN_C9	-to VGA_R[1]

+set_location_assignment PIN_A7	-to VGA_R[2]

+set_location_assignment PIN_B7	-to VGA_R[3]

+set_location_assignment PIN_B8	-to VGA_G[0]

+set_location_assignment PIN_C10 -to VGA_G[1]

+set_location_assignment PIN_B9	-to VGA_G[2]

+set_location_assignment PIN_A8	-to VGA_G[3]

+set_location_assignment PIN_A9	-to VGA_B[0]

+set_location_assignment PIN_D11 -to VGA_B[1]

+set_location_assignment PIN_A10 -to VGA_B[2]

+set_location_assignment PIN_B10 -to VGA_B[3]

+set_location_assignment PIN_A11 -to VGA_HS  

+set_location_assignment PIN_B11 -to VGA_VS  

+set_location_assignment PIN_A3 -to I2C_SCLK    

+set_location_assignment PIN_B3 -to I2C_SDAT    

+set_location_assignment PIN_A6 -to AUD_ADCLRCK 

+set_location_assignment PIN_B6 -to AUD_ADCDAT  

+set_location_assignment PIN_A5 -to AUD_DACLRCK 

+set_location_assignment PIN_B5 -to AUD_DACDAT  

+set_location_assignment PIN_B4 -to AUD_XCK     

+set_location_assignment PIN_A4 -to AUD_BCLK    

+set_location_assignment PIN_W4 -to DRAM_ADDR[0]

+set_location_assignment PIN_W5 -to DRAM_ADDR[1]

+set_location_assignment PIN_Y3 -to DRAM_ADDR[2]

+set_location_assignment PIN_Y4 -to DRAM_ADDR[3]

+set_location_assignment PIN_R6 -to DRAM_ADDR[4]

+set_location_assignment PIN_R5 -to DRAM_ADDR[5]

+set_location_assignment PIN_P6 -to DRAM_ADDR[6]

+set_location_assignment PIN_P5 -to DRAM_ADDR[7]

+set_location_assignment PIN_P3 -to DRAM_ADDR[8]

+set_location_assignment PIN_N4 -to DRAM_ADDR[9]

+set_location_assignment PIN_W3 -to DRAM_ADDR[10]

+set_location_assignment PIN_N6 -to DRAM_ADDR[11]

+set_location_assignment PIN_U3 -to DRAM_BA_0    

+set_location_assignment PIN_V4 -to DRAM_BA_1    

+set_location_assignment PIN_T3 -to DRAM_CAS_N   

+set_location_assignment PIN_N3 -to DRAM_CKE     

+set_location_assignment PIN_U4 -to DRAM_CLK     

+set_location_assignment PIN_T6 -to DRAM_CS_N    

+set_location_assignment PIN_U1 -to DRAM_DQ[0] 

+set_location_assignment PIN_U2 -to DRAM_DQ[1] 

+set_location_assignment PIN_V1 -to DRAM_DQ[2] 

+set_location_assignment PIN_V2 -to DRAM_DQ[3] 

+set_location_assignment PIN_W1 -to DRAM_DQ[4] 

+set_location_assignment PIN_W2 -to DRAM_DQ[5] 

+set_location_assignment PIN_Y1 -to DRAM_DQ[6] 

+set_location_assignment PIN_Y2 -to DRAM_DQ[7] 

+set_location_assignment PIN_N1 -to DRAM_DQ[8] 

+set_location_assignment PIN_N2 -to DRAM_DQ[9] 

+set_location_assignment PIN_P1 -to DRAM_DQ[10]

+set_location_assignment PIN_P2 -to DRAM_DQ[11]

+set_location_assignment PIN_R1 -to DRAM_DQ[12]

+set_location_assignment PIN_R2 -to DRAM_DQ[13]

+set_location_assignment PIN_T1 -to DRAM_DQ[14]

+set_location_assignment PIN_T2 -to DRAM_DQ[15]

+set_location_assignment PIN_R7   -to DRAM_LDQM 

+set_location_assignment PIN_T5   -to DRAM_RAS_N

+set_location_assignment PIN_M5   -to DRAM_UDQM 

+set_location_assignment PIN_R8   -to DRAM_WE_N 

+set_location_assignment PIN_AB20 -to FL_ADDR[0]

+set_location_assignment PIN_AA14 -to FL_ADDR[1]

+set_location_assignment PIN_Y16  -to FL_ADDR[2]

+set_location_assignment PIN_R15  -to FL_ADDR[3]

+set_location_assignment PIN_T15  -to FL_ADDR[4]

+set_location_assignment PIN_U15  -to FL_ADDR[5]

+set_location_assignment PIN_V15  -to FL_ADDR[6]

+set_location_assignment PIN_W15  -to FL_ADDR[7]

+set_location_assignment PIN_R14  -to FL_ADDR[8]

+set_location_assignment PIN_Y13  -to FL_ADDR[9] 

+set_location_assignment PIN_R12  -to FL_ADDR[10]

+set_location_assignment PIN_T12  -to FL_ADDR[11]

+set_location_assignment PIN_AB14 -to FL_ADDR[12]

+set_location_assignment PIN_AA13 -to FL_ADDR[13]

+set_location_assignment PIN_AB13 -to FL_ADDR[14]

+set_location_assignment PIN_AA12 -to FL_ADDR[15]

+set_location_assignment PIN_AB12 -to FL_ADDR[16]

+set_location_assignment PIN_AA20 -to FL_ADDR[17]

+set_location_assignment PIN_U14  -to FL_ADDR[18]

+set_location_assignment PIN_V14  -to FL_ADDR[19]

+set_location_assignment PIN_U13  -to FL_ADDR[20]

+set_location_assignment PIN_R13  -to FL_ADDR[21]

+set_location_assignment PIN_AB16 -to FL_DQ[0]

+set_location_assignment PIN_AA16 -to FL_DQ[1]

+set_location_assignment PIN_AB17 -to FL_DQ[2]

+set_location_assignment PIN_AA17 -to FL_DQ[3]

+set_location_assignment PIN_AB18 -to FL_DQ[4]

+set_location_assignment PIN_AA18 -to FL_DQ[5]

+set_location_assignment PIN_AB19 -to FL_DQ[6]

+set_location_assignment PIN_AA19 -to FL_DQ[7]

+set_location_assignment PIN_AA15 -to FL_OE_N 

+set_location_assignment PIN_W14  -to FL_RST_N

+set_location_assignment PIN_Y14  -to FL_WE_N 

+set_location_assignment PIN_AA3  -to SRAM_ADDR[0] 

+set_location_assignment PIN_AB3  -to SRAM_ADDR[1] 

+set_location_assignment PIN_AA4  -to SRAM_ADDR[2] 

+set_location_assignment PIN_AB4  -to SRAM_ADDR[3] 

+set_location_assignment PIN_AA5  -to SRAM_ADDR[4] 

+set_location_assignment PIN_AB10 -to SRAM_ADDR[5] 

+set_location_assignment PIN_AA11 -to SRAM_ADDR[6] 

+set_location_assignment PIN_AB11 -to SRAM_ADDR[7] 

+set_location_assignment PIN_V11  -to SRAM_ADDR[8] 

+set_location_assignment PIN_W11  -to SRAM_ADDR[9] 

+set_location_assignment PIN_R11  -to SRAM_ADDR[10]

+set_location_assignment PIN_T11  -to SRAM_ADDR[11]

+set_location_assignment PIN_Y10  -to SRAM_ADDR[12]

+set_location_assignment PIN_U10  -to SRAM_ADDR[13]

+set_location_assignment PIN_R10  -to SRAM_ADDR[14]

+set_location_assignment PIN_T7   -to SRAM_ADDR[15]

+set_location_assignment PIN_Y6   -to SRAM_ADDR[16]

+set_location_assignment PIN_Y5   -to SRAM_ADDR[17]

+set_location_assignment PIN_AB5  -to SRAM_CE_N  

+set_location_assignment PIN_AA6  -to SRAM_DQ[0] 

+set_location_assignment PIN_AB6  -to SRAM_DQ[1] 

+set_location_assignment PIN_AA7  -to SRAM_DQ[2] 

+set_location_assignment PIN_AB7  -to SRAM_DQ[3] 

+set_location_assignment PIN_AA8  -to SRAM_DQ[4] 

+set_location_assignment PIN_AB8  -to SRAM_DQ[5] 

+set_location_assignment PIN_AA9  -to SRAM_DQ[6] 

+set_location_assignment PIN_AB9  -to SRAM_DQ[7] 

+set_location_assignment PIN_Y9   -to SRAM_DQ[8] 

+set_location_assignment PIN_W9   -to SRAM_DQ[9] 

+set_location_assignment PIN_V9   -to SRAM_DQ[10]

+set_location_assignment PIN_U9   -to SRAM_DQ[11]

+set_location_assignment PIN_R9   -to SRAM_DQ[12]

+set_location_assignment PIN_W8   -to SRAM_DQ[13]

+set_location_assignment PIN_V8   -to SRAM_DQ[14]

+set_location_assignment PIN_U8   -to SRAM_DQ[15]

+set_location_assignment PIN_Y7   -to SRAM_LB_N  

+set_location_assignment PIN_T8   -to SRAM_OE_N  

+set_location_assignment PIN_W7   -to SRAM_UB_N  

+set_location_assignment PIN_AA10 -to SRAM_WE_N  

diff --git a/scripts/design_project_directory_structure.txt b/scripts/design_project_directory_structure.txt
new file mode 100644
index 0000000..6beefbb
--- /dev/null
+++ b/scripts/design_project_directory_structure.txt
@@ -0,0 +1,35 @@
+## ----------------------------------------------------------------------------
+## Description: 
+## ------------
+## assumes the following design directory structure as prerequisite
+## 
+## DigitaltechnikPraktikum
+## |   
+## +---src
+## |       and2gate_equation.vhd
+## |       invgate_equation.vhd
+## |       mux2to1_structure.vhd
+## |       or2gate_equation.vhd
+## |       t_mux2to1.vhd
+## |       de1_mux2to1_structure.vhd
+## |
+## +---sim
+## |   |   makefile
+## |   |
+## |   \---mux2to1
+## |           makefile
+## |           makefile.sources
+## |
+## +---pnr
+## |   |   makefile
+## |   |
+## |   \---de1_mux2to1
+## |           de1_mux2to1_pins.tcl
+## |           makefile
+## |
+## \---scripts
+##         de1_pin_assignments_minimumio.csv
+##         de1_pin_assignments_minimumio.tcl
+##         modelsim.ini
+##         quartus_project_settings.tcl
+## ----------------------------------------------------------------------------
diff --git a/scripts/modelsim.ini b/scripts/modelsim.ini
new file mode 100644
index 0000000..81e2701
--- /dev/null
+++ b/scripts/modelsim.ini
@@ -0,0 +1,351 @@
+;; ----------------------------------------------------------------------------
+;; Script     : modelsim.ini
+;; ----------------------------------------------------------------------------
+;; Author     : Johann Faerber
+;; Company    : University of Applied Sciences Augsburg
+;; ----------------------------------------------------------------------------
+;; Description: original version modified
+;;              - deleted all VHDL and Verilog device libraries
+;;              - modified compiler standard to VHDL93 = 2008
+;; ----------------------------------------------------------------------------
+;; Revisions  : see end of file
+;; ----------------------------------------------------------------------------
+
+; Copyright 1991-2009 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF 
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;   
+
+[Library]
+std = $MODEL_TECH/../std
+ieee = $MODEL_TECH/../ieee
+verilog = $MODEL_TECH/../verilog
+vital2000 = $MODEL_TECH/../vital2000
+std_developerskit = $MODEL_TECH/../std_developerskit
+synopsys = $MODEL_TECH/../synopsys
+modelsim_lib = $MODEL_TECH/../modelsim_lib
+sv_std = $MODEL_TECH/../sv_std
+
+; Altera Primitive libraries
+;
+; VHDL Section
+;
+altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
+altera = $MODEL_TECH/../altera/vhdl/altera
+altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim
+lpm = $MODEL_TECH/../altera/vhdl/220model
+220model = $MODEL_TECH/../altera/vhdl/220model
+
+[vcom]
+; VHDL93 variable selects language version as the default. 
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Default or value of 3 or 2008 for VHDL-2008.
+VHDL93 = 2008
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+;    -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+[vlog]
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Turn on incremental compilation of modules. Default is off.
+; Incremental = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+[vsim]
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ns
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Directive to license manager:
+; vhdl          Immediately reserve a VHDL license
+; vlog          Immediately reserve a Verilog license
+; plus          Immediately reserve a VHDL and Verilog license
+; nomgc         Do not look for Mentor Graphics Licenses
+; nomti         Do not look for Model Technology Licenses
+; noqueue       Do not wait in the license queue when a license isn't available
+; viewsim	Try for viewer license but accept simulator license(s) instead
+;		of queuing for viewer license
+; License = plus
+
+; Stop the simulator after a VHDL/Verilog assertion message
+; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
+BreakOnAssertion = 3
+
+; Assertion Message Format
+; %S - Severity Level 
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %% - print '%' character
+; AssertionFormat = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
+
+; Assertion File - alternate file for storing VHDL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Default radix for all windows and commands...
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example, sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write.  Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+;   0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+;   0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings from the std_logic_arith, std_logic_unsigned
+; and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Control the format of the (VHDL) FOR generate statement label
+; for each iteration.  Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes.  The %s represents
+; the generate_label; the %d represents the generate parameter value
+; at a particular generate iteration (this is the position number if
+; the generate parameter is of an enumeration type).  Embedded whitespace
+; is allowed (but discouraged); leading and trailing whitespace is ignored.
+; Application of the format must result in a unique scope name over all
+; such names in the design so that name lookup can function properly.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave
+; DefaultRestartOptions = -force
+
+; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
+; (> 500 megabyte memory footprint). Default is disabled.
+; Specify number of megabytes to lock.
+; LockedMemory = 1000
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit.  Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time.  When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit).  Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit.  Limit WLF file size, as closely as possible,
+; to the specified number of megabytes.  If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends.  A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Automatic SDF compilation
+; Disables automatic compilation of SDF files in flows that support it.
+; Default is on, uncomment to turn off.
+; NoAutoSDFCompile = 1
+
+[lmc]
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: <msg directive> = <msg number>[,<msg number>...]
+; Examples:
+;   note = 3009
+;   warning = 3033
+;   error = 3010,3016
+;   fatal = 3016,3033
+;   suppress = 3009,3016,3043
+; The command verror <msg number> can be used to get the complete
+; description of a message.
+
+; Control transcripting of elaboration/runtime messages.
+; The default is to have messages appear in the transcript and 
+; recorded in the wlf file (messages that are recorded in the
+; wlf file can be viewed in the MsgViewer).  The other settings
+; are to send messages only to the transcript or only to the 
+; wlf file.  The valid values are
+;    both  {default}
+;    tran  {transcript only}
+;    wlf   {wlf file only}
+; msgmode = both
+
+;; ----------------------------------------------------------------------------
+;; Revisions:
+;; ----------
+;; $Id:$
+;; ----------------------------------------------------------------------------
diff --git a/scripts/quartus_project_flow.tcl b/scripts/quartus_project_flow.tcl
new file mode 100644
index 0000000..ab4e8db
--- /dev/null
+++ b/scripts/quartus_project_flow.tcl
@@ -0,0 +1,71 @@
+## ----------------------------------------------------------------------------
+## Script     : quartus_project_flow.tcl
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber, F. Beckmann
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: executes process steps in a quartus project
+##              depending on the parameter process
+##              expects project name as command line parameter 
+##              e.g.
+##              quartus_sh -t quartus_project_flow.tcl -projectname de1_mux2to1
+##                         -process compile
+## ----------------------------------------------------------------------------
+## Revisions  : see end of file
+## ----------------------------------------------------------------------------
+
+package require cmdline
+# Load Quartus II Tcl Project package
+package require ::quartus::project
+
+# ----------------------------------------------------------------------------
+# Declare command line parameters
+# ----------------------------------------------------------------------------
+set parameters {
+    {projectname.arg ""   "Project Name"}
+}
+array set arg [::cmdline::getoptions argv $parameters]
+
+# ----------------------------------------------------------------------------
+# Verify required paramters
+# ----------------------------------------------------------------------------
+set requiredParameters {projectname}
+foreach parameter $requiredParameters {
+    if {$arg($parameter) == ""} {
+        puts stderr "Missing required parameter: -$parameter"
+        exit 1
+    }
+}
+
+# ----------------------------------------------------------------------------
+# Check, if project exists
+# ----------------------------------------------------------------------------
+if { ![project_exists $arg(projectname)] } {
+    post_message -type error "Project $arg(projectname) does not exist"
+    exit
+}
+	# ----------------------------------------------------------------------------
+	# Open project
+	# ----------------------------------------------------------------------------
+	project_open $arg(projectname)
+
+    # ----------------------------------------------------------------------------
+    # Run specified design flow by parameter -process
+    # ----------------------------------------------------------------------------
+    load_package flow
+
+    execute_flow -compile
+
+	# ----------------------------------------------------------------------------
+    # Write Reports
+	# ----------------------------------------------------------------------------
+    load_package report
+    load_report $arg(projectname)
+    write_report_panel -file flowsummary.log "Flow Summary"
+
+	# ----------------------------------------------------------------------------
+	# Close project
+	# ----------------------------------------------------------------------------
+	project_close
+
+