1 files changed, 87 insertions, 0 deletions
diff --git a/VexRiscv/src/main/scala/vexriscv/demo/GenFullNoMmu.scala b/VexRiscv/src/main/scala/vexriscv/demo/GenFullNoMmu.scala
new file mode 100644
index 0000000..00ba8c9
--- /dev/null
+++ b/VexRiscv/src/main/scala/vexriscv/demo/GenFullNoMmu.scala
@@ -0,0 +1,87 @@
+package vexriscv.demo
+
+import vexriscv.plugin._
+import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
+import vexriscv.{plugin, VexRiscv, VexRiscvConfig}
+import spinal.core._
+
+/**
+ * Created by spinalvm on 15.06.17.
+ */
+object GenFullNoMmu extends App{
+  def cpu() = new VexRiscv(
+    config = VexRiscvConfig(
+      plugins = List(
+        new PcManagerSimplePlugin(
+          resetVector = 0x80000000l,
+          relaxedPcCalculation = false
+        ),
+        new IBusCachedPlugin(
+          prediction = STATIC,
+          config = InstructionCacheConfig(
+            cacheSize = 4096,
+            bytePerLine =32,
+            wayCount = 1,
+            addressWidth = 32,
+            cpuDataWidth = 32,
+            memDataWidth = 32,
+            catchIllegalAccess = true,
+            catchAccessFault = true,
+            asyncTagMemory = false,
+            twoCycleRam = true,
+            twoCycleCache = true
+          )
+        ),
+        new DBusCachedPlugin(
+          config = new DataCacheConfig(
+            cacheSize         = 4096,
+            bytePerLine       = 32,
+            wayCount          = 1,
+            addressWidth      = 32,
+            cpuDataWidth      = 32,
+            memDataWidth      = 32,
+            catchAccessError  = true,
+            catchIllegal      = true,
+            catchUnaligned    = true
+          )
+        ),
+        new StaticMemoryTranslatorPlugin(
+          ioRange      = _(31 downto 28) === 0xF
+        ),
+        new DecoderSimplePlugin(
+          catchIllegalInstruction = true
+        ),
+        new RegFilePlugin(
+          regFileReadyKind = plugin.SYNC,
+          zeroBoot = false
+        ),
+        new IntAluPlugin,
+        new SrcPlugin(
+          separatedAddSub = false,
+          executeInsertion = true
+        ),
+        new FullBarrelShifterPlugin,
+        new HazardSimplePlugin(
+          bypassExecute           = true,
+          bypassMemory            = true,
+          bypassWriteBack         = true,
+          bypassWriteBackBuffer   = true,
+          pessimisticUseSrc       = false,
+          pessimisticWriteRegFile = false,
+          pessimisticAddressMatch = false
+        ),
+        new MulPlugin,
+        new DivPlugin,
+        new CsrPlugin(CsrPluginConfig.small),
+        new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))),
+        new BranchPlugin(
+          earlyBranch = false,
+          catchAddressMisaligned = true
+        ),
+        new YamlPlugin("cpu0.yaml")
+      )
+    )
+  )
+
+  SpinalVerilog(cpu())
+}