diff options
Diffstat (limited to 'VexRiscv/src/test/cpp/briey')
| -rw-r--r-- | VexRiscv/src/test/cpp/briey/installs.txt | 22 | ||||
| -rw-r--r-- | VexRiscv/src/test/cpp/briey/jtag.gtkw | 40 | ||||
| -rw-r--r-- | VexRiscv/src/test/cpp/briey/main.cpp | 472 | ||||
| -rw-r--r-- | VexRiscv/src/test/cpp/briey/makefile | 59 | ||||
| -rw-r--r-- | VexRiscv/src/test/cpp/briey/sdram.gtkw | 115 | ||||
| -rw-r--r-- | VexRiscv/src/test/cpp/briey/wip.gtkw | 30 |
6 files changed, 738 insertions, 0 deletions
diff --git a/VexRiscv/src/test/cpp/briey/installs.txt b/VexRiscv/src/test/cpp/briey/installs.txt new file mode 100644 index 0000000..3cef523 --- /dev/null +++ b/VexRiscv/src/test/cpp/briey/installs.txt @@ -0,0 +1,22 @@ +sudo apt-get install libYAML-dev + + +sudo apt-get update +sudo apt-get install build-essential software-properties-common -y +sudo add-apt-repository ppa:ubuntu-toolchain-r/test -y +sudo apt-get update +sudo apt-get install gcc-6 g++-6 -y +sudo update-alternatives --install /usr/bin/gcc gcc /usr/bin/gcc-6 60 --slave /usr/bin/g++ g++ /usr/bin/g++-6 + + +wget -O boost_1_64_0.tar.gz http://sourceforge.net/projects/boost/files/boost/1.64.0/boost_1_64_0.tar.gz/download +tar xzvf boost_1_64_0.tar.gz +cd boost_1_64_0/ +./bootstrap.sh --prefix=/usr/local +./b2 +sudo ./b2 install + + + +echo "using gcc : 6.3 : /usr/bin/g++-6 ; " >> tools/build/src/user-config.jam +bjam --toolset=gcc-6 diff --git a/VexRiscv/src/test/cpp/briey/jtag.gtkw b/VexRiscv/src/test/cpp/briey/jtag.gtkw new file mode 100644 index 0000000..6ce65f3 --- /dev/null +++ b/VexRiscv/src/test/cpp/briey/jtag.gtkw @@ -0,0 +1,40 @@ +[*] +[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI +[*] Fri Jun 9 08:05:42 2017 +[*] +[dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/briey/Briey.vcd" +[dumpfile_mtime] "Fri Jun 9 08:05:37 2017" +[dumpfile_size] 2070466159 +[savefile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/briey/jtag.gtkw" +[timestart] 51980000000 +[size] 1776 953 +[pos] -1 -353 +*-33.000000 62611680000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] TOP. +[treeopen] TOP.Briey. +[treeopen] TOP.Briey.axi_jtagCtrl. +[sst_width] 288 +[signals_width] 302 +[sst_expanded] 1 +[sst_vpaned_height] 503 +@28 +TOP.io_jtag_tck +TOP.io_jtag_tdi +TOP.io_jtag_tdo +TOP.io_jtag_tms +@22 +TOP.Briey.axi_jtagCtrl.jtagBridge_1.jtag_tap_fsm_state[3:0] +TOP.Briey.axi_core_cpu.debug_bus_cmd_payload_address[7:0] +TOP.Briey.axi_core_cpu.debug_bus_cmd_payload_data[31:0] +@29 +TOP.Briey.axi_core_cpu.debug_bus_cmd_payload_wr +@28 +TOP.Briey.axi_core_cpu.debug_bus_cmd_ready +TOP.Briey.axi_core_cpu.debug_bus_cmd_valid +@22 +TOP.Briey.axi_core_cpu.debug_bus_rsp_data[31:0] +@28 +TOP.Briey.axi_core_cpu.DebugPlugin_haltIt +TOP.Briey.axi_core_cpu.DebugPlugin_haltedByBreak +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/VexRiscv/src/test/cpp/briey/main.cpp b/VexRiscv/src/test/cpp/briey/main.cpp new file mode 100644 index 0000000..bebe880 --- /dev/null +++ b/VexRiscv/src/test/cpp/briey/main.cpp @@ -0,0 +1,472 @@ +#include "VBriey.h" +#include "VBriey_Briey.h" +//#include "VBriey_Axi4VgaCtrl.h" +//#include "VBriey_VgaCtrl.h" +#ifdef REF +#include "VBriey_RiscvCore.h" +#endif +#include "verilated.h" +#include <stdio.h> +#include <iostream> +#include <stdlib.h> +#include <stdint.h> +#include <cstring> +#include <string.h> +#include <iostream> +#include <fstream> +#include <vector> +#include <iomanip> +#include <time.h> +#include <unistd.h> + +#include "VBriey_VexRiscv.h" + + +#include "../common/framework.h" +#include "../common/jtag.h" +#include "../common/uart.h" + + + +class SdramConfig{ +public: + uint32_t byteCount; + uint32_t bankCount; + uint32_t rowSize; + uint32_t colSize; + + SdramConfig(uint32_t byteCount, + uint32_t bankCount, + uint32_t rowSize, + uint32_t colSize){ + this->byteCount = byteCount; + this->bankCount = bankCount; + this->rowSize = rowSize; + this->colSize = colSize; + } +}; + +class SdramIo{ +public: + CData *BA; + CData *DQM; + CData *CASn; + CData *CKE; + CData *CSn; + CData *RASn; + CData *WEn; + SData *ADDR; + CData *DQ_read; + CData *DQ_write; + CData *DQ_writeEnable; +}; + +class Sdram : public SimElement{ +public: + + SdramConfig *config; + SdramIo *io; + + uint32_t CAS; + uint32_t burstLength; + + class Bank{ + public: + uint8_t *data; + SdramConfig *config; + + bool opened; + uint32_t openedRow; + void init(SdramConfig *config){ + this->config = config; + data = new uint8_t[config->rowSize * config->colSize * config->byteCount]; + opened = false; + } + + virtual ~Bank(){ + delete data; + } + + void activate(uint32_t row){ + if(opened) + cout << "SDRAM error open unclosed bank" << endl; + openedRow = row; + opened = true; + } + + void precharge(){ + opened = false; + } + + void write(uint32_t column, CData byteId, CData data){ + if(!opened) + cout << "SDRAM : write in closed bank" << endl; + uint32_t addr = byteId + (column + openedRow * config->colSize) * config->byteCount; + //printf("SDRAM : Write A=%08x D=%02x\n",addr,data); + this->data[addr] = data; + + } + + CData read(uint32_t column, CData byteId){ + if(!opened) + cout << "SDRAM : write in closed bank" << endl; + uint32_t addr = byteId + (column + openedRow * config->colSize) * config->byteCount; + //printf("SDRAM : Read A=%08x D=%02x\n",addr,data[addr]); + return data[addr]; + } + }; + + Bank* banks; + + CData * readShifter; + + Sdram(SdramConfig *config,SdramIo* io){ + this->config = config; + this->io = io; + banks = new Bank[config->bankCount]; + for(uint32_t bankId = 0;bankId < config->bankCount;bankId++) banks[bankId].init(config); + readShifter = new CData[config->byteCount*3]; + } + + virtual ~Sdram(){ + delete banks; + delete readShifter; + } + + + uint8_t ckeLast = 0; + + + virtual void postCycle(){ + if(CAS >= 2 && CAS <=3){ + for(uint32_t byteId = 0;byteId != config->byteCount;byteId++){ + io->DQ_read[byteId] = readShifter[byteId + (CAS-1)*config->byteCount]; + } + for(uint32_t latency = CAS-1;latency != 0;latency--){ //missing CKE + for(uint32_t byteId = 0;byteId != config->byteCount;byteId++){ + readShifter[byteId+latency*config->byteCount] = readShifter[byteId+(latency-1)*config->byteCount]; + } + } + } + } + + virtual void preCycle(){ + if(!*io->CSn && ckeLast){ + uint32_t code = ((*io->RASn) << 2) | ((*io->CASn) << 1) | ((*io->WEn) << 0); + switch(code){ + case 0: //Mode register set + if(*io->BA == 0 && (*io->ADDR & 0x400) == 0){ + CAS = ((*io->ADDR) >> 4) & 0x7; + burstLength = ((*io->ADDR) >> 0) & 0x7; + if((*io->ADDR & 0x388) != 0) + cout << "SDRAM : ???" << endl; + printf("SDRAM : MODE REGISTER DEFINITION CAS=%d burstLength=%d\n",CAS,burstLength); + } + break; + case 2: //Bank precharge + if((*io->ADDR & 0x400) != 0){ //all + for(uint32_t bankId = 0;bankId < config->bankCount;bankId++) + banks[bankId].precharge(); + } else { //single + banks[*io->BA].precharge(); + } + break; + case 3: //Bank activate + banks[*io->BA].activate(*io->ADDR & 0x7FF); + break; + case 4: //Write + if((*io->ADDR & 0x400) != 0) + cout << "SDRAM : Write autoprecharge not supported" << endl; + + if(*io->DQ_writeEnable == 0) + cout << "SDRAM : Write Wrong DQ direction" << endl; + + for(uint32_t byteId = 0;byteId < config->byteCount;byteId++){ + if(((*io->DQM >> byteId) & 1) == 0) + banks[*io->BA].write(*io->ADDR, byteId ,io->DQ_write[byteId]); + } + break; + + case 5: //Read + if((*io->ADDR & 0x400) != 0) + cout << "SDRAM : READ autoprecharge not supported" << endl; + + if(*io->DQ_writeEnable != 0) + cout << "SDRAM : READ Wrong DQ direction" << endl; + + //if(*io->DQM != config->byteCount-1) + //cout << "SDRAM : READ wrong DQM" << endl; + + for(uint32_t byteId = 0;byteId < config->byteCount;byteId++){ + readShifter[byteId] = banks[*io->BA].read(*io->ADDR, byteId); + } + break; + case 1: // Self refresh + break; + case 7: // NOP + break; + default: + cout << "SDRAM : unknown code" << endl; + break; + } + } + ckeLast = *io->CKE; + } +}; + + +class VexRiscvTracer : public SimElement{ +public: + VBriey_VexRiscv *cpu; + ofstream instructionTraces; + ofstream regTraces; + + VexRiscvTracer(VBriey_VexRiscv *cpu){ + this->cpu = cpu; +#ifdef TRACE_INSTRUCTION + instructionTraces.open ("instructionTrace.log"); +#endif +#ifdef TRACE_REG + regTraces.open ("regTraces.log"); +#endif + } + + + + virtual void preCycle(){ +#ifdef TRACE_INSTRUCTION + if(cpu->writeBack_arbitration_isFiring){ + instructionTraces << hex << setw(8) << cpu->writeBack_INSTRUCTION << endl; + } +#endif +#ifdef TRACE_REG + if(cpu->writeBack_RegFilePlugin_regFileWrite_valid == 1 && cpu->writeBack_RegFilePlugin_regFileWrite_payload_address != 0){ + regTraces << " PC " << hex << setw(8) << cpu->writeBack_PC << " : reg[" << dec << setw(2) << (uint32_t)cpu->writeBack_RegFilePlugin_regFileWrite_payload_address << "] = " << hex << setw(8) << cpu->writeBack_RegFilePlugin_regFileWrite_payload_data << endl; + } + +#endif + } +}; + + + + +#include <SDL2/SDL.h> +#include <assert.h> +#include <stdint.h> +#include <stdlib.h> + + +class Display : public SimElement{ +public: + int width, height; + uint32_t *pixels; + SDL_Window* window; + SDL_Renderer* renderer; + SDL_Texture * texture; + uint32_t x,y; + uint32_t refreshCounter = 0; + + Display(int width, int height){ + this->width = width; + this->height = height; + x = y = 0; + init(); + } + + virtual ~Display(){ + delete[] pixels; + SDL_DestroyTexture(texture); + SDL_DestroyRenderer(renderer); + SDL_DestroyWindow(window); + SDL_Quit(); + } + + void init(){ + + /* Initialize SDL. */ + if (SDL_Init(SDL_INIT_VIDEO) < 0) + return; + + /* Create the window where we will draw. */ + window = SDL_CreateWindow("VGA", + SDL_WINDOWPOS_CENTERED, SDL_WINDOWPOS_CENTERED, + width, height, + SDL_WINDOW_SHOWN); + + /* We must call SDL_CreateRenderer in order for draw calls to affect this window. */ + renderer = SDL_CreateRenderer(window, -1, 0); + + texture = SDL_CreateTexture(renderer, + SDL_PIXELFORMAT_ARGB8888, SDL_TEXTUREACCESS_STATIC, width, height); + pixels = new Uint32[width * height]; + memset(pixels, 0, width * height * sizeof(Uint32)); + } + + void set(uint32_t color){ + pixels[x + y*width] = color; + } + + void incX(){ + x++; + if(x >= width) x = width; + } + + void incY(){ + y++; + if(y >= height) y = height; + } + + void refresh(){ + //cout << "Display refresh " << refreshCounter++ << endl; + SDL_UpdateTexture(texture, NULL, pixels, 640 * sizeof(Uint32)); + SDL_RenderClear(renderer); + SDL_RenderCopy(renderer, texture, NULL, NULL); + SDL_RenderPresent(renderer); + memset(pixels, 0, width * height * sizeof(Uint32)); + } + + virtual void postCycle(){ + + } + + virtual void preCycle(){ + + } +}; + +class Vga : public Display{ +public: + VBriey* top; + Vga(VBriey* top,int width, int height) : Display(width, height){ + this->top = top; + } + + virtual ~Vga(){ + } + + virtual void postCycle(){ + + } + + uint32_t lastvSync = 0,lasthSync = 0; + virtual void preCycle(){ + if(!top->io_vga_vSync && lastvSync) { + y = 0; + refresh(); + } + if(!top->io_vga_hSync && lasthSync && x != 0) { + incY(); + x = 0; + } + if(top->io_vga_colorEn){ + this->set((top->io_vga_color_r << 19) + (top->io_vga_color_g << 10) + (top->io_vga_color_b << 3)); + incX(); + } + + lastvSync = top->io_vga_vSync; + lasthSync = top->io_vga_hSync; + } +}; + +class BrieyWorkspace : public Workspace<VBriey>{ +public: + BrieyWorkspace() : Workspace("Briey"){ + ClockDomain *axiClk = new ClockDomain(&top->io_axiClk,NULL,20000,100000); + ClockDomain *vgaClk = new ClockDomain(&top->io_vgaClk,NULL,40000,100000); + AsyncReset *asyncReset = new AsyncReset(&top->io_asyncReset,50000); + Jtag *jtag = new Jtag(&top->io_jtag_tms,&top->io_jtag_tdi,&top->io_jtag_tdo,&top->io_jtag_tck,80000); + UartRx *uartRx = new UartRx(&top->io_uart_txd,1.0e12/115200); + timeProcesses.push_back(axiClk); + timeProcesses.push_back(vgaClk); + timeProcesses.push_back(asyncReset); + timeProcesses.push_back(jtag); + timeProcesses.push_back(uartRx); + top->io_uart_rxd = 1; + + + SdramConfig *sdramConfig = new SdramConfig( + 2, //byteCount + 4, //bankCount + 1 << 13, //rowSize + 1 << 10 //colSize + ); + SdramIo *sdramIo = new SdramIo(); + sdramIo->BA = &top->io_sdram_BA ; + sdramIo->DQM = &top->io_sdram_DQM ; + sdramIo->CASn = &top->io_sdram_CASn ; + sdramIo->CKE = &top->io_sdram_CKE ; + sdramIo->CSn = &top->io_sdram_CSn ; + sdramIo->RASn = &top->io_sdram_RASn ; + sdramIo->WEn = &top->io_sdram_WEn ; + sdramIo->ADDR = &top->io_sdram_ADDR ; + sdramIo->DQ_read = (CData*)&top->io_sdram_DQ_read ; + sdramIo->DQ_write = (CData*)&top->io_sdram_DQ_write ; + sdramIo->DQ_writeEnable = (CData*)&top->io_sdram_DQ_writeEnable; + Sdram *sdram = new Sdram(sdramConfig, sdramIo); + + axiClk->add(sdram); + #ifdef TRACE + //speedFactor = 100e-6; + //cout << "Simulation caped to " << timeToSec << " of real time"<< endl; + #endif + + axiClk->add(new VexRiscvTracer(top->Briey->axi_core_cpu)); + + #ifdef VGA + Vga *vga = new Vga(top,640,480); + vgaClk->add(vga); + #endif + + top->io_coreInterrupt = 0; + } + + + /*bool trigged = false; + uint32_t frameStartCounter = 0; + virtual void dump(uint64_t i){ + if(!trigged) { + if(top->Briey->axi_vgaCtrl->vga_ctrl->io_frameStart) { + frameStartCounter++; + if(frameStartCounter < 3*32) cout << "**\n" << endl; + } + if(top->Briey->axi_vgaCtrl->vga_ctrl->io_error && frameStartCounter > 3*32) trigged = true; + } + if(trigged)Workspace::dump(i); + }*/ + + +}; + + +struct timespec timer_start(){ + struct timespec start_time; + clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &start_time); + return start_time; +} + +long timer_end(struct timespec start_time){ + struct timespec end_time; + clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &end_time); + uint64_t diffInNanos = end_time.tv_sec*1e9 + end_time.tv_nsec - start_time.tv_sec*1e9 - start_time.tv_nsec; + return diffInNanos; +} + + + +int main(int argc, char **argv, char **env) { + + Verilated::randReset(2); + Verilated::commandArgs(argc, argv); + + printf("BOOT\n"); + timespec startedAt = timer_start(); + + BrieyWorkspace().run(1e9); + + uint64_t duration = timer_end(startedAt); + cout << endl << "****************************************************************" << endl; + + + exit(0); +} diff --git a/VexRiscv/src/test/cpp/briey/makefile b/VexRiscv/src/test/cpp/briey/makefile new file mode 100644 index 0000000..e0a024b --- /dev/null +++ b/VexRiscv/src/test/cpp/briey/makefile @@ -0,0 +1,59 @@ +DEBUG?=no +TRACE?=no +TRACE_INSTRUCTION?=no +TRACE_REG?=no +PRINT_PERF?=no +VGA?=yes +TRACE_START=0 +ADDCFLAGS += -CFLAGS -pthread +ADDCFLAGS += -CFLAGS -lSDL2 +ADDCFLAGS += -LDFLAGS -lSDL2 + + + +ifeq ($(TRACE),yes) + VERILATOR_ARGS += --trace + ADDCFLAGS += -CFLAGS -DTRACE --trace-fst +endif +ifeq ($(DEBUG),yes) + ADDCFLAGS += -CFLAGS "-g3 -O0" +endif +ifneq ($(DEBUG),yes) + ADDCFLAGS += -CFLAGS "-O3" +endif +ifeq ($(PRINT_PERF),yes) + ADDCFLAGS += -CFLAGS -DPRINT_PERF +endif + +ifeq ($(VGA),yes) + ADDCFLAGS += -CFLAGS -DVGA +endif +ifeq ($(TRACE_INSTRUCTION),yes) + ADDCFLAGS += -CFLAGS -DTRACE_INSTRUCTION +endif + +ifeq ($(TRACE_REG),yes) + ADDCFLAGS += -CFLAGS -DTRACE_REG +endif + +ADDCFLAGS += -CFLAGS -DTRACE_START=${TRACE_START} + + + +all: clean compile + +run: compile + ./obj_dir/VBriey + +verilate: ../../../../Briey.v + rm -f Briey.v*.bin + cp ../../../../Briey.v*.bin . | true + verilator -cc ../../../../Briey.v -CFLAGS -std=c++11 ${ADDCFLAGS} --gdbbt ${VERILATOR_ARGS} -Wno-WIDTH -Wno-UNOPTFLAT --x-assign unique --exe main.cpp + +compile: verilate + make -j -C obj_dir/ -f VBriey.mk VBriey + +clean: + rm -f Briey.v*.bin + rm -rf obj_dir + diff --git a/VexRiscv/src/test/cpp/briey/sdram.gtkw b/VexRiscv/src/test/cpp/briey/sdram.gtkw new file mode 100644 index 0000000..e3fcbc8 --- /dev/null +++ b/VexRiscv/src/test/cpp/briey/sdram.gtkw @@ -0,0 +1,115 @@ +[*] +[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI +[*] Wed Jun 7 01:18:28 2017 +[*] +[dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/briey/Briey.vcd" +[dumpfile_mtime] "Wed Jun 7 01:17:07 2017" +[dumpfile_size] 1021433582 +[savefile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/briey/sdram.gtkw" +[timestart] 20762992700 +[size] 1776 953 +[pos] -1 -353 +*-16.000000 20763117800 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] TOP. +[treeopen] TOP.Briey. +[treeopen] TOP.Briey.axi_jtagCtrl. +[treeopen] TOP.Briey.axi_sdramCtrl. +[sst_width] 325 +[signals_width] 456 +[sst_expanded] 1 +[sst_vpaned_height] 503 +@28 +TOP.Briey.axi_core_cpu.DebugPlugin_haltIt +TOP.Briey.axi_sdramCtrl.io_sdram_BA[1:0] +TOP.Briey.axi_sdramCtrl.io_sdram_CKE +TOP.Briey.axi_sdramCtrl.io_sdram_CSn +TOP.Briey.axi_sdramCtrl.io_sdram_DQM[1:0] +@22 +TOP.Briey.axi_sdramCtrl.io_sdram_DQ_read[15:0] +@28 +TOP.Briey.axi_sdramCtrl.io_sdram_DQ_writeEnable +@22 +TOP.Briey.axi_sdramCtrl.io_sdram_DQ_write[15:0] +@28 +TOP.Briey.axi_sdramCtrl.io_sdram_RASn +TOP.Briey.axi_sdramCtrl.io_sdram_CASn +TOP.Briey.axi_sdramCtrl.io_sdram_WEn +@24 +TOP.Briey.axi_sdramCtrl.io_sdram_ADDR[12:0] +@22 +TOP.Briey.axi_sdramCtrl.ctrl.io_bus_cmd_payload_context_id[3:0] +@28 +TOP.Briey.axi_sdramCtrl.ctrl.io_bus_cmd_payload_context_last +@22 +TOP.Briey.axi_sdramCtrl.ctrl.io_bus_cmd_payload_data[15:0] +@28 +TOP.Briey.axi_sdramCtrl.ctrl.io_bus_cmd_payload_mask[1:0] +TOP.Briey.axi_sdramCtrl.ctrl.io_bus_cmd_valid +TOP.Briey.axi_sdramCtrl.ctrl.io_bus_cmd_ready +@22 +TOP.Briey.axi_sdramCtrl.ctrl.io_bus_cmd_payload_address[24:0] +@28 +TOP.Briey.axi_sdramCtrl.ctrl.io_bus_cmd_payload_write +@22 +TOP.Briey.axi_sdramCtrl.ctrl.io_bus_rsp_payload_context_id[3:0] +@28 +TOP.Briey.axi_sdramCtrl.ctrl.io_bus_rsp_payload_context_last +@22 +TOP.Briey.axi_sdramCtrl.ctrl.io_bus_rsp_payload_data[15:0] +@28 +TOP.Briey.axi_sdramCtrl.ctrl.io_bus_rsp_ready +TOP.Briey.axi_sdramCtrl.ctrl.io_bus_rsp_valid +TOP.Briey.axi_core_cpu.DebugPlugin_haltIt +TOP.Briey.axi_core_cpu.DebugPlugin_haltedByBreak +TOP.Briey.axi_core_cpu.DebugPlugin_isPipBusy +TOP.Briey.axi_core_cpu.DebugPlugin_resetIt +TOP.Briey.axi_core_cpu.DebugPlugin_stepIt +TOP.Briey.axi_core_cpu.DebugPlugin_insertDecodeInstruction +@22 +TOP.Briey.axi_jtagCtrl.debugger.io_mem_cmd_payload_address[31:0] +TOP.Briey.axi_jtagCtrl.debugger.io_mem_cmd_payload_data[31:0] +@28 +TOP.Briey.axi_jtagCtrl.debugger.io_mem_cmd_payload_size[1:0] +TOP.Briey.axi_jtagCtrl.debugger.io_mem_cmd_payload_wr +@29 +TOP.Briey.axi_jtagCtrl.debugger.io_mem_cmd_ready +@28 +TOP.Briey.axi_jtagCtrl.debugger.io_mem_cmd_valid +@22 +TOP.Briey.axi_jtagCtrl.debugger.io_mem_rsp_payload[31:0] +@28 +TOP.Briey.axi_jtagCtrl.debugger.io_mem_rsp_valid +@22 +TOP.Briey.axi_core_cpu.prefetch_PC[31:0] +TOP.Briey.axi_core_cpu.execute_PC[31:0] +@28 +TOP.Briey.axi_core_cpu.execute_IS_EBREAK +TOP.Briey.axi_core_cpu.execute_arbitration_isValid +@22 +TOP.Briey.axi_core_cpu.DebugPlugin_busReadDataReg[31:0] +@28 +TOP.Briey.axi_core_cpu.writeBack_arbitration_isValid +@22 +TOP.Briey.axi_core_cpu.writeBack_REGFILE_WRITE_DATA[31:0] +TOP.Briey.axi_core_cpu.writeBack_PC[31:0] +TOP.Briey.axi_core_cpu.execute_REGFILE_WRITE_DATA[31:0] +TOP.Briey.axi_core_cpu.execute_SRC1[31:0] +TOP.Briey.axi_core_cpu.execute_SRC2[31:0] +TOP.Briey.axi_core_cpu.decode_SRC1[31:0] +@28 +TOP.Briey.axi_core_cpu.decode_SRC1_CTRL[1:0] +@22 +TOP.Briey.axi_core_cpu.decode_SRC2[31:0] +@28 +TOP.Briey.axi_core_cpu.decode_SRC2_CTRL[1:0] +@22 +TOP.Briey.axi_core_cpu.decode_REG1[31:0] +TOP.Briey.axi_core_cpu.RegFilePlugin_regFile(0)[31:0] +TOP.Briey.axi_core_cpu.decode_RegFilePlugin_regFileReadAddress1[4:0] +@28 +TOP.Briey.axi_core_cpu.decode_IS_EBREAK +TOP.Briey.axi_core_cpu.decode_arbitration_isValid +@22 +TOP.Briey.axi_core_cpu.decode_INSTRUCTION[31:0] +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/VexRiscv/src/test/cpp/briey/wip.gtkw b/VexRiscv/src/test/cpp/briey/wip.gtkw new file mode 100644 index 0000000..b26d6e2 --- /dev/null +++ b/VexRiscv/src/test/cpp/briey/wip.gtkw @@ -0,0 +1,30 @@ +[*] +[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI +[*] Sun Jul 9 22:38:21 2017 +[*] +[dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/briey/Briey.vcd" +[dumpfile_mtime] "Sun Jul 9 22:38:03 2017" +[dumpfile_size] 1880556694 +[savefile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/briey/wip.gtkw" +[timestart] 225385490000 +[size] 1776 953 +[pos] -775 -1 +*-24.000000 225374620001 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] TOP. +[treeopen] TOP.Briey. +[treeopen] TOP.Briey.axi_vgaCtrl. +[sst_width] 358 +[signals_width] 150 +[sst_expanded] 1 +[sst_vpaned_height] 279 +@28 +TOP.Briey.axi_vgaCtrl.vga_ctrl.io_frameStart +TOP.Briey.axi_vgaCtrl.vga_ctrl.io_pixels_ready +TOP.Briey.axi_vgaCtrl.vga_ctrl.io_pixels_valid +TOP.Briey.axi_vgaCtrl.vga_ctrl.io_softReset +TOP.Briey.axi_vgaCtrl.vga_ctrl.io_vgaClk +TOP.Briey.axi_vgaCtrl.vga_ctrl.io_vga_colorEn +@29 +TOP.Briey.axi_vgaCtrl.vga_run +[pattern_trace] 1 +[pattern_trace] 0 |