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Diffstat (limited to 'VexRiscv/src/test/cpp/custom/atomic')
-rw-r--r--VexRiscv/src/test/cpp/custom/atomic/build/atomic.asm246
-rwxr-xr-xVexRiscv/src/test/cpp/custom/atomic/build/atomic.elfbin0 -> 5460 bytes
-rw-r--r--VexRiscv/src/test/cpp/custom/atomic/build/atomic.hex59
-rw-r--r--VexRiscv/src/test/cpp/custom/atomic/build/atomic.map31
-rwxr-xr-xVexRiscv/src/test/cpp/custom/atomic/build/atomic.v58
-rw-r--r--VexRiscv/src/test/cpp/custom/atomic/makefile73
-rw-r--r--VexRiscv/src/test/cpp/custom/atomic/src/crt.S265
-rw-r--r--VexRiscv/src/test/cpp/custom/atomic/src/ld17
8 files changed, 749 insertions, 0 deletions
diff --git a/VexRiscv/src/test/cpp/custom/atomic/build/atomic.asm b/VexRiscv/src/test/cpp/custom/atomic/build/atomic.asm
new file mode 100644
index 0000000..b2e9937
--- /dev/null
+++ b/VexRiscv/src/test/cpp/custom/atomic/build/atomic.asm
@@ -0,0 +1,246 @@
+
+build/atomic.elf: file format elf32-littleriscv
+
+
+Disassembly of section .crt_section:
+
+00000000 <trap_entry-0x20>:
+ 0: 04c0006f j 4c <_start>
+ 4: 00000013 nop
+ 8: 00000013 nop
+ c: 00000013 nop
+ 10: 00000013 nop
+ 14: 00000013 nop
+ 18: 00000013 nop
+ 1c: 00000013 nop
+
+00000020 <trap_entry>:
+ 20: 30002ef3 csrr t4,mstatus
+ 24: 080efe93 andi t4,t4,128
+ 28: 000e8a63 beqz t4,3c <notExternalInterrupt>
+ 2c: 00002eb7 lui t4,0x2
+ 30: 800e8e93 addi t4,t4,-2048 # 1800 <pass+0x1498>
+ 34: 300e9073 csrw mstatus,t4
+ 38: 30200073 mret
+
+0000003c <notExternalInterrupt>:
+ 3c: 34102ef3 csrr t4,mepc
+ 40: 004e8e93 addi t4,t4,4
+ 44: 341e9073 csrw mepc,t4
+ 48: 30200073 mret
+
+0000004c <_start>:
+ 4c: 00100e13 li t3,1
+ 50: 10000537 lui a0,0x10000
+ 54: 06400593 li a1,100
+ 58: 06500613 li a2,101
+ 5c: 06600693 li a3,102
+ 60: 00d52023 sw a3,0(a0) # 10000000 <pass+0xffffc98>
+ 64: 18b5262f sc.w a2,a1,(a0)
+ 68: 00100713 li a4,1
+ 6c: 2ee61863 bne a2,a4,35c <fail>
+ 70: 00052703 lw a4,0(a0)
+ 74: 2ee69463 bne a3,a4,35c <fail>
+ 78: 00200e13 li t3,2
+ 7c: 10000537 lui a0,0x10000
+ 80: 00450513 addi a0,a0,4 # 10000004 <pass+0xffffc9c>
+ 84: 06700593 li a1,103
+ 88: 06800613 li a2,104
+ 8c: 06900693 li a3,105
+ 90: 00d52023 sw a3,0(a0)
+ 94: 18b5262f sc.w a2,a1,(a0)
+ 98: 00100713 li a4,1
+ 9c: 2ce61063 bne a2,a4,35c <fail>
+ a0: 00052703 lw a4,0(a0)
+ a4: 2ae69c63 bne a3,a4,35c <fail>
+ a8: 00300e13 li t3,3
+ ac: 10000537 lui a0,0x10000
+ b0: 00450513 addi a0,a0,4 # 10000004 <pass+0xffffc9c>
+ b4: 06700593 li a1,103
+ b8: 06800613 li a2,104
+ bc: 06900693 li a3,105
+ c0: 18b5262f sc.w a2,a1,(a0)
+ c4: 00100713 li a4,1
+ c8: 28e61a63 bne a2,a4,35c <fail>
+ cc: 00052703 lw a4,0(a0)
+ d0: 28e69663 bne a3,a4,35c <fail>
+ d4: 00400e13 li t3,4
+ d8: 10000537 lui a0,0x10000
+ dc: 00850513 addi a0,a0,8 # 10000008 <pass+0xffffca0>
+ e0: 06a00593 li a1,106
+ e4: 06b00613 li a2,107
+ e8: 06c00693 li a3,108
+ ec: 00d52023 sw a3,0(a0)
+ f0: 100527af lr.w a5,(a0)
+ f4: 18b5262f sc.w a2,a1,(a0)
+ f8: 26d79263 bne a5,a3,35c <fail>
+ fc: 26061063 bnez a2,35c <fail>
+ 100: 00052703 lw a4,0(a0)
+ 104: 24e59c63 bne a1,a4,35c <fail>
+ 108: 00500e13 li t3,5
+ 10c: 10000537 lui a0,0x10000
+ 110: 00850513 addi a0,a0,8 # 10000008 <pass+0xffffca0>
+ 114: 06d00593 li a1,109
+ 118: 06e00613 li a2,110
+ 11c: 06f00693 li a3,111
+ 120: 00d52023 sw a3,0(a0)
+ 124: 18b5262f sc.w a2,a1,(a0)
+ 128: 22061a63 bnez a2,35c <fail>
+ 12c: 00052703 lw a4,0(a0)
+ 130: 22e59663 bne a1,a4,35c <fail>
+ 134: 00600e13 li t3,6
+ 138: 10000537 lui a0,0x10000
+ 13c: 00c50513 addi a0,a0,12 # 1000000c <pass+0xffffca4>
+ 140: 07000593 li a1,112
+ 144: 07100613 li a2,113
+ 148: 07200693 li a3,114
+ 14c: 10000437 lui s0,0x10000
+ 150: 01040413 addi s0,s0,16 # 10000010 <pass+0xffffca8>
+ 154: 07300493 li s1,115
+ 158: 07400913 li s2,116
+ 15c: 07500993 li s3,117
+ 160: 00d52023 sw a3,0(a0)
+ 164: 01342023 sw s3,0(s0)
+ 168: 100527af lr.w a5,(a0)
+ 16c: 10042aaf lr.w s5,(s0)
+ 170: 18b5262f sc.w a2,a1,(a0)
+ 174: 1894292f sc.w s2,s1,(s0)
+ 178: 1ed79263 bne a5,a3,35c <fail>
+ 17c: 1e061063 bnez a2,35c <fail>
+ 180: 00052703 lw a4,0(a0)
+ 184: 1ce59c63 bne a1,a4,35c <fail>
+ 188: 1d3a9a63 bne s5,s3,35c <fail>
+ 18c: 1c091863 bnez s2,35c <fail>
+ 190: 00042a03 lw s4,0(s0)
+ 194: 1d449463 bne s1,s4,35c <fail>
+ 198: 00700e13 li t3,7
+ 19c: 10000537 lui a0,0x10000
+ 1a0: 01450513 addi a0,a0,20 # 10000014 <pass+0xffffcac>
+ 1a4: 07800593 li a1,120
+ 1a8: 07900613 li a2,121
+ 1ac: 07a00693 li a3,122
+ 1b0: 01000e93 li t4,16
+
+000001b4 <test7>:
+ 1b4: 00d52023 sw a3,0(a0)
+ 1b8: 100527af lr.w a5,(a0)
+ 1bc: 18b5262f sc.w a2,a1,(a0)
+ 1c0: 18d79e63 bne a5,a3,35c <fail>
+ 1c4: 18061c63 bnez a2,35c <fail>
+ 1c8: 00052703 lw a4,0(a0)
+ 1cc: 18e59863 bne a1,a4,35c <fail>
+ 1d0: fffe8e93 addi t4,t4,-1
+ 1d4: 00450513 addi a0,a0,4
+ 1d8: 00358593 addi a1,a1,3
+ 1dc: 00360613 addi a2,a2,3
+ 1e0: 00368693 addi a3,a3,3
+ 1e4: fc0e98e3 bnez t4,1b4 <test7>
+ 1e8: 00800e13 li t3,8
+ 1ec: 10000537 lui a0,0x10000
+ 1f0: 01850513 addi a0,a0,24 # 10000018 <pass+0xffffcb0>
+ 1f4: 07800593 li a1,120
+ 1f8: 07900613 li a2,121
+ 1fc: 07a00693 li a3,122
+ 200: 00052783 lw a5,0(a0)
+ 204: 18b5262f sc.w a2,a1,(a0)
+ 208: 00100713 li a4,1
+ 20c: 14e61863 bne a2,a4,35c <fail>
+ 210: 00052703 lw a4,0(a0)
+ 214: 14e79463 bne a5,a4,35c <fail>
+ 218: 00900e13 li t3,9
+ 21c: 10000537 lui a0,0x10000
+ 220: 10050513 addi a0,a0,256 # 10000100 <pass+0xffffd98>
+ 224: 07b00593 li a1,123
+ 228: 07c00613 li a2,124
+ 22c: 07d00693 li a3,125
+ 230: 00d52023 sw a3,0(a0)
+ 234: 100527af lr.w a5,(a0)
+ 238: 00000073 ecall
+ 23c: 18b5262f sc.w a2,a1,(a0)
+ 240: 00100713 li a4,1
+ 244: 10e61c63 bne a2,a4,35c <fail>
+ 248: 00052703 lw a4,0(a0)
+ 24c: 10e69863 bne a3,a4,35c <fail>
+ 250: 00a00e13 li t3,10
+ 254: 10000537 lui a0,0x10000
+ 258: 20050513 addi a0,a0,512 # 10000200 <pass+0xffffe98>
+ 25c: 10000837 lui a6,0x10000
+ 260: 20480813 addi a6,a6,516 # 10000204 <pass+0xffffe9c>
+ 264: 07e00593 li a1,126
+ 268: 07f00613 li a2,127
+ 26c: 08000693 li a3,128
+ 270: 08100893 li a7,129
+ 274: 00d52023 sw a3,0(a0)
+ 278: 01182023 sw a7,0(a6)
+ 27c: 100827af lr.w a5,(a6)
+ 280: 18b5262f sc.w a2,a1,(a0)
+ 284: 00100713 li a4,1
+ 288: 0ce61a63 bne a2,a4,35c <fail>
+ 28c: 00082703 lw a4,0(a6)
+ 290: 0ce89663 bne a7,a4,35c <fail>
+ 294: 00b00e13 li t3,11
+ 298: 10000537 lui a0,0x10000
+ 29c: 30050513 addi a0,a0,768 # 10000300 <pass+0xfffff98>
+ 2a0: 08200593 li a1,130
+ 2a4: 08300613 li a2,131
+ 2a8: 08400693 li a3,132
+ 2ac: 00d52023 sw a3,0(a0)
+ 2b0: 00001eb7 lui t4,0x1
+ 2b4: 800e8e93 addi t4,t4,-2048 # 800 <pass+0x498>
+ 2b8: 304e9073 csrw mie,t4
+ 2bc: 00800e93 li t4,8
+ 2c0: 100527af lr.w a5,(a0)
+ 2c4: 300e9073 csrw mstatus,t4
+ 2c8: 00000013 nop
+ 2cc: 00000013 nop
+ 2d0: 00000013 nop
+ 2d4: 00000013 nop
+ 2d8: 00000013 nop
+ 2dc: 00000013 nop
+ 2e0: 18b5262f sc.w a2,a1,(a0)
+ 2e4: 00100713 li a4,1
+ 2e8: 06e61a63 bne a2,a4,35c <fail>
+ 2ec: 00052703 lw a4,0(a0)
+ 2f0: 06e69663 bne a3,a4,35c <fail>
+ 2f4: 00c00e13 li t3,12
+ 2f8: 10000537 lui a0,0x10000
+ 2fc: 40050513 addi a0,a0,1024 # 10000400 <pass+0x10000098>
+ 300: 08c00593 li a1,140
+ 304: 08d00613 li a2,141
+ 308: 08e00693 li a3,142
+ 30c: 00d52023 sw a3,0(a0)
+ 310: 00001eb7 lui t4,0x1
+ 314: 800e8e93 addi t4,t4,-2048 # 800 <pass+0x498>
+ 318: 304e9073 csrw mie,t4
+ 31c: 00002eb7 lui t4,0x2
+ 320: 808e8e93 addi t4,t4,-2040 # 1808 <pass+0x14a0>
+ 324: 100527af lr.w a5,(a0)
+ 328: 300e9073 csrw mstatus,t4
+ 32c: 00000013 nop
+ 330: 00000013 nop
+ 334: 00000013 nop
+ 338: 00000013 nop
+ 33c: 00000013 nop
+ 340: 00000013 nop
+ 344: 18b5262f sc.w a2,a1,(a0)
+ 348: 00100713 li a4,1
+ 34c: 00e61863 bne a2,a4,35c <fail>
+ 350: 00052703 lw a4,0(a0)
+ 354: 00e69463 bne a3,a4,35c <fail>
+ 358: 0100006f j 368 <pass>
+
+0000035c <fail>:
+ 35c: f0100137 lui sp,0xf0100
+ 360: f2410113 addi sp,sp,-220 # f00fff24 <pass+0xf00ffbbc>
+ 364: 01c12023 sw t3,0(sp)
+
+00000368 <pass>:
+ 368: f0100137 lui sp,0xf0100
+ 36c: f2010113 addi sp,sp,-224 # f00fff20 <pass+0xf00ffbb8>
+ 370: 00012023 sw zero,0(sp)
+ 374: 00000013 nop
+ 378: 00000013 nop
+ 37c: 00000013 nop
+ 380: 00000013 nop
+ 384: 00000013 nop
+ 388: 00000013 nop
diff --git a/VexRiscv/src/test/cpp/custom/atomic/build/atomic.elf b/VexRiscv/src/test/cpp/custom/atomic/build/atomic.elf
new file mode 100755
index 0000000..a67f244
--- /dev/null
+++ b/VexRiscv/src/test/cpp/custom/atomic/build/atomic.elf
Binary files differ
diff --git a/VexRiscv/src/test/cpp/custom/atomic/build/atomic.hex b/VexRiscv/src/test/cpp/custom/atomic/build/atomic.hex
new file mode 100644
index 0000000..593eef7
--- /dev/null
+++ b/VexRiscv/src/test/cpp/custom/atomic/build/atomic.hex
@@ -0,0 +1,59 @@
+:100000006F00C00413000000130000001300000084
+:100010001300000013000000130000001300000094
+:10002000F32E003093FE0E08638A0E00B72E0000F8
+:10003000938E0E8073900E3073002030F32E1034A8
+:10004000938E4E0073901E3473002030130E1000F8
+:100050003705001093054006130650069306600608
+:100060002320D5002F26B518130710006318E62E9D
+:10007000032705006394E62E130E200037050010B9
+:100080001305450093057006130680069306900637
+:100090002320D5002F26B518130710006310E62C77
+:1000A00003270500639CE62A130E30003705001075
+:1000B0001305450093057006130680069306900607
+:1000C0002F26B51813071000631AE628032705002A
+:1000D0006396E628130E40003705001013058500CF
+:1000E0009305A0061306B0069306C0062320D5008C
+:1000F000AF2705102F26B5186392D7266310062662
+:1001000003270500639CE524130E500037050010FB
+:10011000130585009305D0061306E0069306F00646
+:100120002320D5002F26B518631A062203270500C1
+:100130006396E522130E6000370500101305C50015
+:1001400093050007130610079306200737040010D5
+:10015000130404019304300713094007930950075F
+:100160002320D50023203401AF270510AF2A041027
+:100170002F26B5182F2994186392D71E6310061ED8
+:1001800003270500639CE51C639A3A1D6318091C4C
+:10019000032A04006394441D130E700037050010F9
+:1001A0001305450193058007130690079306A007E2
+:1001B000930E00012320D500AF2705102F26B51878
+:1001C000639ED718631C0618032705006398E5187B
+:1001D000938EFEFF13054500938535001306360008
+:1001E00093863600E3980EFC130E8000370500104E
+:1001F0001305850193058007130690079306A00752
+:10020000832705002F26B518130710006318E6147E
+:10021000032705006394E714130E900037050010C0
+:10022000130505109305B0071306C0079306D00702
+:100230002320D500AF270510730000002F26B51826
+:1002400013071000631CE610032705006398E610EF
+:10025000130EA00037050010130505203708001005
+:10026000130848209305E0071306F00793060008DB
+:10027000930810082320D50023201801AF27081069
+:100280002F26B51813071000631AE60C0327080081
+:100290006396E80C130EB000370500101305053007
+:1002A0009305200813063008930640082320D50044
+:1002B000B71E0000938E0E8073904E30930E800018
+:1002C000AF27051073900E301300000013000000DC
+:1002D00013000000130000001300000013000000D2
+:1002E0002F26B51813071000631AE606032705002A
+:1002F0006396E606130EC00037050010130505408F
+:100300009305C0081306D0089306E0082320D50003
+:10031000B71E0000938E0E8073904E30B72E0000F3
+:10032000938E8E80AF27051073900E30130000005F
+:100330001300000013000000130000001300000071
+:10034000130000002F26B518130710006318E600ED
+:10035000032705006394E6006F000001370110F0E9
+:10036000130141F22320C101370110F0130101F202
+:100370002320010013000000130000001300000000
+:0C03800013000000130000001300000038
+:040000030000004CAD
+:00000001FF
diff --git a/VexRiscv/src/test/cpp/custom/atomic/build/atomic.map b/VexRiscv/src/test/cpp/custom/atomic/build/atomic.map
new file mode 100644
index 0000000..5c6ed9f
--- /dev/null
+++ b/VexRiscv/src/test/cpp/custom/atomic/build/atomic.map
@@ -0,0 +1,31 @@
+
+Memory Configuration
+
+Name Origin Length Attributes
+onChipRam 0x0000000000000000 0x0000000000002000 w !xr
+*default* 0x0000000000000000 0xffffffffffffffff
+
+Linker script and memory map
+
+LOAD build/src/crt.o
+LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.1.1/libgcc.a
+START GROUP
+LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.1.1/../../../../riscv64-unknown-elf/lib/libc.a
+LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.1.1/../../../../riscv64-unknown-elf/lib/libgloss.a
+END GROUP
+LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.1.1/libgcc.a
+ 0x0000000000000000 . = 0x0
+
+.crt_section 0x0000000000000000 0x38c
+ 0x0000000000000000 . = ALIGN (0x4)
+ *crt.o(.text)
+ .text 0x0000000000000000 0x38c build/src/crt.o
+ 0x0000000000000020 trap_entry
+ 0x000000000000004c _start
+OUTPUT(build/atomic.elf elf32-littleriscv)
+
+.data 0x000000000000038c 0x0
+ .data 0x000000000000038c 0x0 build/src/crt.o
+
+.bss 0x000000000000038c 0x0
+ .bss 0x000000000000038c 0x0 build/src/crt.o
diff --git a/VexRiscv/src/test/cpp/custom/atomic/build/atomic.v b/VexRiscv/src/test/cpp/custom/atomic/build/atomic.v
new file mode 100755
index 0000000..1d8d7a8
--- /dev/null
+++ b/VexRiscv/src/test/cpp/custom/atomic/build/atomic.v
@@ -0,0 +1,58 @@
+@00000000
+6F 00 C0 04 13 00 00 00 13 00 00 00 13 00 00 00
+13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00
+F3 2E 00 30 93 FE 0E 08 63 8A 0E 00 B7 2E 00 00
+93 8E 0E 80 73 90 0E 30 73 00 20 30 F3 2E 10 34
+93 8E 4E 00 73 90 1E 34 73 00 20 30 13 0E 10 00
+37 05 00 10 93 05 40 06 13 06 50 06 93 06 60 06
+23 20 D5 00 2F 26 B5 18 13 07 10 00 63 18 E6 2E
+03 27 05 00 63 94 E6 2E 13 0E 20 00 37 05 00 10
+13 05 45 00 93 05 70 06 13 06 80 06 93 06 90 06
+23 20 D5 00 2F 26 B5 18 13 07 10 00 63 10 E6 2C
+03 27 05 00 63 9C E6 2A 13 0E 30 00 37 05 00 10
+13 05 45 00 93 05 70 06 13 06 80 06 93 06 90 06
+2F 26 B5 18 13 07 10 00 63 1A E6 28 03 27 05 00
+63 96 E6 28 13 0E 40 00 37 05 00 10 13 05 85 00
+93 05 A0 06 13 06 B0 06 93 06 C0 06 23 20 D5 00
+AF 27 05 10 2F 26 B5 18 63 92 D7 26 63 10 06 26
+03 27 05 00 63 9C E5 24 13 0E 50 00 37 05 00 10
+13 05 85 00 93 05 D0 06 13 06 E0 06 93 06 F0 06
+23 20 D5 00 2F 26 B5 18 63 1A 06 22 03 27 05 00
+63 96 E5 22 13 0E 60 00 37 05 00 10 13 05 C5 00
+93 05 00 07 13 06 10 07 93 06 20 07 37 04 00 10
+13 04 04 01 93 04 30 07 13 09 40 07 93 09 50 07
+23 20 D5 00 23 20 34 01 AF 27 05 10 AF 2A 04 10
+2F 26 B5 18 2F 29 94 18 63 92 D7 1E 63 10 06 1E
+03 27 05 00 63 9C E5 1C 63 9A 3A 1D 63 18 09 1C
+03 2A 04 00 63 94 44 1D 13 0E 70 00 37 05 00 10
+13 05 45 01 93 05 80 07 13 06 90 07 93 06 A0 07
+93 0E 00 01 23 20 D5 00 AF 27 05 10 2F 26 B5 18
+63 9E D7 18 63 1C 06 18 03 27 05 00 63 98 E5 18
+93 8E FE FF 13 05 45 00 93 85 35 00 13 06 36 00
+93 86 36 00 E3 98 0E FC 13 0E 80 00 37 05 00 10
+13 05 85 01 93 05 80 07 13 06 90 07 93 06 A0 07
+83 27 05 00 2F 26 B5 18 13 07 10 00 63 18 E6 14
+03 27 05 00 63 94 E7 14 13 0E 90 00 37 05 00 10
+13 05 05 10 93 05 B0 07 13 06 C0 07 93 06 D0 07
+23 20 D5 00 AF 27 05 10 73 00 00 00 2F 26 B5 18
+13 07 10 00 63 1C E6 10 03 27 05 00 63 98 E6 10
+13 0E A0 00 37 05 00 10 13 05 05 20 37 08 00 10
+13 08 48 20 93 05 E0 07 13 06 F0 07 93 06 00 08
+93 08 10 08 23 20 D5 00 23 20 18 01 AF 27 08 10
+2F 26 B5 18 13 07 10 00 63 1A E6 0C 03 27 08 00
+63 96 E8 0C 13 0E B0 00 37 05 00 10 13 05 05 30
+93 05 20 08 13 06 30 08 93 06 40 08 23 20 D5 00
+B7 1E 00 00 93 8E 0E 80 73 90 4E 30 93 0E 80 00
+AF 27 05 10 73 90 0E 30 13 00 00 00 13 00 00 00
+13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00
+2F 26 B5 18 13 07 10 00 63 1A E6 06 03 27 05 00
+63 96 E6 06 13 0E C0 00 37 05 00 10 13 05 05 40
+93 05 C0 08 13 06 D0 08 93 06 E0 08 23 20 D5 00
+B7 1E 00 00 93 8E 0E 80 73 90 4E 30 B7 2E 00 00
+93 8E 8E 80 AF 27 05 10 73 90 0E 30 13 00 00 00
+13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00
+13 00 00 00 2F 26 B5 18 13 07 10 00 63 18 E6 00
+03 27 05 00 63 94 E6 00 6F 00 00 01 37 01 10 F0
+13 01 41 F2 23 20 C1 01 37 01 10 F0 13 01 01 F2
+23 20 01 00 13 00 00 00 13 00 00 00 13 00 00 00
+13 00 00 00 13 00 00 00 13 00 00 00
diff --git a/VexRiscv/src/test/cpp/custom/atomic/makefile b/VexRiscv/src/test/cpp/custom/atomic/makefile
new file mode 100644
index 0000000..217a057
--- /dev/null
+++ b/VexRiscv/src/test/cpp/custom/atomic/makefile
@@ -0,0 +1,73 @@
+PROJ_NAME=atomic
+
+
+RISCV_PATH=/opt/riscv/
+CFLAGS += -march=rv32ia -mabi=ilp32
+RISCV_NAME = riscv64-unknown-elf
+RISCV_OBJCOPY = $(RISCV_PATH)/bin/$(RISCV_NAME)-objcopy
+RISCV_OBJDUMP = $(RISCV_PATH)/bin/$(RISCV_NAME)-objdump
+RISCV_CLIB=$(RISCV_PATH)$(RISCV_NAME)/lib/
+RISCV_CC=$(RISCV_PATH)/bin/$(RISCV_NAME)-gcc
+LDSCRIPT=src/ld
+
+
+SRCS = $(wildcard src/*.c) \
+ $(wildcard src/*.cpp) \
+ $(wildcard src/*.S)
+
+
+CFLAGS += -static
+LDFLAGS += -e_start -T $(LDSCRIPT) -nostartfiles -Wl,-Map,$(OBJDIR)/$(PROJ_NAME).map -Wl,--print-memory-usage
+OBJDIR = build
+OBJS := $(SRCS)
+OBJS := $(OBJS:.c=.o)
+OBJS := $(OBJS:.cpp=.o)
+OBJS := $(OBJS:.S=.o)
+OBJS := $(addprefix $(OBJDIR)/,$(OBJS))
+
+
+
+all: $(OBJDIR)/$(PROJ_NAME).elf $(OBJDIR)/$(PROJ_NAME).hex $(OBJDIR)/$(PROJ_NAME).asm $(OBJDIR)/$(PROJ_NAME).v
+ @echo "done"
+
+$(OBJDIR)/%.elf: $(OBJS) | $(OBJDIR)
+ $(RISCV_CC) $(CFLAGS) -o $@ $^ $(LDFLAGS) $(LIBS)
+
+%.hex: %.elf
+ $(RISCV_OBJCOPY) -O ihex $^ $@
+
+%.bin: %.elf
+ $(RISCV_OBJCOPY) -O binary $^ $@
+
+%.v: %.elf
+ $(RISCV_OBJCOPY) -O verilog $^ $@
+
+%.asm: %.elf
+ $(RISCV_OBJDUMP) -S -d $^ > $@
+
+$(OBJDIR)/%.o: %.c
+ mkdir -p $(dir $@)
+ $(RISCV_CC) -c $(CFLAGS) $(INC) -o $@ $^
+
+$(OBJDIR)/%.o: %.cpp
+ mkdir -p $(dir $@)
+ $(RISCV_CC) -c $(CFLAGS) $(INC) -o $@ $^
+
+$(OBJDIR)/%.o: %.S
+ mkdir -p $(dir $@)
+ $(RISCV_CC) -c $(CFLAGS) -o $@ $^ -D__ASSEMBLY__=1
+
+$(OBJDIR):
+ mkdir -p $@
+
+clean:
+ rm -f $(OBJDIR)/$(PROJ_NAME).elf
+ rm -f $(OBJDIR)/$(PROJ_NAME).hex
+ rm -f $(OBJDIR)/$(PROJ_NAME).map
+ rm -f $(OBJDIR)/$(PROJ_NAME).v
+ rm -f $(OBJDIR)/$(PROJ_NAME).asm
+ find $(OBJDIR) -type f -name '*.o' -print0 | xargs -0 -r rm
+
+.SECONDARY: $(OBJS)
+
+
diff --git a/VexRiscv/src/test/cpp/custom/atomic/src/crt.S b/VexRiscv/src/test/cpp/custom/atomic/src/crt.S
new file mode 100644
index 0000000..1462dd2
--- /dev/null
+++ b/VexRiscv/src/test/cpp/custom/atomic/src/crt.S
@@ -0,0 +1,265 @@
+.globl _start
+
+
+ j _start
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+
+.global trap_entry
+trap_entry:
+ csrr x29, mstatus
+ and x29, x29, 0x080
+ beqz x29, notExternalInterrupt
+ li x29, 0x1800 //000 disable interrupts
+ csrw mstatus,x29
+ mret
+
+notExternalInterrupt:
+ csrr x29, mepc
+ addi x29, x29, 4
+ csrw mepc, x29
+ mret
+
+_start:
+//Test 1 SC on unreserved area should fail and not write memory
+ li x28, 1
+ li a0, 0x10000000
+ li a1, 100
+ li a2, 101
+ li a3, 102
+ sw a3, 0(a0)
+ sc.w a2, a1, (a0)
+ li a4, 1
+ bne a2, a4, fail
+ lw a4, 0(a0)
+ bne a3, a4, fail
+
+//Test 2 SC on another unreserved area should fail and not write memory
+ li x28, 2
+ li a0, 0x10000004
+ li a1, 103
+ li a2, 104
+ li a3, 105
+ sw a3, 0(a0)
+ sc.w a2, a1, (a0)
+ li a4, 1
+ bne a2, a4, fail
+ lw a4, 0(a0)
+ bne a3, a4, fail
+
+
+//Test 3 retrying SC on unreserved area should fail and not write memory
+ li x28, 3
+ li a0, 0x10000004
+ li a1, 103
+ li a2, 104
+ li a3, 105
+ sc.w a2, a1, (a0)
+ li a4, 1
+ bne a2, a4, fail
+ lw a4, 0(a0)
+ bne a3, a4, fail
+
+
+//Test 4 SC on reserved area should pass and should be written write memory
+ li x28, 4
+ li a0, 0x10000008
+ li a1, 106
+ li a2, 107
+ li a3, 108
+ sw a3, 0(a0)
+ lr.w a5, (a0)
+ sc.w a2, a1, (a0)
+ bne a5, a3, fail
+ bne a2, x0, fail
+ lw a4, 0(a0)
+ bne a1, a4, fail
+
+
+//Test 5 redo SC on reserved area should pass and should be written write memory
+ li x28, 5
+ li a0, 0x10000008
+ li a1, 109
+ li a2, 110
+ li a3, 111
+ sw a3, 0(a0)
+ sc.w a2, a1, (a0)
+ bne a2, x0, fail
+ lw a4, 0(a0)
+ bne a1, a4, fail
+
+//Test 6 Allow two entries at the same time
+ li x28, 6
+ li a0, 0x1000000C
+ li a1, 112
+ li a2, 113
+ li a3, 114
+ li s0, 0x10000010
+ li s1, 115
+ li s2, 116
+ li s3, 117
+
+ sw a3, 0(a0)
+ sw s3, 0(s0)
+ lr.w a5, (a0)
+ lr.w s5, (s0)
+ sc.w a2, a1, (a0)
+ sc.w s2, s1, (s0)
+ bne a5, a3, fail
+ bne a2, x0, fail
+ lw a4, 0(a0)
+ bne a1, a4, fail
+
+ bne s5, s3, fail
+ bne s2, x0, fail
+ lw s4, 0(s0)
+ bne s1, s4, fail
+
+//Test 7 do a lot of allocation to clear the entries
+ li x28, 7
+ li a0, 0x10000014
+ li a1, 120
+ li a2, 121
+ li a3, 122
+ li x29, 16
+test7:
+ sw a3, 0(a0)
+ lr.w a5, (a0)
+ sc.w a2, a1, (a0)
+ bne a5, a3, fail
+ bne a2, x0, fail
+ lw a4, 0(a0)
+ bne a1, a4, fail
+ add x29, x29, -1
+ add a0, a0, 4
+ add a1, a1, 3
+ add a2, a2, 3
+ add a3, a3, 3
+ bnez x29, test7
+
+
+//Test 8 SC on discarded entries should fail
+ li x28, 8
+ li a0, 0x10000018
+ li a1, 120
+ li a2, 121
+ li a3, 122
+ lw a5, 0(a0)
+ sc.w a2, a1, (a0)
+ li a4, 1
+ bne a2, a4, fail
+ lw a4, 0(a0)
+ bne a5, a4, fail
+
+
+//Test 9 SC should fail after a context switching
+ li x28, 9
+ li a0, 0x10000100
+ li a1, 123
+ li a2, 124
+ li a3, 125
+ sw a3, 0(a0)
+ lr.w a5, (a0)
+ scall
+ sc.w a2, a1, (a0)
+ li a4, 1
+ bne a2, a4, fail
+ lw a4, 0(a0)
+ bne a3, a4, fail
+
+
+
+//Test 10 SC should fail if the address doesn't match
+ li x28, 10
+ li a0, 0x10000200
+ li a6, 0x10000204
+ li a1, 126
+ li a2, 127
+ li a3, 128
+ li a7, 129
+ sw a3, 0(a0)
+ sw a7, 0(a6)
+ lr.w a5, (a6)
+ sc.w a2, a1, (a0)
+ li a4, 1
+ bne a2, a4, fail
+ lw a4, 0(a6)
+ bne a7, a4, fail
+
+
+
+//Test 11 SC should fail after a external interrupt context switching
+ li x28, 11
+ li a0, 0x10000300
+ li a1, 130
+ li a2, 131
+ li a3, 132
+ sw a3, 0(a0)
+ li x29, 0x800 //800 external interrupts
+ csrw mie,x29
+ li x29, 0x008 //008 enable interrupts
+ lr.w a5, (a0)
+ csrw mstatus,x29 //Enable external interrupt (will jump instantly due to testbench setup)
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ sc.w a2, a1, (a0)
+ li a4, 1
+ bne a2, a4, fail
+ lw a4, 0(a0)
+ bne a3, a4, fail
+
+
+//Test 12 SC should fail after a external interrupt context switching (callback on lr)
+ li x28, 12
+ li a0, 0x10000400
+ li a1, 140
+ li a2, 141
+ li a3, 142
+ sw a3, 0(a0)
+ li x29, 0x800 //800 external interrupts
+ csrw mie,x29
+ li x29, 0x1808 //008 enable interrupts
+ lr.w a5, (a0)
+ csrw mstatus,x29 //Enable external interrupt (will jump instantly due to testbench setup)
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ sc.w a2, a1, (a0)
+ li a4, 1
+ bne a2, a4, fail
+ lw a4, 0(a0)
+ bne a3, a4, fail
+
+
+
+ j pass
+
+
+fail: //x28 => error code
+ li x2, 0xF00FFF24
+ sw x28, 0(x2)
+
+pass:
+ li x2, 0xF00FFF20
+ sw x0, 0(x2)
+
+
+
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
diff --git a/VexRiscv/src/test/cpp/custom/atomic/src/ld b/VexRiscv/src/test/cpp/custom/atomic/src/ld
new file mode 100644
index 0000000..8d95523
--- /dev/null
+++ b/VexRiscv/src/test/cpp/custom/atomic/src/ld
@@ -0,0 +1,17 @@
+OUTPUT_ARCH( "riscv" )
+
+MEMORY {
+ onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x00000000, LENGTH = 8K
+}
+
+SECTIONS
+{
+ . = 0x000;
+
+ .crt_section :
+ {
+ . = ALIGN(4);
+ *crt.o(.text)
+ } > onChipRam
+
+}
generated by cgit v1.2.3 (git 2.25.1) at 2025-10-23 19:34:31 +0000