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Diffstat (limited to 'VexRiscv/src/test/cpp/custom/custom_csr')
-rw-r--r--VexRiscv/src/test/cpp/custom/custom_csr/build/custom_csr.asm55
-rwxr-xr-xVexRiscv/src/test/cpp/custom/custom_csr/build/custom_csr.elfbin0 -> 4644 bytes
-rw-r--r--VexRiscv/src/test/cpp/custom/custom_csr/build/custom_csr.hex12
-rw-r--r--VexRiscv/src/test/cpp/custom/custom_csr/build/custom_csr.map30
-rwxr-xr-xVexRiscv/src/test/cpp/custom/custom_csr/build/custom_csr.v12
-rw-r--r--VexRiscv/src/test/cpp/custom/custom_csr/makefile73
-rw-r--r--VexRiscv/src/test/cpp/custom/custom_csr/src/crt.S64
-rw-r--r--VexRiscv/src/test/cpp/custom/custom_csr/src/ld17
8 files changed, 263 insertions, 0 deletions
diff --git a/VexRiscv/src/test/cpp/custom/custom_csr/build/custom_csr.asm b/VexRiscv/src/test/cpp/custom/custom_csr/build/custom_csr.asm
new file mode 100644
index 0000000..cf186d1
--- /dev/null
+++ b/VexRiscv/src/test/cpp/custom/custom_csr/build/custom_csr.asm
@@ -0,0 +1,55 @@
+
+build/custom_csr.elf: file format elf32-littleriscv
+
+
+Disassembly of section .crt_section:
+
+00000000 <_start>:
+ 0: 00100e13 li t3,1
+ 4: b04020f3 csrr ra,mhpmcounter4
+ 8: b0402173 csrr sp,mhpmcounter4
+ c: b04021f3 csrr gp,mhpmcounter4
+ 10: 06114863 blt sp,ra,80 <fail>
+ 14: 0621c663 blt gp,sp,80 <fail>
+ 18: 00200e13 li t3,2
+ 1c: 005dc0b7 lui ra,0x5dc
+ 20: 98a08093 addi ra,ra,-1654 # 5db98a <pass+0x5db8fe>
+ 24: b0409073 csrw mhpmcounter4,ra
+ 28: b0402173 csrr sp,mhpmcounter4
+ 2c: 04114a63 blt sp,ra,80 <fail>
+ 30: 00300e13 li t3,3
+ 34: b05020f3 csrr ra,mhpmcounter5
+ 38: b0502173 csrr sp,mhpmcounter5
+ 3c: b05021f3 csrr gp,mhpmcounter5
+ 40: 0420d063 ble sp,ra,80 <fail>
+ 44: 02315e63 ble gp,sp,80 <fail>
+ 48: 00400e13 li t3,4
+ 4c: b0609073 csrw mhpmcounter6,ra
+ 50: b04020f3 csrr ra,mhpmcounter4
+ 54: 10000113 li sp,256
+ 58: 0220f463 bleu sp,ra,80 <fail>
+ 5c: 00500e13 li t3,5
+ 60: b07020f3 csrr ra,mhpmcounter7
+ 64: b04020f3 csrr ra,mhpmcounter4
+ 68: 40000137 lui sp,0x40000
+ 6c: 10010113 addi sp,sp,256 # 40000100 <pass+0x40000074>
+ 70: 400001b7 lui gp,0x40000
+ 74: 0020f663 bleu sp,ra,80 <fail>
+ 78: 0030e463 bltu ra,gp,80 <fail>
+ 7c: 0100006f j 8c <pass>
+
+00000080 <fail>:
+ 80: f0100137 lui sp,0xf0100
+ 84: f2410113 addi sp,sp,-220 # f00fff24 <pass+0xf00ffe98>
+ 88: 01c12023 sw t3,0(sp)
+
+0000008c <pass>:
+ 8c: f0100137 lui sp,0xf0100
+ 90: f2010113 addi sp,sp,-224 # f00fff20 <pass+0xf00ffe94>
+ 94: 00012023 sw zero,0(sp)
+ 98: 00000013 nop
+ 9c: 00000013 nop
+ a0: 00000013 nop
+ a4: 00000013 nop
+ a8: 00000013 nop
+ ac: 00000013 nop
diff --git a/VexRiscv/src/test/cpp/custom/custom_csr/build/custom_csr.elf b/VexRiscv/src/test/cpp/custom/custom_csr/build/custom_csr.elf
new file mode 100755
index 0000000..61da8ff
--- /dev/null
+++ b/VexRiscv/src/test/cpp/custom/custom_csr/build/custom_csr.elf
Binary files differ
diff --git a/VexRiscv/src/test/cpp/custom/custom_csr/build/custom_csr.hex b/VexRiscv/src/test/cpp/custom/custom_csr/build/custom_csr.hex
new file mode 100644
index 0000000..16b3a39
--- /dev/null
+++ b/VexRiscv/src/test/cpp/custom/custom_csr/build/custom_csr.hex
@@ -0,0 +1,12 @@
+:10000000130E1000F32040B0732140B0F32140B034
+:100010006348110663C62106130E2000B7C05D00B9
+:100020009380A098739040B0732140B0634A11044C
+:10003000130E3000F32050B0732150B0F32150B0B4
+:1000400063D02004635E3102130E4000739060B0F1
+:10005000F32040B01301001063F42002130E50008F
+:10006000F32070B0F32040B03701004013010110BD
+:10007000B701004063F6200063E430006F00000128
+:10008000370110F0130141F22320C101370110F0B4
+:10009000130101F2232001001300000013000000EF
+:1000A0001300000013000000130000001300000004
+:00000001FF
diff --git a/VexRiscv/src/test/cpp/custom/custom_csr/build/custom_csr.map b/VexRiscv/src/test/cpp/custom/custom_csr/build/custom_csr.map
new file mode 100644
index 0000000..ec2b738
--- /dev/null
+++ b/VexRiscv/src/test/cpp/custom/custom_csr/build/custom_csr.map
@@ -0,0 +1,30 @@
+
+Memory Configuration
+
+Name Origin Length Attributes
+onChipRam 0x0000000000000000 0x0000000000002000 w !xr
+*default* 0x0000000000000000 0xffffffffffffffff
+
+Linker script and memory map
+
+LOAD build/src/crt.o
+LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.2.0/rv32i/ilp32/libgcc.a
+START GROUP
+LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.2.0/../../../../riscv64-unknown-elf/lib/rv32i/ilp32/libc.a
+LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.2.0/../../../../riscv64-unknown-elf/lib/rv32i/ilp32/libgloss.a
+END GROUP
+LOAD /opt/riscv/bin/../lib/gcc/riscv64-unknown-elf/7.2.0/rv32i/ilp32/libgcc.a
+ 0x0000000000000000 . = 0x0
+
+.crt_section 0x0000000000000000 0xb0
+ 0x0000000000000000 . = ALIGN (0x4)
+ *crt.o(.text)
+ .text 0x0000000000000000 0xb0 build/src/crt.o
+ 0x0000000000000000 _start
+OUTPUT(build/custom_csr.elf elf32-littleriscv)
+
+.data 0x00000000000000b0 0x0
+ .data 0x00000000000000b0 0x0 build/src/crt.o
+
+.bss 0x00000000000000b0 0x0
+ .bss 0x00000000000000b0 0x0 build/src/crt.o
diff --git a/VexRiscv/src/test/cpp/custom/custom_csr/build/custom_csr.v b/VexRiscv/src/test/cpp/custom/custom_csr/build/custom_csr.v
new file mode 100755
index 0000000..81c1861
--- /dev/null
+++ b/VexRiscv/src/test/cpp/custom/custom_csr/build/custom_csr.v
@@ -0,0 +1,12 @@
+@00000000
+13 0E 10 00 F3 20 40 B0 73 21 40 B0 F3 21 40 B0
+63 48 11 06 63 C6 21 06 13 0E 20 00 B7 C0 5D 00
+93 80 A0 98 73 90 40 B0 73 21 40 B0 63 4A 11 04
+13 0E 30 00 F3 20 50 B0 73 21 50 B0 F3 21 50 B0
+63 D0 20 04 63 5E 31 02 13 0E 40 00 73 90 60 B0
+F3 20 40 B0 13 01 00 10 63 F4 20 02 13 0E 50 00
+F3 20 70 B0 F3 20 40 B0 37 01 00 40 13 01 01 10
+B7 01 00 40 63 F6 20 00 63 E4 30 00 6F 00 00 01
+37 01 10 F0 13 01 41 F2 23 20 C1 01 37 01 10 F0
+13 01 01 F2 23 20 01 00 13 00 00 00 13 00 00 00
+13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00
diff --git a/VexRiscv/src/test/cpp/custom/custom_csr/makefile b/VexRiscv/src/test/cpp/custom/custom_csr/makefile
new file mode 100644
index 0000000..5621ec5
--- /dev/null
+++ b/VexRiscv/src/test/cpp/custom/custom_csr/makefile
@@ -0,0 +1,73 @@
+PROJ_NAME=custom_csr
+
+
+RISCV_PATH=/opt/riscv/
+CFLAGS += -march=rv32i -mabi=ilp32
+RISCV_NAME = riscv64-unknown-elf
+RISCV_OBJCOPY = $(RISCV_PATH)/bin/$(RISCV_NAME)-objcopy
+RISCV_OBJDUMP = $(RISCV_PATH)/bin/$(RISCV_NAME)-objdump
+RISCV_CLIB=$(RISCV_PATH)$(RISCV_NAME)/lib/
+RISCV_CC=$(RISCV_PATH)/bin/$(RISCV_NAME)-gcc
+LDSCRIPT=src/ld
+
+
+SRCS = $(wildcard src/*.c) \
+ $(wildcard src/*.cpp) \
+ $(wildcard src/*.S)
+
+
+CFLAGS += -static
+LDFLAGS += -e_start -T $(LDSCRIPT) -nostartfiles -Wl,-Map,$(OBJDIR)/$(PROJ_NAME).map -Wl,--print-memory-usage
+OBJDIR = build
+OBJS := $(SRCS)
+OBJS := $(OBJS:.c=.o)
+OBJS := $(OBJS:.cpp=.o)
+OBJS := $(OBJS:.S=.o)
+OBJS := $(addprefix $(OBJDIR)/,$(OBJS))
+
+
+
+all: $(OBJDIR)/$(PROJ_NAME).elf $(OBJDIR)/$(PROJ_NAME).hex $(OBJDIR)/$(PROJ_NAME).asm $(OBJDIR)/$(PROJ_NAME).v
+ @echo "done"
+
+$(OBJDIR)/%.elf: $(OBJS) | $(OBJDIR)
+ $(RISCV_CC) $(CFLAGS) -o $@ $^ $(LDFLAGS) $(LIBS)
+
+%.hex: %.elf
+ $(RISCV_OBJCOPY) -O ihex $^ $@
+
+%.bin: %.elf
+ $(RISCV_OBJCOPY) -O binary $^ $@
+
+%.v: %.elf
+ $(RISCV_OBJCOPY) -O verilog $^ $@
+
+%.asm: %.elf
+ $(RISCV_OBJDUMP) -S -d $^ > $@
+
+$(OBJDIR)/%.o: %.c
+ mkdir -p $(dir $@)
+ $(RISCV_CC) -c $(CFLAGS) $(INC) -o $@ $^
+
+$(OBJDIR)/%.o: %.cpp
+ mkdir -p $(dir $@)
+ $(RISCV_CC) -c $(CFLAGS) $(INC) -o $@ $^
+
+$(OBJDIR)/%.o: %.S
+ mkdir -p $(dir $@)
+ $(RISCV_CC) -c $(CFLAGS) -o $@ $^ -D__ASSEMBLY__=1
+
+$(OBJDIR):
+ mkdir -p $@
+
+clean:
+ rm -f $(OBJDIR)/$(PROJ_NAME).elf
+ rm -f $(OBJDIR)/$(PROJ_NAME).hex
+ rm -f $(OBJDIR)/$(PROJ_NAME).map
+ rm -f $(OBJDIR)/$(PROJ_NAME).v
+ rm -f $(OBJDIR)/$(PROJ_NAME).asm
+ find $(OBJDIR) -type f -name '*.o' -print0 | xargs -0 -r rm
+
+.SECONDARY: $(OBJS)
+
+
diff --git a/VexRiscv/src/test/cpp/custom/custom_csr/src/crt.S b/VexRiscv/src/test/cpp/custom/custom_csr/src/crt.S
new file mode 100644
index 0000000..8b7e43b
--- /dev/null
+++ b/VexRiscv/src/test/cpp/custom/custom_csr/src/crt.S
@@ -0,0 +1,64 @@
+.globl _start
+_start:
+
+//Test 1
+ li x28, 1
+ csrr x1, 0xB04
+ csrr x2, 0xB04
+ csrr x3, 0xB04
+ blt x2, x1, fail
+ blt x3, x2, fail
+
+
+//Test 2
+ li x28, 2
+ li x1, 6142346
+ csrw 0xB04, x1
+ csrr x2, 0xB04
+ blt x2, x1, fail
+
+
+//Test 3
+ li x28, 3
+ csrr x1, 0xB05
+ csrr x2, 0xB05
+ csrr x3, 0xB05
+ bge x1, x2, fail
+ bge x2, x3, fail
+
+
+
+//Test 4
+ li x28, 4
+ csrw 0xB06, x1
+ csrr x1, 0xB04
+ li x2, 0x100
+ bgeu x1, x2, fail
+
+//Test 5
+ li x28, 5
+ csrr x1, 0xB07
+ csrr x1, 0xB04
+ li x2, 0x40000100
+ li x3, 0x40000000
+ bgeu x1, x2, fail
+ bltu x1, x3, fail
+
+ j pass
+
+fail: //x28 => error code
+ li x2, 0xF00FFF24
+ sw x28, 0(x2)
+
+pass:
+ li x2, 0xF00FFF20
+ sw x0, 0(x2)
+
+
+
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
diff --git a/VexRiscv/src/test/cpp/custom/custom_csr/src/ld b/VexRiscv/src/test/cpp/custom/custom_csr/src/ld
new file mode 100644
index 0000000..8d95523
--- /dev/null
+++ b/VexRiscv/src/test/cpp/custom/custom_csr/src/ld
@@ -0,0 +1,17 @@
+OUTPUT_ARCH( "riscv" )
+
+MEMORY {
+ onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x00000000, LENGTH = 8K
+}
+
+SECTIONS
+{
+ . = 0x000;
+
+ .crt_section :
+ {
+ . = ALIGN(4);
+ *crt.o(.text)
+ } > onChipRam
+
+}
generated by cgit v1.2.3 (git 2.25.1) at 2025-10-24 04:42:38 +0000