diff options
Diffstat (limited to 'VexRiscv/src/test/cpp/raw')
67 files changed, 23207 insertions, 0 deletions
diff --git a/VexRiscv/src/test/cpp/raw/amo/.gitignore b/VexRiscv/src/test/cpp/raw/amo/.gitignore new file mode 100644 index 0000000..c12cb2c --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/amo/.gitignore @@ -0,0 +1,4 @@ +*.map +*.v +*.elf +*.o
\ No newline at end of file diff --git a/VexRiscv/src/test/cpp/raw/amo/build/amo.asm b/VexRiscv/src/test/cpp/raw/amo/build/amo.asm new file mode 100644 index 0000000..d86b61c --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/amo/build/amo.asm @@ -0,0 +1,247 @@ + +build/amo.elf: file format elf32-littleriscv + + +Disassembly of section .crt_section: + +80000000 <_start>: +80000000: 00100e13 li t3,1 +80000004: 00000097 auipc ra,0x0 +80000008: 27408093 addi ra,ra,628 # 80000278 <test1_data> +8000000c: 02d00113 li sp,45 +80000010: 0820a1af amoswap.w gp,sp,(ra) +80000014: 0000a203 lw tp,0(ra) +80000018: 02d00a13 li s4,45 +8000001c: 224a1663 bne s4,tp,80000248 <fail> +80000020: 00b00a13 li s4,11 +80000024: 223a1263 bne s4,gp,80000248 <fail> + +80000028 <test2>: +80000028: 00200e13 li t3,2 +8000002c: 00000097 auipc ra,0x0 +80000030: 25008093 addi ra,ra,592 # 8000027c <test2_data> +80000034: 03700113 li sp,55 +80000038: 0820a1af amoswap.w gp,sp,(ra) +8000003c: 0000a203 lw tp,0(ra) +80000040: 03700a13 li s4,55 +80000044: 204a1263 bne s4,tp,80000248 <fail> +80000048: 01600a13 li s4,22 +8000004c: 1e3a1e63 bne s4,gp,80000248 <fail> + +80000050 <test3>: +80000050: 00300e13 li t3,3 +80000054: 00000097 auipc ra,0x0 +80000058: 22c08093 addi ra,ra,556 # 80000280 <test3_data> +8000005c: 04200113 li sp,66 +80000060: 0020a1af amoadd.w gp,sp,(ra) +80000064: 0000a203 lw tp,0(ra) +80000068: 08b00a13 li s4,139 +8000006c: 1c4a1e63 bne s4,tp,80000248 <fail> +80000070: 04900a13 li s4,73 +80000074: 1c3a1a63 bne s4,gp,80000248 <fail> + +80000078 <test4>: +80000078: 00400e13 li t3,4 +8000007c: 00000097 auipc ra,0x0 +80000080: 20808093 addi ra,ra,520 # 80000284 <test4_data> +80000084: 05700113 li sp,87 +80000088: 2020a1af amoxor.w gp,sp,(ra) +8000008c: 0000a203 lw tp,0(ra) +80000090: 06d00a13 li s4,109 +80000094: 1a4a1a63 bne s4,tp,80000248 <fail> +80000098: 03a00a13 li s4,58 +8000009c: 1a3a1663 bne s4,gp,80000248 <fail> + +800000a0 <test5>: +800000a0: 00500e13 li t3,5 +800000a4: 00000097 auipc ra,0x0 +800000a8: 1e408093 addi ra,ra,484 # 80000288 <test5_data> +800000ac: 02c00113 li sp,44 +800000b0: 6020a1af amoand.w gp,sp,(ra) +800000b4: 0000a203 lw tp,0(ra) +800000b8: 02800a13 li s4,40 +800000bc: 184a1663 bne s4,tp,80000248 <fail> +800000c0: 03800a13 li s4,56 +800000c4: 183a1263 bne s4,gp,80000248 <fail> + +800000c8 <test6>: +800000c8: 00600e13 li t3,6 +800000cc: 00000097 auipc ra,0x0 +800000d0: 1c008093 addi ra,ra,448 # 8000028c <test6_data> +800000d4: 01800113 li sp,24 +800000d8: 4020a1af amoor.w gp,sp,(ra) +800000dc: 0000a203 lw tp,0(ra) +800000e0: 05b00a13 li s4,91 +800000e4: 164a1263 bne s4,tp,80000248 <fail> +800000e8: 04b00a13 li s4,75 +800000ec: 143a1e63 bne s4,gp,80000248 <fail> + +800000f0 <test7>: +800000f0: 00700e13 li t3,7 +800000f4: 00000097 auipc ra,0x0 +800000f8: 19c08093 addi ra,ra,412 # 80000290 <test7_data> +800000fc: 01800113 li sp,24 +80000100: 8020a1af amomin.w gp,sp,(ra) +80000104: 0000a203 lw tp,0(ra) +80000108: 01800a13 li s4,24 +8000010c: 124a1e63 bne s4,tp,80000248 <fail> +80000110: 03800a13 li s4,56 +80000114: 123a1a63 bne s4,gp,80000248 <fail> + +80000118 <test8>: +80000118: 00800e13 li t3,8 +8000011c: 00000097 auipc ra,0x0 +80000120: 17808093 addi ra,ra,376 # 80000294 <test8_data> +80000124: 05800113 li sp,88 +80000128: 8020a1af amomin.w gp,sp,(ra) +8000012c: 0000a203 lw tp,0(ra) +80000130: 05300a13 li s4,83 +80000134: 104a1a63 bne s4,tp,80000248 <fail> +80000138: 05300a13 li s4,83 +8000013c: 103a1663 bne s4,gp,80000248 <fail> + +80000140 <test9>: +80000140: 00900e13 li t3,9 +80000144: 00000097 auipc ra,0x0 +80000148: 15408093 addi ra,ra,340 # 80000298 <test9_data> +8000014c: fca00113 li sp,-54 +80000150: 8020a1af amomin.w gp,sp,(ra) +80000154: 0000a203 lw tp,0(ra) +80000158: fca00a13 li s4,-54 +8000015c: 0e4a1663 bne s4,tp,80000248 <fail> +80000160: 02100a13 li s4,33 +80000164: 0e3a1263 bne s4,gp,80000248 <fail> + +80000168 <test10>: +80000168: 00a00e13 li t3,10 +8000016c: 00000097 auipc ra,0x0 +80000170: 13008093 addi ra,ra,304 # 8000029c <test10_data> +80000174: 03400113 li sp,52 +80000178: 8020a1af amomin.w gp,sp,(ra) +8000017c: 0000a203 lw tp,0(ra) +80000180: fbf00a13 li s4,-65 +80000184: 0c4a1263 bne s4,tp,80000248 <fail> +80000188: fbf00a13 li s4,-65 +8000018c: 0a3a1e63 bne s4,gp,80000248 <fail> + +80000190 <test11>: +80000190: 00b00e13 li t3,11 +80000194: 00000097 auipc ra,0x0 +80000198: 10c08093 addi ra,ra,268 # 800002a0 <test11_data> +8000019c: fcc00113 li sp,-52 +800001a0: a020a1af amomax.w gp,sp,(ra) +800001a4: 0000a203 lw tp,0(ra) +800001a8: fcc00a13 li s4,-52 +800001ac: 084a1e63 bne s4,tp,80000248 <fail> +800001b0: fa900a13 li s4,-87 +800001b4: 083a1a63 bne s4,gp,80000248 <fail> + +800001b8 <test12>: +800001b8: 00c00e13 li t3,12 +800001bc: 00000097 auipc ra,0x0 +800001c0: 0e808093 addi ra,ra,232 # 800002a4 <test12_data> +800001c4: 03400113 li sp,52 +800001c8: a020a1af amomax.w gp,sp,(ra) +800001cc: 0000a203 lw tp,0(ra) +800001d0: 03400a13 li s4,52 +800001d4: 064a1a63 bne s4,tp,80000248 <fail> +800001d8: fc900a13 li s4,-55 +800001dc: 063a1663 bne s4,gp,80000248 <fail> + +800001e0 <test13>: +800001e0: 00d00e13 li t3,13 +800001e4: 00000097 auipc ra,0x0 +800001e8: 0c408093 addi ra,ra,196 # 800002a8 <test13_data> +800001ec: ffff0137 lui sp,0xffff0 +800001f0: c020a1af amominu.w gp,sp,(ra) +800001f4: 0000a203 lw tp,0(ra) +800001f8: ffff0a37 lui s4,0xffff0 +800001fc: 044a1663 bne s4,tp,80000248 <fail> +80000200: ffff0a37 lui s4,0xffff0 +80000204: 004a0a13 addi s4,s4,4 # ffff0004 <test14_data+0x7ffefd58> +80000208: 043a1063 bne s4,gp,80000248 <fail> +8000020c: 0480006f j 80000254 <pass> + +80000210 <test14>: +80000210: 00e00e13 li t3,14 +80000214: 00000097 auipc ra,0x0 +80000218: 09808093 addi ra,ra,152 # 800002ac <test14_data> +8000021c: ffff0137 lui sp,0xffff0 +80000220: 00c10113 addi sp,sp,12 # ffff000c <test14_data+0x7ffefd60> +80000224: e020a1af amomaxu.w gp,sp,(ra) +80000228: 0000a203 lw tp,0(ra) +8000022c: ffff0a37 lui s4,0xffff0 +80000230: 00ca0a13 addi s4,s4,12 # ffff000c <test14_data+0x7ffefd60> +80000234: 004a1a63 bne s4,tp,80000248 <fail> +80000238: ffff0a37 lui s4,0xffff0 +8000023c: 005a0a13 addi s4,s4,5 # ffff0005 <test14_data+0x7ffefd59> +80000240: 003a1463 bne s4,gp,80000248 <fail> +80000244: 0100006f j 80000254 <pass> + +80000248 <fail>: +80000248: f0100137 lui sp,0xf0100 +8000024c: f2410113 addi sp,sp,-220 # f00fff24 <test14_data+0x700ffc78> +80000250: 01c12023 sw t3,0(sp) + +80000254 <pass>: +80000254: f0100137 lui sp,0xf0100 +80000258: f2010113 addi sp,sp,-224 # f00fff20 <test14_data+0x700ffc74> +8000025c: 00012023 sw zero,0(sp) +80000260: 00000013 nop +80000264: 00000013 nop +80000268: 00000013 nop +8000026c: 00000013 nop +80000270: 00000013 nop +80000274: 00000013 nop + +80000278 <test1_data>: +80000278: 0000000b 0xb + +8000027c <test2_data>: +8000027c: 0016 c.slli zero,0x5 + ... + +80000280 <test3_data>: +80000280: 0049 c.nop 18 + ... + +80000284 <test4_data>: +80000284: 003a c.slli zero,0xe + ... + +80000288 <test5_data>: +80000288: 0038 addi a4,sp,8 + ... + +8000028c <test6_data>: +8000028c: 0000004b fnmsub.s ft0,ft0,ft0,ft0,rne + +80000290 <test7_data>: +80000290: 0038 addi a4,sp,8 + ... + +80000294 <test8_data>: +80000294: 00000053 fadd.s ft0,ft0,ft0,rne + +80000298 <test9_data>: +80000298: 0021 c.nop 8 + ... + +8000029c <test10_data>: +8000029c: ffffffbf 0xffffffbf + +800002a0 <test11_data>: +800002a0: ffa9 bnez a5,800001fa <test13+0x1a> +800002a2: ffff 0xffff + +800002a4 <test12_data>: +800002a4: ffc9 bnez a5,8000023e <test14+0x2e> +800002a6: ffff 0xffff + +800002a8 <test13_data>: +800002a8: 0004 0x4 +800002aa: ffff 0xffff + +800002ac <test14_data>: +800002ac: 0005 c.nop 1 +800002ae: ffff 0xffff diff --git a/VexRiscv/src/test/cpp/raw/amo/build/amo.hex b/VexRiscv/src/test/cpp/raw/amo/build/amo.hex new file mode 100644 index 0000000..74d3567 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/amo/build/amo.hex @@ -0,0 +1,45 @@ +:0200000480007A
+:10000000130E100097000000938040271301D002C8
+:10001000AFA1200803A20000130AD00263164A22EF
+:10002000130AB00063123A22130E2000970000005A
+:100030009380002513017003AFA1200803A20000E4
+:10004000130A700363124A20130A6001631E3A1EEA
+:10005000130E3000970000009380C022130120048B
+:10006000AFA1200003A20000130AB008631E4A1CBF
+:10007000130A9004631A3A1C130E40009700000004
+:100080009380802013017005AFA1202003A20000FF
+:10009000130AD006631A4A1A130AA00363163A1AFF
+:1000A000130E5000970000009380401E1301C00201
+:1000B000AFA1206003A20000130A800263164A1851
+:1000C000130A800363123A18130E600097000000B1
+:1000D0009380001C13018001AFA1204003A2000007
+:1000E000130AB00563124A16130AB004631E3A14C9
+:1000F000130E7000970000009380C0191301800157
+:10010000AFA1208003A20000130A8001631E4A12DF
+:10011000130A8003631A3A12130E8000970000003E
+:100120009380801713018005AFA1208003A20000F7
+:10013000130A3005631A4A10130A300563163A1081
+:10014000130E900097000000938040151301A0FC4F
+:10015000AFA1208003A20000130AA0FC63164A0E80
+:10016000130A100263123A0E130EA000970000004B
+:100170009380001313014003AFA1208003A200006D
+:10018000130AF0FB63124A0C130AF0FB631E3A0ACF
+:10019000130EB000970000009380C0101301C0FC44
+:1001A000AFA120A003A20000130AC0FC631E4A08EE
+:1001B000130A90FA631A3A08130EC0009700000061
+:1001C0009380800E13014003AFA120A003A2000082
+:1001D000130A4003631A4A06130A90FC63163A0690
+:1001E000130ED000970000009380400C3701FFFFF2
+:1001F000AFA120C003A20000370AFFFF63164A0424
+:10020000370AFFFF130A4A0063103A046F008004A4
+:10021000130EE00097000000938080093701FFFF74
+:100220001301C100AFA120E003A20000370AFFFFC5
+:10023000130ACA00631A4A00370AFFFF130A5A005A
+:1002400063143A006F000001370110F0130141F20E
+:100250002320C101370110F0130101F22320010016
+:100260001300000013000000130000001300000042
+:1002700013000000130000000B0000001600000037
+:10028000490000003A000000380000004B00000068
+:10029000380000005300000021000000BFFFFFFFF6
+:1002A000A9FFFFFFC9FFFFFF0400FFFF0500FFFFDD
+:00000001FF
diff --git a/VexRiscv/src/test/cpp/raw/amo/makefile b/VexRiscv/src/test/cpp/raw/amo/makefile new file mode 100644 index 0000000..6e9afc5 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/amo/makefile @@ -0,0 +1,5 @@ +PROJ_NAME=amo + +ATOMIC=yes + +include ../common/asm.mk
\ No newline at end of file diff --git a/VexRiscv/src/test/cpp/raw/amo/src/crt.S b/VexRiscv/src/test/cpp/raw/amo/src/crt.S new file mode 100644 index 0000000..5696f1d --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/amo/src/crt.S @@ -0,0 +1,174 @@ +.globl _star +#define TEST_ID x28 + +_start: + +#define assert(reg, value) \ + li x20, value; \ + bne x20, reg, fail; + +test1: + li TEST_ID, 1 + la x1, test1_data + li x2, 45 + amoswap.w x3,x2,(x1) + lw x4, 0(x1) + assert(x4, 45) + assert(x3, 11) + +test2: + li TEST_ID, 2 + la x1, test2_data + li x2, 55 + amoswap.w x3,x2,(x1) + lw x4, 0(x1) + assert(x4, 55) + assert(x3, 22) + + +test3: + li TEST_ID,3 + la x1, test3_data + li x2, 66 + amoadd.w x3,x2,(x1) + lw x4, 0(x1) + assert(x4, 66+73) + assert(x3, 73) + +test4: + li TEST_ID,4 + la x1, test4_data + li x2, 87 + amoxor.w x3,x2,(x1) + lw x4, 0(x1) + assert(x4, 87^58) + assert(x3, 58) + +test5: + li TEST_ID,5 + la x1, test5_data + li x2, 44 + amoand.w x3,x2,(x1) + lw x4, 0(x1) + assert(x4, 44 & 56) + assert(x3, 56) + +test6: + li TEST_ID,6 + la x1, test6_data + li x2, 24 + amoor.w x3,x2,(x1) + lw x4, 0(x1) + assert(x4, 24 | 75) + assert(x3, 75) + +test7: + li TEST_ID,7 + la x1, test7_data + li x2, 24 + amomin.w x3,x2,(x1) + lw x4, 0(x1) + assert(x4, 24) + assert(x3, 56) + + +test8: + li TEST_ID,8 + la x1, test8_data + li x2, 88 + amomin.w x3,x2,(x1) + lw x4, 0(x1) + assert(x4, 83) + assert(x3, 83) + +test9: + li TEST_ID,9 + la x1, test9_data + li x2, -54 + amomin.w x3,x2,(x1) + lw x4, 0(x1) + assert(x4, -54) + assert(x3, 33) + +test10: + li TEST_ID,10 + la x1, test10_data + li x2, 52 + amomin.w x3,x2,(x1) + lw x4, 0(x1) + assert(x4, -65) + assert(x3, -65) + +test11: + li TEST_ID,11 + la x1, test11_data + li x2, -52 + amomax.w x3,x2,(x1) + lw x4, 0(x1) + assert(x4, -52) + assert(x3, -87) + +test12: + li TEST_ID,12 + la x1, test12_data + li x2, 52 + amomax.w x3,x2,(x1) + lw x4, 0(x1) + assert(x4, 52) + assert(x3, -55) + + +test13: + li TEST_ID,13 + la x1, test13_data + li x2, 0xFFFF0000 + amominu.w x3,x2,(x1) + lw x4, 0(x1) + assert(x4, 0xFFFF0000) + assert(x3, 0xFFFF0004) + + j pass + + +test14: + li TEST_ID,14 + la x1, test14_data + li x2, 0xFFFF000C + amomaxu.w x3,x2,(x1) + lw x4, 0(x1) + assert(x4, 0xFFFF000C) + assert(x3, 0xFFFF0005) + + j pass + + +fail: + li x2, 0xF00FFF24 + sw TEST_ID, 0(x2) + +pass: + li x2, 0xF00FFF20 + sw x0, 0(x2) + + nop + nop + nop + nop + nop + nop + + +test1_data: .word 11 +test2_data: .word 22 +test3_data: .word 73 +test4_data: .word 58 +test5_data: .word 56 +test6_data: .word 75 +test7_data: .word 56 +test8_data: .word 83 +test9_data: .word 33 +test10_data: .word -65 +test11_data: .word -87 +test12_data: .word -55 +test13_data: .word 0xFFFF0004 +test14_data: .word 0xFFFF0005
\ No newline at end of file diff --git a/VexRiscv/src/test/cpp/raw/amo/src/ld b/VexRiscv/src/test/cpp/raw/amo/src/ld new file mode 100644 index 0000000..93d8de8 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/amo/src/ld @@ -0,0 +1,16 @@ +OUTPUT_ARCH( "riscv" ) + +MEMORY { + onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 128K +} + +SECTIONS +{ + + .crt_section : + { + . = ALIGN(4); + *crt.o(.text) + } > onChipRam + +} diff --git a/VexRiscv/src/test/cpp/raw/common/asm.mk b/VexRiscv/src/test/cpp/raw/common/asm.mk new file mode 100644 index 0000000..92b51ce --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/common/asm.mk @@ -0,0 +1,89 @@ + +RISCV_PATH?=/opt/riscv/ +RISCV_NAME = riscv64-unknown-elf +RISCV_OBJCOPY = $(RISCV_PATH)/bin/$(RISCV_NAME)-objcopy +RISCV_OBJDUMP = $(RISCV_PATH)/bin/$(RISCV_NAME)-objdump +RISCV_CLIB=$(RISCV_PATH)$(RISCV_NAME)/lib/ +RISCV_CC=$(RISCV_PATH)/bin/$(RISCV_NAME)-gcc +LDSCRIPT=src/ld + +MABI=ilp32 +MARCH := rv32i +ifeq ($(MULDIV),yes) + MARCH := $(MARCH)m +endif +ifeq ($(ATOMIC),yes) + MARCH := $(MARCH)a +endif +ifeq ($(COMPRESSED),yes) + MARCH := $(MARCH)c +endif +ifeq ($(FLOATING),yes) + MARCH := $(MARCH)fd +endif + +CFLAGS += -march=$(MARCH) -mabi=$(MABI) +LDFLAGS += -march=$(MARCH) -mabi=$(MABI) + + + +SRCS = $(wildcard src/*.c) \ + $(wildcard src/*.cpp) \ + $(wildcard src/*.S) + + +CFLAGS += -static +LDFLAGS += -e_start -T $(LDSCRIPT) -nostartfiles -Wl,-Map,$(OBJDIR)/$(PROJ_NAME).map -Wl,--print-memory-usage +OBJDIR = build +OBJS := $(SRCS) +OBJS := $(OBJS:.c=.o) +OBJS := $(OBJS:.cpp=.o) +OBJS := $(OBJS:.S=.o) +OBJS := $(addprefix $(OBJDIR)/,$(OBJS)) + + + +all: $(OBJDIR)/$(PROJ_NAME).elf $(OBJDIR)/$(PROJ_NAME).hex $(OBJDIR)/$(PROJ_NAME).asm $(OBJDIR)/$(PROJ_NAME).bin + @echo "done" + +$(OBJDIR)/%.elf: $(OBJS) | $(OBJDIR) + $(RISCV_CC) $(CFLAGS) -o $@ $^ $(LDFLAGS) $(LIBS) + +%.hex: %.elf + $(RISCV_OBJCOPY) -O ihex $^ $@ + +%.bin: %.elf + $(RISCV_OBJCOPY) -O binary $^ $@ + +%.v: %.elf + $(RISCV_OBJCOPY) -O verilog $^ $@ + +%.asm: %.elf + $(RISCV_OBJDUMP) -S -d $^ > $@ + +$(OBJDIR)/%.o: %.c + mkdir -p $(dir $@) + $(RISCV_CC) -c $(CFLAGS) $(INC) -o $@ $^ + +$(OBJDIR)/%.o: %.cpp + mkdir -p $(dir $@) + $(RISCV_CC) -c $(CFLAGS) $(INC) -o $@ $^ + +$(OBJDIR)/%.o: %.S + mkdir -p $(dir $@) + $(RISCV_CC) -c $(CFLAGS) -o $@ $^ -D__ASSEMBLY__=1 + +$(OBJDIR): + mkdir -p $@ + +clean: + rm -f $(OBJDIR)/$(PROJ_NAME).elf + rm -f $(OBJDIR)/$(PROJ_NAME).hex + rm -f $(OBJDIR)/$(PROJ_NAME).map + rm -f $(OBJDIR)/$(PROJ_NAME).v + rm -f $(OBJDIR)/$(PROJ_NAME).asm + find $(OBJDIR) -type f -name '*.o' -print0 | xargs -0 -r rm + +.SECONDARY: $(OBJS) + + diff --git a/VexRiscv/src/test/cpp/raw/dcache/.gitignore b/VexRiscv/src/test/cpp/raw/dcache/.gitignore new file mode 100644 index 0000000..c12cb2c --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/dcache/.gitignore @@ -0,0 +1,4 @@ +*.map +*.v +*.elf +*.o
\ No newline at end of file diff --git a/VexRiscv/src/test/cpp/raw/dcache/build/dcache.asm b/VexRiscv/src/test/cpp/raw/dcache/build/dcache.asm new file mode 100644 index 0000000..202a1e6 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/dcache/build/dcache.asm @@ -0,0 +1,78 @@ + +build/dcache.elf: file format elf32-littleriscv + + +Disassembly of section .crt_section: + +80000000 <_start>: +80000000: 00000097 auipc ra,0x0 +80000004: 0b408093 addi ra,ra,180 # 800000b4 <fail> + +80000008 <test1>: +80000008: 00100e13 li t3,1 +8000000c: 00100093 li ra,1 +80000010: 00300113 li sp,3 +80000014: 00208093 addi ra,ra,2 +80000018: 08209e63 bne ra,sp,800000b4 <fail> + +8000001c <test2>: +8000001c: 00200e13 li t3,2 +80000020: f56700b7 lui ra,0xf5670 +80000024: 900ff137 lui sp,0x900ff +80000028: 40000313 li t1,1024 + +8000002c <test2_repeat>: +8000002c: 00100193 li gp,1 +80000030: 00200293 li t0,2 +80000034: 006303b3 add t2,t1,t1 +80000038: 007181b3 add gp,gp,t2 +8000003c: 007282b3 add t0,t0,t2 +80000040: 00312023 sw gp,0(sp) # 900ff000 <pass+0x100fef40> +80000044: 0000a023 sw zero,0(ra) # f5670000 <pass+0x7566ff40> +80000048: 00012203 lw tp,0(sp) +8000004c: 06429463 bne t0,tp,800000b4 <fail> +80000050: ffc30313 addi t1,t1,-4 +80000054: 01008093 addi ra,ra,16 +80000058: 01010113 addi sp,sp,16 +8000005c: 0000500f 0x500f +80000060: fc0316e3 bnez t1,8000002c <test2_repeat> + +80000064 <test3>: +80000064: 00300e13 li t3,3 +80000068: f56700b7 lui ra,0xf5670 +8000006c: 900ff137 lui sp,0x900ff +80000070: 40000313 li t1,1024 + +80000074 <test3_repeat>: +80000074: 00200193 li gp,2 +80000078: 00300293 li t0,3 +8000007c: 006303b3 add t2,t1,t1 +80000080: 007181b3 add gp,gp,t2 +80000084: 007282b3 add t0,t0,t2 +80000088: 00012203 lw tp,0(sp) # 900ff000 <pass+0x100fef40> +8000008c: 00312023 sw gp,0(sp) +80000090: 0000a023 sw zero,0(ra) # f5670000 <pass+0x7566ff40> +80000094: 0000500f 0x500f +80000098: 00012203 lw tp,0(sp) +8000009c: 00429c63 bne t0,tp,800000b4 <fail> +800000a0: ffc30313 addi t1,t1,-4 +800000a4: 01008093 addi ra,ra,16 +800000a8: 01010113 addi sp,sp,16 +800000ac: fc0314e3 bnez t1,80000074 <test3_repeat> +800000b0: 0100006f j 800000c0 <pass> + +800000b4 <fail>: +800000b4: f0100137 lui sp,0xf0100 +800000b8: f2410113 addi sp,sp,-220 # f00fff24 <pass+0x700ffe64> +800000bc: 01c12023 sw t3,0(sp) + +800000c0 <pass>: +800000c0: f0100137 lui sp,0xf0100 +800000c4: f2010113 addi sp,sp,-224 # f00fff20 <pass+0x700ffe60> +800000c8: 00012023 sw zero,0(sp) +800000cc: 00000013 nop +800000d0: 00000013 nop +800000d4: 00000013 nop +800000d8: 00000013 nop +800000dc: 00000013 nop +800000e0: 00000013 nop diff --git a/VexRiscv/src/test/cpp/raw/dcache/build/dcache.hex b/VexRiscv/src/test/cpp/raw/dcache/build/dcache.hex new file mode 100644 index 0000000..2bc8fe9 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/dcache/build/dcache.hex @@ -0,0 +1,17 @@ +:0200000480007A
+:10000000970000009380400B130E10009300100027
+:100010001301300093802000639E2008130E2000FF
+:10002000B70067F537F10F901303004093011000FC
+:1000300093022000B3036300B3817100B3827200A6
+:100040002320310023A00000032201006394420614
+:100050001303C3FF93800001130101010F5000003F
+:10006000E31603FC130E3000B70067F537F10F906D
+:10007000130300409301200093023000B303630098
+:10008000B3817100B382720003220100232031008A
+:1000900023A000000F50000003220100639C4200D7
+:1000A0001303C3FF9380000113010101E31403FC58
+:1000B0006F000001370110F0130141F22320C1014C
+:1000C000370110F0130101F223200100130000009A
+:1000D00013000000130000001300000013000000D4
+:0400E0001300000009
+:00000001FF
diff --git a/VexRiscv/src/test/cpp/raw/dcache/makefile b/VexRiscv/src/test/cpp/raw/dcache/makefile new file mode 100644 index 0000000..5ebb942 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/dcache/makefile @@ -0,0 +1,3 @@ +PROJ_NAME=dcache + +include ../common/asm.mk
\ No newline at end of file diff --git a/VexRiscv/src/test/cpp/raw/dcache/src/crt.S b/VexRiscv/src/test/cpp/raw/dcache/src/crt.S new file mode 100644 index 0000000..054b1dd --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/dcache/src/crt.S @@ -0,0 +1,75 @@ +.globl _star +#define TEST_ID x28 + +_start: + la x1, fail + //csrw mtvec, x1 + +test1: //Dummy test + li TEST_ID, 1 + li x1, 1 + li x2, 3 + addi x1, x1, 2 + bne x1, x2, fail + +test2: //No invalidate, without load => new one + li TEST_ID, 2 + li x1, 0xF5670000 + li x2, 0x900FF000 + li x6, 4096/4 +test2_repeat: + la x3, 1 + la x5, 2 + add x7, x6, x6 + add x3, x3, x7 + add x5, x5, x7 + sw x3, 0(x2) + sw x0, 0(x1) + lw x4, 0(x2) + bne x5,x4, fail + addi x6, x6, -4 + addi x1, x1, 16 + addi x2, x2, 16 +.word 0x000500F // dcache flush + bnez x6, test2_repeat + +test3: //with invalidate, with preload + li TEST_ID, 3 + li x1, 0xF5670000 + li x2, 0x900FF000 + li x6, 4096/4 +test3_repeat: + la x3, 2 + la x5, 3 + add x7, x6, x6 + add x3, x3, x7 + add x5, x5, x7 + lw x4, 0(x2) + sw x3, 0(x2) + sw x0, 0(x1) +.word 0x000500F // dcache flush + lw x4, 0(x2) + bne x5,x4, fail + addi x6, x6, -4 + addi x1, x1, 16 + addi x2, x2, 16 + bnez x6, test3_repeat + + + + j pass + +fail: + li x2, 0xF00FFF24 + sw TEST_ID, 0(x2) + +pass: + li x2, 0xF00FFF20 + sw x0, 0(x2) + + nop + nop + nop + nop + nop + nop diff --git a/VexRiscv/src/test/cpp/raw/dcache/src/ld b/VexRiscv/src/test/cpp/raw/dcache/src/ld new file mode 100644 index 0000000..93d8de8 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/dcache/src/ld @@ -0,0 +1,16 @@ +OUTPUT_ARCH( "riscv" ) + +MEMORY { + onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 128K +} + +SECTIONS +{ + + .crt_section : + { + . = ALIGN(4); + *crt.o(.text) + } > onChipRam + +} diff --git a/VexRiscv/src/test/cpp/raw/deleg/.gitignore b/VexRiscv/src/test/cpp/raw/deleg/.gitignore new file mode 100644 index 0000000..c12cb2c --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/deleg/.gitignore @@ -0,0 +1,4 @@ +*.map +*.v +*.elf +*.o
\ No newline at end of file diff --git a/VexRiscv/src/test/cpp/raw/deleg/build/deleg.asm b/VexRiscv/src/test/cpp/raw/deleg/build/deleg.asm new file mode 100644 index 0000000..e64c374 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/deleg/build/deleg.asm @@ -0,0 +1,749 @@ + +build/deleg.elf: file format elf32-littleriscv + + +Disassembly of section .crt_section: + +80000000 <_start>: +80000000: 00100e93 li t4,1 +80000004: 00001097 auipc ra,0x1 +80000008: a3c08093 addi ra,ra,-1476 # 80000a40 <mtrap> +8000000c: 30509073 csrw mtvec,ra +80000010: 00001097 auipc ra,0x1 +80000014: a6808093 addi ra,ra,-1432 # 80000a78 <strap> +80000018: 10509073 csrw stvec,ra +8000001c: f00110b7 lui ra,0xf0011 +80000020: 00000113 li sp,0 +80000024: 0020a023 sw sp,0(ra) # f0011000 <strap+0x70010588> +80000028: 00000013 nop +8000002c: 00000013 nop +80000030: 00000013 nop +80000034: 00000013 nop +80000038: 00000013 nop +8000003c: 00000013 nop +80000040: 00000013 nop +80000044: 00000013 nop + +80000048 <test1>: +80000048: 00100e13 li t3,1 +8000004c: 00000f17 auipc t5,0x0 +80000050: 00cf0f13 addi t5,t5,12 # 80000058 <test2> +80000054: 00000073 ecall + +80000058 <test2>: +80000058: 00200e13 li t3,2 +8000005c: 000020b7 lui ra,0x2 +80000060: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> +80000064: 00000113 li sp,0 +80000068: 3000b073 csrc mstatus,ra +8000006c: 30012073 csrs mstatus,sp +80000070: 00000097 auipc ra,0x0 +80000074: 01408093 addi ra,ra,20 # 80000084 <test2+0x2c> +80000078: 34109073 csrw mepc,ra +8000007c: 30200073 mret +80000080: 1a90006f j 80000a28 <fail> +80000084: 00000f17 auipc t5,0x0 +80000088: 024f0f13 addi t5,t5,36 # 800000a8 <test4> +8000008c: 00000073 ecall +80000090: 1990006f j 80000a28 <fail> + +80000094 <test3>: +80000094: 00300e13 li t3,3 +80000098: 00000f17 auipc t5,0x0 +8000009c: 010f0f13 addi t5,t5,16 # 800000a8 <test4> +800000a0: 00102083 lw ra,1(zero) # 1 <_start-0x7fffffff> +800000a4: 1850006f j 80000a28 <fail> + +800000a8 <test4>: +800000a8: 00400e13 li t3,4 +800000ac: 000020b7 lui ra,0x2 +800000b0: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> +800000b4: 00001137 lui sp,0x1 +800000b8: 80010113 addi sp,sp,-2048 # 800 <_start-0x7ffff800> +800000bc: 3000b073 csrc mstatus,ra +800000c0: 30012073 csrs mstatus,sp +800000c4: 00000097 auipc ra,0x0 +800000c8: 01408093 addi ra,ra,20 # 800000d8 <test4+0x30> +800000cc: 34109073 csrw mepc,ra +800000d0: 30200073 mret +800000d4: 1550006f j 80000a28 <fail> +800000d8: 00000f17 auipc t5,0x0 +800000dc: 010f0f13 addi t5,t5,16 # 800000e8 <test5> +800000e0: 00102083 lw ra,1(zero) # 1 <_start-0x7fffffff> +800000e4: 1450006f j 80000a28 <fail> + +800000e8 <test5>: +800000e8: 00500e13 li t3,5 +800000ec: 000020b7 lui ra,0x2 +800000f0: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> +800000f4: 00000113 li sp,0 +800000f8: 3000b073 csrc mstatus,ra +800000fc: 30012073 csrs mstatus,sp +80000100: 00000097 auipc ra,0x0 +80000104: 01408093 addi ra,ra,20 # 80000114 <test5+0x2c> +80000108: 34109073 csrw mepc,ra +8000010c: 30200073 mret +80000110: 1190006f j 80000a28 <fail> +80000114: 00000f17 auipc t5,0x0 +80000118: 010f0f13 addi t5,t5,16 # 80000124 <test6> +8000011c: 00102083 lw ra,1(zero) # 1 <_start-0x7fffffff> +80000120: 1090006f j 80000a28 <fail> + +80000124 <test6>: +80000124: 00600e13 li t3,6 +80000128: 01000093 li ra,16 +8000012c: 30209073 csrw medeleg,ra + +80000130 <test7>: +80000130: 00700e13 li t3,7 +80000134: 00000f17 auipc t5,0x0 +80000138: 010f0f13 addi t5,t5,16 # 80000144 <test8> +8000013c: 00102083 lw ra,1(zero) # 1 <_start-0x7fffffff> +80000140: 0e90006f j 80000a28 <fail> + +80000144 <test8>: +80000144: 00800e13 li t3,8 +80000148: 00000f17 auipc t5,0x0 +8000014c: 03cf0f13 addi t5,t5,60 # 80000184 <test9> +80000150: 000020b7 lui ra,0x2 +80000154: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> +80000158: 00001137 lui sp,0x1 +8000015c: 80010113 addi sp,sp,-2048 # 800 <_start-0x7ffff800> +80000160: 3000b073 csrc mstatus,ra +80000164: 30012073 csrs mstatus,sp +80000168: 00000097 auipc ra,0x0 +8000016c: 01408093 addi ra,ra,20 # 8000017c <test8+0x38> +80000170: 34109073 csrw mepc,ra +80000174: 30200073 mret +80000178: 0b10006f j 80000a28 <fail> +8000017c: 00102083 lw ra,1(zero) # 1 <_start-0x7fffffff> +80000180: 0a90006f j 80000a28 <fail> + +80000184 <test9>: +80000184: 00900e13 li t3,9 +80000188: 00000f17 auipc t5,0x0 +8000018c: 038f0f13 addi t5,t5,56 # 800001c0 <test10> +80000190: 000020b7 lui ra,0x2 +80000194: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> +80000198: 00000113 li sp,0 +8000019c: 3000b073 csrc mstatus,ra +800001a0: 30012073 csrs mstatus,sp +800001a4: 00000097 auipc ra,0x0 +800001a8: 01408093 addi ra,ra,20 # 800001b8 <test9+0x34> +800001ac: 34109073 csrw mepc,ra +800001b0: 30200073 mret +800001b4: 0750006f j 80000a28 <fail> +800001b8: 00102083 lw ra,1(zero) # 1 <_start-0x7fffffff> +800001bc: 06d0006f j 80000a28 <fail> + +800001c0 <test10>: +800001c0: 00a00e13 li t3,10 +800001c4: 00000f17 auipc t5,0x0 +800001c8: 07cf0f13 addi t5,t5,124 # 80000240 <test11> +800001cc: f00110b7 lui ra,0xf0011 +800001d0: 00000113 li sp,0 +800001d4: 0020a023 sw sp,0(ra) # f0011000 <strap+0x70010588> +800001d8: 00000013 nop +800001dc: 00000013 nop +800001e0: 00000013 nop +800001e4: 00000013 nop +800001e8: 00000013 nop +800001ec: 00000013 nop +800001f0: 00000013 nop +800001f4: 00000013 nop +800001f8: 00800093 li ra,8 +800001fc: 30009073 csrw mstatus,ra +80000200: 000010b7 lui ra,0x1 +80000204: 80008093 addi ra,ra,-2048 # 800 <_start-0x7ffff800> +80000208: 30409073 csrw mie,ra +8000020c: f00110b7 lui ra,0xf0011 +80000210: 00100113 li sp,1 +80000214: 0020a023 sw sp,0(ra) # f0011000 <strap+0x70010588> +80000218: 00000013 nop +8000021c: 00000013 nop +80000220: 00000013 nop +80000224: 00000013 nop +80000228: 00000013 nop +8000022c: 00000013 nop +80000230: 00000013 nop +80000234: 00000013 nop +80000238: 10500073 wfi +8000023c: 7ec0006f j 80000a28 <fail> + +80000240 <test11>: +80000240: 00b00e13 li t3,11 +80000244: 00000f17 auipc t5,0x0 +80000248: 0a8f0f13 addi t5,t5,168 # 800002ec <test12> +8000024c: f00110b7 lui ra,0xf0011 +80000250: 00000113 li sp,0 +80000254: 0020a023 sw sp,0(ra) # f0011000 <strap+0x70010588> +80000258: 00000013 nop +8000025c: 00000013 nop +80000260: 00000013 nop +80000264: 00000013 nop +80000268: 00000013 nop +8000026c: 00000013 nop +80000270: 00000013 nop +80000274: 00000013 nop +80000278: 00800093 li ra,8 +8000027c: 30009073 csrw mstatus,ra +80000280: 000010b7 lui ra,0x1 +80000284: 80008093 addi ra,ra,-2048 # 800 <_start-0x7ffff800> +80000288: 30409073 csrw mie,ra +8000028c: 000020b7 lui ra,0x2 +80000290: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> +80000294: 00001137 lui sp,0x1 +80000298: 80010113 addi sp,sp,-2048 # 800 <_start-0x7ffff800> +8000029c: 3000b073 csrc mstatus,ra +800002a0: 30012073 csrs mstatus,sp +800002a4: 00000097 auipc ra,0x0 +800002a8: 01408093 addi ra,ra,20 # 800002b8 <test11+0x78> +800002ac: 34109073 csrw mepc,ra +800002b0: 30200073 mret +800002b4: 7740006f j 80000a28 <fail> +800002b8: f00110b7 lui ra,0xf0011 +800002bc: 00100113 li sp,1 +800002c0: 0020a023 sw sp,0(ra) # f0011000 <strap+0x70010588> +800002c4: 00000013 nop +800002c8: 00000013 nop +800002cc: 00000013 nop +800002d0: 00000013 nop +800002d4: 00000013 nop +800002d8: 00000013 nop +800002dc: 00000013 nop +800002e0: 00000013 nop +800002e4: 10500073 wfi +800002e8: 7400006f j 80000a28 <fail> + +800002ec <test12>: +800002ec: 00c00e13 li t3,12 +800002f0: 00000f17 auipc t5,0x0 +800002f4: 0a4f0f13 addi t5,t5,164 # 80000394 <test14> +800002f8: f00110b7 lui ra,0xf0011 +800002fc: 00000113 li sp,0 +80000300: 0020a023 sw sp,0(ra) # f0011000 <strap+0x70010588> +80000304: 00000013 nop +80000308: 00000013 nop +8000030c: 00000013 nop +80000310: 00000013 nop +80000314: 00000013 nop +80000318: 00000013 nop +8000031c: 00000013 nop +80000320: 00000013 nop +80000324: 00800093 li ra,8 +80000328: 30009073 csrw mstatus,ra +8000032c: 000010b7 lui ra,0x1 +80000330: 80008093 addi ra,ra,-2048 # 800 <_start-0x7ffff800> +80000334: 30409073 csrw mie,ra +80000338: 000020b7 lui ra,0x2 +8000033c: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> +80000340: 00000113 li sp,0 +80000344: 3000b073 csrc mstatus,ra +80000348: 30012073 csrs mstatus,sp +8000034c: 00000097 auipc ra,0x0 +80000350: 01408093 addi ra,ra,20 # 80000360 <test12+0x74> +80000354: 34109073 csrw mepc,ra +80000358: 30200073 mret +8000035c: 6cc0006f j 80000a28 <fail> +80000360: f00110b7 lui ra,0xf0011 +80000364: 00100113 li sp,1 +80000368: 0020a023 sw sp,0(ra) # f0011000 <strap+0x70010588> +8000036c: 00000013 nop +80000370: 00000013 nop +80000374: 00000013 nop +80000378: 00000013 nop +8000037c: 00000013 nop +80000380: 00000013 nop +80000384: 00000013 nop +80000388: 00000013 nop +8000038c: 10500073 wfi +80000390: 6980006f j 80000a28 <fail> + +80000394 <test14>: +80000394: 00200093 li ra,2 +80000398: 10009073 csrw sstatus,ra +8000039c: 00e00e13 li t3,14 +800003a0: 00000f17 auipc t5,0x0 +800003a4: 080f0f13 addi t5,t5,128 # 80000420 <test15> +800003a8: f00120b7 lui ra,0xf0012 +800003ac: 00000113 li sp,0 +800003b0: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011588> +800003b4: 00000013 nop +800003b8: 00000013 nop +800003bc: 00000013 nop +800003c0: 00000013 nop +800003c4: 00000013 nop +800003c8: 00000013 nop +800003cc: 00000013 nop +800003d0: 00000013 nop +800003d4: 00200093 li ra,2 +800003d8: 30009073 csrw mstatus,ra +800003dc: 20000093 li ra,512 +800003e0: 30409073 csrw mie,ra +800003e4: 00000e93 li t4,0 +800003e8: f00120b7 lui ra,0xf0012 +800003ec: 00100113 li sp,1 +800003f0: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011588> +800003f4: 00000013 nop +800003f8: 00000013 nop +800003fc: 00000013 nop +80000400: 00000013 nop +80000404: 00000013 nop +80000408: 00000013 nop +8000040c: 00000013 nop +80000410: 00000013 nop +80000414: 06400093 li ra,100 +80000418: fff08093 addi ra,ra,-1 +8000041c: fe104ee3 bgtz ra,80000418 <test14+0x84> + +80000420 <test15>: +80000420: 00f00e13 li t3,15 +80000424: 00000f17 auipc t5,0x0 +80000428: 0a8f0f13 addi t5,t5,168 # 800004cc <test16> +8000042c: f00120b7 lui ra,0xf0012 +80000430: 00000113 li sp,0 +80000434: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011588> +80000438: 00000013 nop +8000043c: 00000013 nop +80000440: 00000013 nop +80000444: 00000013 nop +80000448: 00000013 nop +8000044c: 00000013 nop +80000450: 00000013 nop +80000454: 00000013 nop +80000458: 00200093 li ra,2 +8000045c: 30009073 csrw mstatus,ra +80000460: 20000093 li ra,512 +80000464: 30409073 csrw mie,ra +80000468: 000020b7 lui ra,0x2 +8000046c: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> +80000470: 00001137 lui sp,0x1 +80000474: 80010113 addi sp,sp,-2048 # 800 <_start-0x7ffff800> +80000478: 3000b073 csrc mstatus,ra +8000047c: 30012073 csrs mstatus,sp +80000480: 00000097 auipc ra,0x0 +80000484: 01408093 addi ra,ra,20 # 80000494 <test15+0x74> +80000488: 34109073 csrw mepc,ra +8000048c: 30200073 mret +80000490: 5980006f j 80000a28 <fail> +80000494: 00100e93 li t4,1 +80000498: f00120b7 lui ra,0xf0012 +8000049c: 00100113 li sp,1 +800004a0: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011588> +800004a4: 00000013 nop +800004a8: 00000013 nop +800004ac: 00000013 nop +800004b0: 00000013 nop +800004b4: 00000013 nop +800004b8: 00000013 nop +800004bc: 00000013 nop +800004c0: 00000013 nop +800004c4: 10500073 wfi +800004c8: 5600006f j 80000a28 <fail> + +800004cc <test16>: +800004cc: 01000e13 li t3,16 +800004d0: 00000f17 auipc t5,0x0 +800004d4: 0a0f0f13 addi t5,t5,160 # 80000570 <test17> +800004d8: f00120b7 lui ra,0xf0012 +800004dc: 00000113 li sp,0 +800004e0: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011588> +800004e4: 00000013 nop +800004e8: 00000013 nop +800004ec: 00000013 nop +800004f0: 00000013 nop +800004f4: 00000013 nop +800004f8: 00000013 nop +800004fc: 00000013 nop +80000500: 00000013 nop +80000504: 00200093 li ra,2 +80000508: 30009073 csrw mstatus,ra +8000050c: 20000093 li ra,512 +80000510: 30409073 csrw mie,ra +80000514: 000020b7 lui ra,0x2 +80000518: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> +8000051c: 00000113 li sp,0 +80000520: 3000b073 csrc mstatus,ra +80000524: 30012073 csrs mstatus,sp +80000528: 00000097 auipc ra,0x0 +8000052c: 01408093 addi ra,ra,20 # 8000053c <test16+0x70> +80000530: 34109073 csrw mepc,ra +80000534: 30200073 mret +80000538: 4f00006f j 80000a28 <fail> +8000053c: f00120b7 lui ra,0xf0012 +80000540: 00100113 li sp,1 +80000544: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011588> +80000548: 00000013 nop +8000054c: 00000013 nop +80000550: 00000013 nop +80000554: 00000013 nop +80000558: 00000013 nop +8000055c: 00000013 nop +80000560: 00000013 nop +80000564: 00000013 nop +80000568: 10500073 wfi +8000056c: 4bc0006f j 80000a28 <fail> + +80000570 <test17>: +80000570: 01100e13 li t3,17 +80000574: 20000093 li ra,512 +80000578: 30309073 csrw mideleg,ra +8000057c: 00000f17 auipc t5,0x0 +80000580: 080f0f13 addi t5,t5,128 # 800005fc <test18> +80000584: f00120b7 lui ra,0xf0012 +80000588: 00000113 li sp,0 +8000058c: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011588> +80000590: 00000013 nop +80000594: 00000013 nop +80000598: 00000013 nop +8000059c: 00000013 nop +800005a0: 00000013 nop +800005a4: 00000013 nop +800005a8: 00000013 nop +800005ac: 00000013 nop +800005b0: 00200093 li ra,2 +800005b4: 30009073 csrw mstatus,ra +800005b8: 20000093 li ra,512 +800005bc: 30409073 csrw mie,ra +800005c0: 00000e93 li t4,0 +800005c4: f00120b7 lui ra,0xf0012 +800005c8: 00100113 li sp,1 +800005cc: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011588> +800005d0: 00000013 nop +800005d4: 00000013 nop +800005d8: 00000013 nop +800005dc: 00000013 nop +800005e0: 00000013 nop +800005e4: 00000013 nop +800005e8: 00000013 nop +800005ec: 00000013 nop +800005f0: 06400093 li ra,100 +800005f4: fff08093 addi ra,ra,-1 +800005f8: fe104ee3 bgtz ra,800005f4 <test17+0x84> + +800005fc <test18>: +800005fc: 01200e13 li t3,18 +80000600: 00000f17 auipc t5,0x0 +80000604: 0a8f0f13 addi t5,t5,168 # 800006a8 <test19> +80000608: f00120b7 lui ra,0xf0012 +8000060c: 00000113 li sp,0 +80000610: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011588> +80000614: 00000013 nop +80000618: 00000013 nop +8000061c: 00000013 nop +80000620: 00000013 nop +80000624: 00000013 nop +80000628: 00000013 nop +8000062c: 00000013 nop +80000630: 00000013 nop +80000634: 00200093 li ra,2 +80000638: 30009073 csrw mstatus,ra +8000063c: 20000093 li ra,512 +80000640: 30409073 csrw mie,ra +80000644: 000020b7 lui ra,0x2 +80000648: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> +8000064c: 00001137 lui sp,0x1 +80000650: 80010113 addi sp,sp,-2048 # 800 <_start-0x7ffff800> +80000654: 3000b073 csrc mstatus,ra +80000658: 30012073 csrs mstatus,sp +8000065c: 00000097 auipc ra,0x0 +80000660: 01408093 addi ra,ra,20 # 80000670 <test18+0x74> +80000664: 34109073 csrw mepc,ra +80000668: 30200073 mret +8000066c: 3bc0006f j 80000a28 <fail> +80000670: 00100e93 li t4,1 +80000674: f00120b7 lui ra,0xf0012 +80000678: 00100113 li sp,1 +8000067c: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011588> +80000680: 00000013 nop +80000684: 00000013 nop +80000688: 00000013 nop +8000068c: 00000013 nop +80000690: 00000013 nop +80000694: 00000013 nop +80000698: 00000013 nop +8000069c: 00000013 nop +800006a0: 10500073 wfi +800006a4: 3840006f j 80000a28 <fail> + +800006a8 <test19>: +800006a8: 01300e13 li t3,19 +800006ac: 00000f17 auipc t5,0x0 +800006b0: 0a0f0f13 addi t5,t5,160 # 8000074c <test20> +800006b4: f00120b7 lui ra,0xf0012 +800006b8: 00000113 li sp,0 +800006bc: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011588> +800006c0: 00000013 nop +800006c4: 00000013 nop +800006c8: 00000013 nop +800006cc: 00000013 nop +800006d0: 00000013 nop +800006d4: 00000013 nop +800006d8: 00000013 nop +800006dc: 00000013 nop +800006e0: 00200093 li ra,2 +800006e4: 30009073 csrw mstatus,ra +800006e8: 20000093 li ra,512 +800006ec: 30409073 csrw mie,ra +800006f0: 000020b7 lui ra,0x2 +800006f4: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> +800006f8: 00000113 li sp,0 +800006fc: 3000b073 csrc mstatus,ra +80000700: 30012073 csrs mstatus,sp +80000704: 00000097 auipc ra,0x0 +80000708: 01408093 addi ra,ra,20 # 80000718 <test19+0x70> +8000070c: 34109073 csrw mepc,ra +80000710: 30200073 mret +80000714: 3140006f j 80000a28 <fail> +80000718: f00120b7 lui ra,0xf0012 +8000071c: 00100113 li sp,1 +80000720: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011588> +80000724: 00000013 nop +80000728: 00000013 nop +8000072c: 00000013 nop +80000730: 00000013 nop +80000734: 00000013 nop +80000738: 00000013 nop +8000073c: 00000013 nop +80000740: 00000013 nop +80000744: 10500073 wfi +80000748: 2e00006f j 80000a28 <fail> + +8000074c <test20>: +8000074c: f00120b7 lui ra,0xf0012 +80000750: 00000113 li sp,0 +80000754: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011588> +80000758: 00000013 nop +8000075c: 00000013 nop +80000760: 00000013 nop +80000764: 00000013 nop +80000768: 00000013 nop +8000076c: 00000013 nop +80000770: 00000013 nop +80000774: 00000013 nop +80000778: 01400e13 li t3,20 +8000077c: 00000f17 auipc t5,0x0 +80000780: 030f0f13 addi t5,t5,48 # 800007ac <test21> +80000784: 00200093 li ra,2 +80000788: 30009073 csrw mstatus,ra +8000078c: 20000093 li ra,512 +80000790: 30409073 csrw mie,ra +80000794: 00000e93 li t4,0 +80000798: 20000093 li ra,512 +8000079c: 1440a073 csrs sip,ra +800007a0: 06400093 li ra,100 +800007a4: fff08093 addi ra,ra,-1 +800007a8: fe104ee3 bgtz ra,800007a4 <test20+0x58> + +800007ac <test21>: +800007ac: 01500e13 li t3,21 +800007b0: 00000f17 auipc t5,0x0 +800007b4: 060f0f13 addi t5,t5,96 # 80000810 <test22> +800007b8: 20000093 li ra,512 +800007bc: 1440b073 csrc sip,ra +800007c0: 00200093 li ra,2 +800007c4: 30009073 csrw mstatus,ra +800007c8: 20000093 li ra,512 +800007cc: 30409073 csrw mie,ra +800007d0: 000020b7 lui ra,0x2 +800007d4: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> +800007d8: 00001137 lui sp,0x1 +800007dc: 80010113 addi sp,sp,-2048 # 800 <_start-0x7ffff800> +800007e0: 3000b073 csrc mstatus,ra +800007e4: 30012073 csrs mstatus,sp +800007e8: 00000097 auipc ra,0x0 +800007ec: 01408093 addi ra,ra,20 # 800007fc <test21+0x50> +800007f0: 34109073 csrw mepc,ra +800007f4: 30200073 mret +800007f8: 2300006f j 80000a28 <fail> +800007fc: 00100e93 li t4,1 +80000800: 20000093 li ra,512 +80000804: 1440a073 csrs sip,ra +80000808: 10500073 wfi +8000080c: 21c0006f j 80000a28 <fail> + +80000810 <test22>: +80000810: 01600e13 li t3,22 +80000814: 00000f17 auipc t5,0x0 +80000818: 058f0f13 addi t5,t5,88 # 8000086c <test23> +8000081c: 20000093 li ra,512 +80000820: 1440b073 csrc sip,ra +80000824: 00200093 li ra,2 +80000828: 30009073 csrw mstatus,ra +8000082c: 20000093 li ra,512 +80000830: 30409073 csrw mie,ra +80000834: 20000093 li ra,512 +80000838: 1440a073 csrs sip,ra +8000083c: 000020b7 lui ra,0x2 +80000840: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> +80000844: 00000113 li sp,0 +80000848: 3000b073 csrc mstatus,ra +8000084c: 30012073 csrs mstatus,sp +80000850: 00000097 auipc ra,0x0 +80000854: 01408093 addi ra,ra,20 # 80000864 <test22+0x54> +80000858: 34109073 csrw mepc,ra +8000085c: 30200073 mret +80000860: 1c80006f j 80000a28 <fail> +80000864: 10500073 wfi +80000868: 1c00006f j 80000a28 <fail> + +8000086c <test23>: +8000086c: 01700e13 li t3,23 +80000870: 00000e93 li t4,0 +80000874: f00120b7 lui ra,0xf0012 +80000878: 00000113 li sp,0 +8000087c: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011588> +80000880: 00000013 nop +80000884: 00000013 nop +80000888: 00000013 nop +8000088c: 00000013 nop +80000890: 00000013 nop +80000894: 00000013 nop +80000898: 00000013 nop +8000089c: 00000013 nop +800008a0: 20000093 li ra,512 +800008a4: 1440b073 csrc sip,ra +800008a8: 344021f3 csrr gp,mip +800008ac: f00120b7 lui ra,0xf0012 +800008b0: 00100113 li sp,1 +800008b4: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011588> +800008b8: 00000013 nop +800008bc: 00000013 nop +800008c0: 00000013 nop +800008c4: 00000013 nop +800008c8: 00000013 nop +800008cc: 00000013 nop +800008d0: 00000013 nop +800008d4: 00000013 nop +800008d8: 20000093 li ra,512 +800008dc: 1440b073 csrc sip,ra +800008e0: 344021f3 csrr gp,mip +800008e4: f00120b7 lui ra,0xf0012 +800008e8: 00000113 li sp,0 +800008ec: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011588> +800008f0: 00000013 nop +800008f4: 00000013 nop +800008f8: 00000013 nop +800008fc: 00000013 nop +80000900: 00000013 nop +80000904: 00000013 nop +80000908: 00000013 nop +8000090c: 00000013 nop +80000910: 20000093 li ra,512 +80000914: 1440b073 csrc sip,ra +80000918: 344021f3 csrr gp,mip +8000091c: f00120b7 lui ra,0xf0012 +80000920: 00000113 li sp,0 +80000924: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011588> +80000928: 00000013 nop +8000092c: 00000013 nop +80000930: 00000013 nop +80000934: 00000013 nop +80000938: 00000013 nop +8000093c: 00000013 nop +80000940: 00000013 nop +80000944: 00000013 nop +80000948: 20000093 li ra,512 +8000094c: 1440a073 csrs sip,ra +80000950: 344021f3 csrr gp,mip +80000954: f00120b7 lui ra,0xf0012 +80000958: 00100113 li sp,1 +8000095c: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011588> +80000960: 00000013 nop +80000964: 00000013 nop +80000968: 00000013 nop +8000096c: 00000013 nop +80000970: 00000013 nop +80000974: 00000013 nop +80000978: 00000013 nop +8000097c: 00000013 nop +80000980: 20000093 li ra,512 +80000984: 1440a073 csrs sip,ra +80000988: 344021f3 csrr gp,mip +8000098c: f00120b7 lui ra,0xf0012 +80000990: 00000113 li sp,0 +80000994: 0020a023 sw sp,0(ra) # f0012000 <strap+0x70011588> +80000998: 00000013 nop +8000099c: 00000013 nop +800009a0: 00000013 nop +800009a4: 00000013 nop +800009a8: 00000013 nop +800009ac: 00000013 nop +800009b0: 00000013 nop +800009b4: 00000013 nop + +800009b8 <test24>: +800009b8: 01800e13 li t3,24 +800009bc: 00200093 li ra,2 +800009c0: 3040a073 csrs mie,ra +800009c4: 3440a073 csrs mip,ra +800009c8: 3000a073 csrs mstatus,ra +800009cc: 00100e93 li t4,1 +800009d0: 00000f17 auipc t5,0x0 +800009d4: 03cf0f13 addi t5,t5,60 # 80000a0c <test25> +800009d8: 000020b7 lui ra,0x2 +800009dc: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> +800009e0: 00001137 lui sp,0x1 +800009e4: 80010113 addi sp,sp,-2048 # 800 <_start-0x7ffff800> +800009e8: 3000b073 csrc mstatus,ra +800009ec: 30012073 csrs mstatus,sp +800009f0: 00000097 auipc ra,0x0 +800009f4: 01408093 addi ra,ra,20 # 80000a04 <test24_s> +800009f8: 34109073 csrw mepc,ra +800009fc: 30200073 mret +80000a00: 0280006f j 80000a28 <fail> + +80000a04 <test24_s>: +80000a04: 10500073 wfi +80000a08: 0200006f j 80000a28 <fail> + +80000a0c <test25>: +80000a0c: 01900e13 li t3,25 +80000a10: 00000f17 auipc t5,0x0 +80000a14: 014f0f13 addi t5,t5,20 # 80000a24 <test26> +80000a18: 30046073 csrsi mstatus,8 +80000a1c: 10500073 wfi +80000a20: 0080006f j 80000a28 <fail> + +80000a24 <test26>: +80000a24: 0100006f j 80000a34 <pass> + +80000a28 <fail>: +80000a28: f0100137 lui sp,0xf0100 +80000a2c: f2410113 addi sp,sp,-220 # f00fff24 <strap+0x700ff4ac> +80000a30: 01c12023 sw t3,0(sp) + +80000a34 <pass>: +80000a34: f0100137 lui sp,0xf0100 +80000a38: f2010113 addi sp,sp,-224 # f00fff20 <strap+0x700ff4a8> +80000a3c: 00012023 sw zero,0(sp) + +80000a40 <mtrap>: +80000a40: fe0e84e3 beqz t4,80000a28 <fail> +80000a44: 342020f3 csrr ra,mcause +80000a48: 341020f3 csrr ra,mepc +80000a4c: 300020f3 csrr ra,mstatus +80000a50: 343020f3 csrr ra,mbadaddr +80000a54: 08000093 li ra,128 +80000a58: 3000b073 csrc mstatus,ra +80000a5c: 00200093 li ra,2 +80000a60: fc1e8ae3 beq t4,ra,80000a34 <pass> +80000a64: 000020b7 lui ra,0x2 +80000a68: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> +80000a6c: 3000a073 csrs mstatus,ra +80000a70: 341f1073 csrw mepc,t5 +80000a74: 30200073 mret + +80000a78 <strap>: +80000a78: fa0e88e3 beqz t4,80000a28 <fail> +80000a7c: 142020f3 csrr ra,scause +80000a80: 141020f3 csrr ra,sepc +80000a84: 100020f3 csrr ra,sstatus +80000a88: 143020f3 csrr ra,sbadaddr +80000a8c: 00000073 ecall +80000a90: 00000013 nop +80000a94: 00000013 nop +80000a98: 00000013 nop +80000a9c: 00000013 nop +80000aa0: 00000013 nop +80000aa4: 00000013 nop diff --git a/VexRiscv/src/test/cpp/raw/deleg/build/deleg.hex b/VexRiscv/src/test/cpp/raw/deleg/build/deleg.hex new file mode 100644 index 0000000..9290e85 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/deleg/build/deleg.hex @@ -0,0 +1,174 @@ +:0200000480007A
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diff --git a/VexRiscv/src/test/cpp/raw/deleg/makefile b/VexRiscv/src/test/cpp/raw/deleg/makefile new file mode 100644 index 0000000..8f98b68 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/deleg/makefile @@ -0,0 +1,3 @@ +PROJ_NAME=deleg + +include ../common/asm.mk
\ No newline at end of file diff --git a/VexRiscv/src/test/cpp/raw/deleg/src/crt.S b/VexRiscv/src/test/cpp/raw/deleg/src/crt.S new file mode 100644 index 0000000..f88d13f --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/deleg/src/crt.S @@ -0,0 +1,399 @@ +.globl _start + +#define TEST_ID x28 +#define TRAP_OK x29 +#define TRAP_RET x30 + +#include "encoding.h" + +#define externalInterrupt(value) \ + li x1, 0xF0011000; \ + li x2, value; \ + sw x2, 0(x1); \ + nop; \ + nop; \ + nop; \ + nop; \ + nop; \ + nop; \ + nop; \ + nop; \ + + +#define externalInterruptS(value) \ + li x1, 0xF0012000; \ + li x2, value; \ + sw x2, 0(x1); \ + nop; \ + nop; \ + nop; \ + nop; \ + nop; \ + nop; \ + nop; \ + nop; \ + + + +#define delay() \ + li x1, 100; \ +1: \ + addi x1, x1, -1; \ + bgt x1, x0, 1b; \ + + +#define setPriv(value) \ + li x1, 3 << 11; \ + li x2, value << 11; \ + csrc mstatus, x1; \ + csrs mstatus, x2; \ + auipc x1, 0; \ + addi x1, x1, 20; \ + csrw mepc, x1; \ + mret; \ + j fail; \ + + +ROM_SUPER_0: + +_start: + li TRAP_OK, 1 + la x1, mtrap + csrw mtvec, x1 + la x1, strap + csrw stvec, x1 + externalInterrupt(0); + +test1: + li TEST_ID, 1 + la TRAP_RET, test2 + ecall + +test2: //simple ecall from user to machine + li TEST_ID, 2 + setPriv(0) + la TRAP_RET, test4 + ecall + j fail + +test3: //M mialigned load exception without deleg + li TEST_ID, 3 + la TRAP_RET, test4 + lw x1, 1(x0) + j fail +test4: //S mialigned load exception without deleg + li TEST_ID, 4 + setPriv(1) + la TRAP_RET, test5 + lw x1, 1(x0) + j fail +test5: //U mialigned load exception without deleg + li TEST_ID, 5 + setPriv(0) + la TRAP_RET, test6 + lw x1, 1(x0) + j fail + +test6: // set medeleg + li TEST_ID, 6 + li x1, 1 << CAUSE_MISALIGNED_LOAD + csrw medeleg, x1 + +test7: //machine mode exception + li TEST_ID, 7 + la TRAP_RET, test8 + lw x1, 1(x0) + j fail + +test8: //supervisor mode exception + li TEST_ID, 8 + la TRAP_RET, test9 + setPriv(1) + lw x1, 1(x0) + j fail + +test9: //user mode exception + li TEST_ID, 9 + la TRAP_RET, test10 + setPriv(0) + lw x1, 1(x0) + j fail + +test10: //M external interrupt + li TEST_ID, 10 + la TRAP_RET, test11 + externalInterrupt(0) + li x1, MSTATUS_MIE + csrw mstatus, x1 + li x1, 1 << 11 + csrw mie, x1 + externalInterrupt(1) + wfi + j fail + +test11: //S external interrupt + li TEST_ID, 11 + la TRAP_RET, test12 + externalInterrupt(0) + li x1, MSTATUS_MIE + csrw mstatus, x1 + li x1, 1 << 11 + csrw mie, x1 + setPriv(1) + externalInterrupt(1) + wfi + j fail + +test12: //U external interrupt + li TEST_ID, 12 + la TRAP_RET, test14 + externalInterrupt(0) + li x1, MSTATUS_MIE + csrw mstatus, x1 + li x1, 1 << 11 + csrw mie, x1 + setPriv(0) + externalInterrupt(1) + wfi + j fail + + + +test14: //M external interrupt S + li x1, MSTATUS_SIE + csrw sstatus, x1 + + li TEST_ID, 14 + la TRAP_RET, test15 + externalInterruptS(0) + li x1, MSTATUS_SIE + csrw mstatus, x1 + li x1, 1 << 9 + csrw mie, x1 + li TRAP_OK, 0 + externalInterruptS(1) + delay() + +test15: //S external interrupt S + li TEST_ID, 15 + la TRAP_RET, test16 + externalInterruptS(0) + li x1, SSTATUS_SIE + csrw mstatus, x1 + li x1, 1 << 9 + csrw mie, x1 + setPriv(1) + li TRAP_OK, 1 + externalInterruptS(1) + wfi + j fail + +test16: //U external interrupt S + li TEST_ID, 16 + la TRAP_RET, test17 + externalInterruptS(0) + li x1, SSTATUS_SIE + csrw mstatus, x1 + li x1, 1 << 9 + csrw mie, x1 + setPriv(0) + externalInterruptS(1) + wfi + j fail + + +test17:// set mideleg + li TEST_ID, 17 + li x1, 1 << 9 + csrw mideleg, x1 + + + la TRAP_RET, test18 + externalInterruptS(0) + li x1, MSTATUS_SIE + csrw mstatus, x1 + li x1, 1 << 9 + csrw mie, x1 + li TRAP_OK, 0 + externalInterruptS(1) + delay() + +test18: //S external interrupt S with deleg + li TEST_ID, 18 + la TRAP_RET, test19 + externalInterruptS(0) + li x1, SSTATUS_SIE + csrw mstatus, x1 + li x1, 1 << 9 + csrw mie, x1 + setPriv(1) + li TRAP_OK, 1 + externalInterruptS(1) + wfi + j fail + +test19: //U external interrupt S with deleg + li TEST_ID, 19 + la TRAP_RET, test20 + externalInterruptS(0) + li x1, SSTATUS_SIE + csrw mstatus, x1 + li x1, 1 << 9 + csrw mie, x1 + setPriv(0) + externalInterruptS(1) + wfi + j fail + + + + + +test20:// M external interrupt S by software with deleg + externalInterruptS(0) + li TEST_ID, 20 + la TRAP_RET, test21 + li x1, MSTATUS_SIE + csrw mstatus, x1 + li x1, 1 << 9 + csrw mie, x1 + li TRAP_OK, 0 + li x1, 1 << 9 + csrs sip, x1 + delay() + +test21: //S external interrupt S by software with deleg + li TEST_ID, 21 + la TRAP_RET, test22 + li x1, 1 << 9 + csrc sip, x1 + li x1, SSTATUS_SIE + csrw mstatus, x1 + li x1, 1 << 9 + csrw mie, x1 + setPriv(1) + li TRAP_OK, 1 + li x1, 1 << 9 + csrs sip, x1 + wfi + j fail + +test22: //U external interrupt S by software with deleg + li TEST_ID, 22 + la TRAP_RET, test23 + li x1, 1 << 9 + csrc sip, x1 + li x1, SSTATUS_SIE + csrw mstatus, x1 + li x1, 1 << 9 + csrw mie, x1 + li x1, 1 << 9 + csrs sip, x1 + setPriv(0) + wfi + j fail + + + +test23: //Test software and hardware setting inettrupt + li TEST_ID, 23 + li TRAP_OK, 0 + externalInterruptS(0) + li x1, 1 << 9 + csrc sip, x1 + csrr x3, mip + + + externalInterruptS(1) + li x1, 1 << 9 + csrc sip, x1 + csrr x3, mip + + + externalInterruptS(0) + li x1, 1 << 9 + csrc sip, x1 + csrr x3, mip + + + externalInterruptS(0) + li x1, 1 << 9 + csrs sip, x1 + csrr x3, mip + + + externalInterruptS(1) + li x1, 1 << 9 + csrs sip, x1 + csrr x3, mip + + externalInterruptS(0) + +test24: //test supervisor software interrupt + li TEST_ID, 24 + li x1, 2 + csrs mie, x1 + csrs mip, x1 + csrs mstatus, x1 + + li TRAP_OK, 1 + la TRAP_RET, test25 + setPriv(1) +test24_s: + wfi + j fail + + +test25: //test undelegated supervisor interrupt in machine mode (continue test24) + li TEST_ID, 25 + la TRAP_RET, test26 + csrsi mstatus, 1 << 3 //mie + wfi + j fail + + +test26: + + j pass + +fail: + li x2, 0xF00FFF24 + sw TEST_ID, 0(x2) + +pass: + li x2, 0xF00FFF20 + sw x0, 0(x2) + + +mtrap: + beq TRAP_OK, x0, fail + csrr x1, mcause + csrr x1, mepc + csrr x1, mstatus + csrr x1, mbadaddr + li x1, MSTATUS_MPIE + csrc mstatus, x1 + li x1, 2 + beq TRAP_OK, x1, pass + li x1, 3 << 11 + csrs mstatus, x1 + csrw mepc, TRAP_RET + mret + + +strap: + beq TRAP_OK, x0, fail + csrr x1, scause + csrr x1, sepc + csrr x1, sstatus + csrr x1, sbadaddr + ecall + + + + nop + nop + nop + nop + nop + nop diff --git a/VexRiscv/src/test/cpp/raw/deleg/src/encoding.h b/VexRiscv/src/test/cpp/raw/deleg/src/encoding.h new file mode 100644 index 0000000..c109ce1 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/deleg/src/encoding.h @@ -0,0 +1,1471 @@ +// See LICENSE for license details. + +#ifndef RISCV_CSR_ENCODING_H +#define RISCV_CSR_ENCODING_H + +#define MSTATUS_UIE 0x00000001 +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_HIE 0x00000004 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_UPIE 0x00000010 +#define MSTATUS_SPIE 0x00000020 +#define MSTATUS_HPIE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP 0x00000100 +#define MSTATUS_HPP 0x00000600 +#define MSTATUS_MPP 0x00001800 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_XS 0x00018000 +#define MSTATUS_MPRV 0x00020000 +#define MSTATUS_SUM 0x00040000 +#define MSTATUS_MXR 0x00080000 +#define MSTATUS_TVM 0x00100000 +#define MSTATUS_TW 0x00200000 +#define MSTATUS_TSR 0x00400000 +#define MSTATUS32_SD 0x80000000 +#define MSTATUS_UXL 0x0000000300000000 +#define MSTATUS_SXL 0x0000000C00000000 +#define MSTATUS64_SD 0x8000000000000000 + +#define SSTATUS_UIE 0x00000001 +#define SSTATUS_SIE 0x00000002 +#define SSTATUS_UPIE 0x00000010 +#define SSTATUS_SPIE 0x00000020 +#define SSTATUS_SPP 0x00000100 +#define SSTATUS_FS 0x00006000 +#define SSTATUS_XS 0x00018000 +#define SSTATUS_SUM 0x00040000 +#define SSTATUS_MXR 0x00080000 +#define SSTATUS32_SD 0x80000000 +#define SSTATUS_UXL 0x0000000300000000 +#define SSTATUS64_SD 0x8000000000000000 + +#define DCSR_XDEBUGVER (3U<<30) +#define DCSR_NDRESET (1<<29) +#define DCSR_FULLRESET (1<<28) +#define DCSR_EBREAKM (1<<15) +#define DCSR_EBREAKH (1<<14) +#define DCSR_EBREAKS (1<<13) +#define DCSR_EBREAKU (1<<12) +#define DCSR_STOPCYCLE (1<<10) +#define DCSR_STOPTIME (1<<9) +#define DCSR_CAUSE (7<<6) +#define DCSR_DEBUGINT (1<<5) +#define DCSR_HALT (1<<3) +#define DCSR_STEP (1<<2) +#define DCSR_PRV (3<<0) + +#define DCSR_CAUSE_NONE 0 +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HWBP 2 +#define DCSR_CAUSE_DEBUGINT 3 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_HALT 5 + +#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) +#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) +#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) + +#define MCONTROL_SELECT (1<<19) +#define MCONTROL_TIMING (1<<18) +#define MCONTROL_ACTION (0x3f<<12) +#define MCONTROL_CHAIN (1<<11) +#define MCONTROL_MATCH (0xf<<7) +#define MCONTROL_M (1<<6) +#define MCONTROL_H (1<<5) +#define MCONTROL_S (1<<4) +#define MCONTROL_U (1<<3) +#define MCONTROL_EXECUTE (1<<2) +#define MCONTROL_STORE (1<<1) +#define MCONTROL_LOAD (1<<0) + +#define MCONTROL_TYPE_NONE 0 +#define MCONTROL_TYPE_MATCH 2 + +#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 +#define MCONTROL_ACTION_DEBUG_MODE 1 +#define MCONTROL_ACTION_TRACE_START 2 +#define MCONTROL_ACTION_TRACE_STOP 3 +#define MCONTROL_ACTION_TRACE_EMIT 4 + +#define MCONTROL_MATCH_EQUAL 0 +#define MCONTROL_MATCH_NAPOT 1 +#define MCONTROL_MATCH_GE 2 +#define MCONTROL_MATCH_LT 3 +#define MCONTROL_MATCH_MASK_LOW 4 +#define MCONTROL_MATCH_MASK_HIGH 5 + +#define MIP_SSIP (1 << IRQ_S_SOFT) +#define MIP_HSIP (1 << IRQ_H_SOFT) +#define MIP_MSIP (1 << IRQ_M_SOFT) +#define MIP_STIP (1 << IRQ_S_TIMER) +#define MIP_HTIP (1 << IRQ_H_TIMER) +#define MIP_MTIP (1 << IRQ_M_TIMER) +#define MIP_SEIP (1 << IRQ_S_EXT) +#define MIP_HEIP (1 << IRQ_H_EXT) +#define MIP_MEIP (1 << IRQ_M_EXT) + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define PRV_U 0 +#define PRV_S 1 +#define PRV_H 2 +#define PRV_M 3 + +#define SATP32_MODE 0x80000000 +#define SATP32_ASID 0x7FC00000 +#define SATP32_PPN 0x003FFFFF +#define SATP64_MODE 0xF000000000000000 +#define SATP64_ASID 0x0FFFF00000000000 +#define SATP64_PPN 0x00000FFFFFFFFFFF + +#define SATP_MODE_OFF 0 +#define SATP_MODE_SV32 1 +#define SATP_MODE_SV39 8 +#define SATP_MODE_SV48 9 +#define SATP_MODE_SV57 10 +#define SATP_MODE_SV64 11 + +#define PMP_R 0x01 +#define PMP_W 0x02 +#define PMP_X 0x04 +#define PMP_A 0x18 +#define PMP_L 0x80 +#define PMP_SHIFT 2 + +#define PMP_TOR 0x08 +#define PMP_NA4 0x10 +#define PMP_NAPOT 0x18 + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#define DEFAULT_RSTVEC 0x00001000 +#define CLINT_BASE 0x02000000 +#define CLINT_SIZE 0x000c0000 +#define EXT_IO_BASE 0x40000000 +#define DRAM_BASE 0x80000000 + +// page table entry (PTE) fields +#define PTE_V 0x001 // Valid +#define PTE_R 0x002 // Read +#define PTE_W 0x004 // Write +#define PTE_X 0x008 // Execute +#define PTE_U 0x010 // User +#define PTE_G 0x020 // Global +#define PTE_A 0x040 // Accessed +#define PTE_D 0x080 // Dirty +#define PTE_SOFT 0x300 // Reserved for Software + +#define PTE_PPN_SHIFT 10 + +#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) + +#ifdef __riscv + +#if __riscv_xlen == 64 +# define MSTATUS_SD MSTATUS64_SD +# define SSTATUS_SD SSTATUS64_SD +# define RISCV_PGLEVEL_BITS 9 +# define SATP_MODE SATP64_MODE +#else +# define MSTATUS_SD MSTATUS32_SD +# define SSTATUS_SD SSTATUS32_SD +# define RISCV_PGLEVEL_BITS 10 +# define SATP_MODE SATP32_MODE +#endif +#define RISCV_PGSHIFT 12 +#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) + +#ifndef __ASSEMBLER__ + +#ifdef __GNUC__ + +#define read_csr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_csr(reg, val) ({ \ + asm volatile ("csrw " #reg ", %0" :: "rK"(val)); }) + +#define swap_csr(reg, val) ({ unsigned long __tmp; \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ + __tmp; }) + +#define set_csr(reg, bit) ({ unsigned long __tmp; \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; }) + +#define clear_csr(reg, bit) ({ unsigned long __tmp; \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; }) + +#define rdtime() read_csr(time) +#define rdcycle() read_csr(cycle) +#define rdinstret() read_csr(instret) + +#endif + +#endif + +#endif + +#endif +/* Automatically generated by parse-opcodes. */ +#ifndef RISCV_ENCODING_H +#define RISCV_ENCODING_H +#define MATCH_BEQ 0x63 +#define MASK_BEQ 0x707f +#define MATCH_BNE 0x1063 +#define MASK_BNE 0x707f +#define MATCH_BLT 0x4063 +#define MASK_BLT 0x707f +#define MATCH_BGE 0x5063 +#define MASK_BGE 0x707f +#define MATCH_BLTU 0x6063 +#define MASK_BLTU 0x707f +#define MATCH_BGEU 0x7063 +#define MASK_BGEU 0x707f +#define MATCH_JALR 0x67 +#define MASK_JALR 0x707f +#define MATCH_JAL 0x6f +#define MASK_JAL 0x7f +#define MATCH_LUI 0x37 +#define MASK_LUI 0x7f +#define MATCH_AUIPC 0x17 +#define MASK_AUIPC 0x7f +#define MATCH_ADDI 0x13 +#define MASK_ADDI 0x707f +#define MATCH_SLLI 0x1013 +#define MASK_SLLI 0xfc00707f +#define MATCH_SLTI 0x2013 +#define MASK_SLTI 0x707f +#define MATCH_SLTIU 0x3013 +#define MASK_SLTIU 0x707f +#define MATCH_XORI 0x4013 +#define MASK_XORI 0x707f +#define MATCH_SRLI 0x5013 +#define MASK_SRLI 0xfc00707f +#define MATCH_SRAI 0x40005013 +#define MASK_SRAI 0xfc00707f +#define MATCH_ORI 0x6013 +#define MASK_ORI 0x707f +#define MATCH_ANDI 0x7013 +#define MASK_ANDI 0x707f +#define MATCH_ADD 0x33 +#define MASK_ADD 0xfe00707f +#define MATCH_SUB 0x40000033 +#define MASK_SUB 0xfe00707f +#define MATCH_SLL 0x1033 +#define MASK_SLL 0xfe00707f +#define MATCH_SLT 0x2033 +#define MASK_SLT 0xfe00707f +#define MATCH_SLTU 0x3033 +#define MASK_SLTU 0xfe00707f +#define MATCH_XOR 0x4033 +#define MASK_XOR 0xfe00707f +#define MATCH_SRL 0x5033 +#define MASK_SRL 0xfe00707f +#define MATCH_SRA 0x40005033 +#define MASK_SRA 0xfe00707f +#define MATCH_OR 0x6033 +#define MASK_OR 0xfe00707f +#define MATCH_AND 0x7033 +#define MASK_AND 0xfe00707f +#define MATCH_ADDIW 0x1b +#define MASK_ADDIW 0x707f +#define MATCH_SLLIW 0x101b +#define MASK_SLLIW 0xfe00707f +#define MATCH_SRLIW 0x501b +#define MASK_SRLIW 0xfe00707f +#define MATCH_SRAIW 0x4000501b +#define MASK_SRAIW 0xfe00707f +#define MATCH_ADDW 0x3b +#define MASK_ADDW 0xfe00707f +#define MATCH_SUBW 0x4000003b +#define MASK_SUBW 0xfe00707f +#define MATCH_SLLW 0x103b +#define MASK_SLLW 0xfe00707f +#define MATCH_SRLW 0x503b +#define MASK_SRLW 0xfe00707f +#define MATCH_SRAW 0x4000503b +#define MASK_SRAW 0xfe00707f +#define MATCH_LB 0x3 +#define MASK_LB 0x707f +#define MATCH_LH 0x1003 +#define MASK_LH 0x707f +#define MATCH_LW 0x2003 +#define MASK_LW 0x707f +#define MATCH_LD 0x3003 +#define MASK_LD 0x707f +#define MATCH_LBU 0x4003 +#define MASK_LBU 0x707f +#define MATCH_LHU 0x5003 +#define MASK_LHU 0x707f +#define MATCH_LWU 0x6003 +#define MASK_LWU 0x707f +#define MATCH_SB 0x23 +#define MASK_SB 0x707f +#define MATCH_SH 0x1023 +#define MASK_SH 0x707f +#define MATCH_SW 0x2023 +#define MASK_SW 0x707f +#define MATCH_SD 0x3023 +#define MASK_SD 0x707f +#define MATCH_FENCE 0xf +#define MASK_FENCE 0x707f +#define MATCH_FENCE_I 0x100f +#define MASK_FENCE_I 0x707f +#define MATCH_MUL 0x2000033 +#define MASK_MUL 0xfe00707f +#define MATCH_MULH 0x2001033 +#define MASK_MULH 0xfe00707f +#define MATCH_MULHSU 0x2002033 +#define MASK_MULHSU 0xfe00707f +#define MATCH_MULHU 0x2003033 +#define MASK_MULHU 0xfe00707f +#define MATCH_DIV 0x2004033 +#define MASK_DIV 0xfe00707f +#define MATCH_DIVU 0x2005033 +#define MASK_DIVU 0xfe00707f +#define MATCH_REM 0x2006033 +#define MASK_REM 0xfe00707f +#define MATCH_REMU 0x2007033 +#define MASK_REMU 0xfe00707f +#define MATCH_MULW 0x200003b +#define MASK_MULW 0xfe00707f +#define MATCH_DIVW 0x200403b +#define MASK_DIVW 0xfe00707f +#define MATCH_DIVUW 0x200503b +#define MASK_DIVUW 0xfe00707f +#define MATCH_REMW 0x200603b +#define MASK_REMW 0xfe00707f +#define MATCH_REMUW 0x200703b +#define MASK_REMUW 0xfe00707f +#define MATCH_AMOADD_W 0x202f +#define MASK_AMOADD_W 0xf800707f +#define MATCH_AMOXOR_W 0x2000202f +#define MASK_AMOXOR_W 0xf800707f +#define MATCH_AMOOR_W 0x4000202f +#define MASK_AMOOR_W 0xf800707f +#define MATCH_AMOAND_W 0x6000202f +#define MASK_AMOAND_W 0xf800707f +#define MATCH_AMOMIN_W 0x8000202f +#define MASK_AMOMIN_W 0xf800707f +#define MATCH_AMOMAX_W 0xa000202f +#define MASK_AMOMAX_W 0xf800707f +#define MATCH_AMOMINU_W 0xc000202f +#define MASK_AMOMINU_W 0xf800707f +#define MATCH_AMOMAXU_W 0xe000202f +#define MASK_AMOMAXU_W 0xf800707f +#define MATCH_AMOSWAP_W 0x800202f +#define MASK_AMOSWAP_W 0xf800707f +#define MATCH_LR_W 0x1000202f +#define MASK_LR_W 0xf9f0707f +#define MATCH_SC_W 0x1800202f +#define MASK_SC_W 0xf800707f +#define MATCH_AMOADD_D 0x302f +#define MASK_AMOADD_D 0xf800707f +#define MATCH_AMOXOR_D 0x2000302f +#define MASK_AMOXOR_D 0xf800707f +#define MATCH_AMOOR_D 0x4000302f +#define MASK_AMOOR_D 0xf800707f +#define MATCH_AMOAND_D 0x6000302f +#define MASK_AMOAND_D 0xf800707f +#define MATCH_AMOMIN_D 0x8000302f +#define MASK_AMOMIN_D 0xf800707f +#define MATCH_AMOMAX_D 0xa000302f +#define MASK_AMOMAX_D 0xf800707f +#define MATCH_AMOMINU_D 0xc000302f +#define MASK_AMOMINU_D 0xf800707f +#define MATCH_AMOMAXU_D 0xe000302f +#define MASK_AMOMAXU_D 0xf800707f +#define MATCH_AMOSWAP_D 0x800302f +#define MASK_AMOSWAP_D 0xf800707f +#define MATCH_LR_D 0x1000302f +#define MASK_LR_D 0xf9f0707f +#define MATCH_SC_D 0x1800302f +#define MASK_SC_D 0xf800707f +#define MATCH_ECALL 0x73 +#define MASK_ECALL 0xffffffff +#define MATCH_EBREAK 0x100073 +#define MASK_EBREAK 0xffffffff +#define MATCH_URET 0x200073 +#define MASK_URET 0xffffffff +#define MATCH_SRET 0x10200073 +#define MASK_SRET 0xffffffff +#define MATCH_MRET 0x30200073 +#define MASK_MRET 0xffffffff +#define MATCH_DRET 0x7b200073 +#define MASK_DRET 0xffffffff +#define MATCH_SFENCE_VMA 0x12000073 +#define MASK_SFENCE_VMA 0xfe007fff +#define MATCH_WFI 0x10500073 +#define MASK_WFI 0xffffffff +#define MATCH_CSRRW 0x1073 +#define MASK_CSRRW 0x707f +#define MATCH_CSRRS 0x2073 +#define MASK_CSRRS 0x707f +#define MATCH_CSRRC 0x3073 +#define MASK_CSRRC 0x707f +#define MATCH_CSRRWI 0x5073 +#define MASK_CSRRWI 0x707f +#define MATCH_CSRRSI 0x6073 +#define MASK_CSRRSI 0x707f +#define MATCH_CSRRCI 0x7073 +#define MASK_CSRRCI 0x707f +#define MATCH_FADD_S 0x53 +#define MASK_FADD_S 0xfe00007f +#define MATCH_FSUB_S 0x8000053 +#define MASK_FSUB_S 0xfe00007f +#define MATCH_FMUL_S 0x10000053 +#define MASK_FMUL_S 0xfe00007f +#define MATCH_FDIV_S 0x18000053 +#define MASK_FDIV_S 0xfe00007f +#define MATCH_FSGNJ_S 0x20000053 +#define MASK_FSGNJ_S 0xfe00707f +#define MATCH_FSGNJN_S 0x20001053 +#define MASK_FSGNJN_S 0xfe00707f +#define MATCH_FSGNJX_S 0x20002053 +#define MASK_FSGNJX_S 0xfe00707f +#define MATCH_FMIN_S 0x28000053 +#define MASK_FMIN_S 0xfe00707f +#define MATCH_FMAX_S 0x28001053 +#define MASK_FMAX_S 0xfe00707f +#define MATCH_FSQRT_S 0x58000053 +#define MASK_FSQRT_S 0xfff0007f +#define MATCH_FADD_D 0x2000053 +#define MASK_FADD_D 0xfe00007f +#define MATCH_FSUB_D 0xa000053 +#define MASK_FSUB_D 0xfe00007f +#define MATCH_FMUL_D 0x12000053 +#define MASK_FMUL_D 0xfe00007f +#define MATCH_FDIV_D 0x1a000053 +#define MASK_FDIV_D 0xfe00007f +#define MATCH_FSGNJ_D 0x22000053 +#define MASK_FSGNJ_D 0xfe00707f +#define MATCH_FSGNJN_D 0x22001053 +#define MASK_FSGNJN_D 0xfe00707f +#define MATCH_FSGNJX_D 0x22002053 +#define MASK_FSGNJX_D 0xfe00707f +#define MATCH_FMIN_D 0x2a000053 +#define MASK_FMIN_D 0xfe00707f +#define MATCH_FMAX_D 0x2a001053 +#define MASK_FMAX_D 0xfe00707f +#define MATCH_FCVT_S_D 0x40100053 +#define MASK_FCVT_S_D 0xfff0007f +#define MATCH_FCVT_D_S 0x42000053 +#define MASK_FCVT_D_S 0xfff0007f +#define MATCH_FSQRT_D 0x5a000053 +#define MASK_FSQRT_D 0xfff0007f +#define MATCH_FADD_Q 0x6000053 +#define MASK_FADD_Q 0xfe00007f +#define MATCH_FSUB_Q 0xe000053 +#define MASK_FSUB_Q 0xfe00007f +#define MATCH_FMUL_Q 0x16000053 +#define MASK_FMUL_Q 0xfe00007f +#define MATCH_FDIV_Q 0x1e000053 +#define MASK_FDIV_Q 0xfe00007f +#define MATCH_FSGNJ_Q 0x26000053 +#define MASK_FSGNJ_Q 0xfe00707f +#define MATCH_FSGNJN_Q 0x26001053 +#define MASK_FSGNJN_Q 0xfe00707f +#define MATCH_FSGNJX_Q 0x26002053 +#define MASK_FSGNJX_Q 0xfe00707f +#define MATCH_FMIN_Q 0x2e000053 +#define MASK_FMIN_Q 0xfe00707f +#define MATCH_FMAX_Q 0x2e001053 +#define MASK_FMAX_Q 0xfe00707f +#define MATCH_FCVT_S_Q 0x40300053 +#define MASK_FCVT_S_Q 0xfff0007f +#define MATCH_FCVT_Q_S 0x46000053 +#define MASK_FCVT_Q_S 0xfff0007f +#define MATCH_FCVT_D_Q 0x42300053 +#define MASK_FCVT_D_Q 0xfff0007f +#define MATCH_FCVT_Q_D 0x46100053 +#define MASK_FCVT_Q_D 0xfff0007f +#define MATCH_FSQRT_Q 0x5e000053 +#define MASK_FSQRT_Q 0xfff0007f +#define MATCH_FLE_S 0xa0000053 +#define MASK_FLE_S 0xfe00707f +#define MATCH_FLT_S 0xa0001053 +#define MASK_FLT_S 0xfe00707f +#define MATCH_FEQ_S 0xa0002053 +#define MASK_FEQ_S 0xfe00707f +#define MATCH_FLE_D 0xa2000053 +#define MASK_FLE_D 0xfe00707f +#define MATCH_FLT_D 0xa2001053 +#define MASK_FLT_D 0xfe00707f +#define MATCH_FEQ_D 0xa2002053 +#define MASK_FEQ_D 0xfe00707f +#define MATCH_FLE_Q 0xa6000053 +#define MASK_FLE_Q 0xfe00707f +#define MATCH_FLT_Q 0xa6001053 +#define MASK_FLT_Q 0xfe00707f +#define MATCH_FEQ_Q 0xa6002053 +#define MASK_FEQ_Q 0xfe00707f +#define MATCH_FCVT_W_S 0xc0000053 +#define MASK_FCVT_W_S 0xfff0007f +#define MATCH_FCVT_WU_S 0xc0100053 +#define MASK_FCVT_WU_S 0xfff0007f +#define MATCH_FCVT_L_S 0xc0200053 +#define MASK_FCVT_L_S 0xfff0007f +#define MATCH_FCVT_LU_S 0xc0300053 +#define MASK_FCVT_LU_S 0xfff0007f +#define MATCH_FMV_X_W 0xe0000053 +#define MASK_FMV_X_W 0xfff0707f +#define MATCH_FCLASS_S 0xe0001053 +#define MASK_FCLASS_S 0xfff0707f +#define MATCH_FCVT_W_D 0xc2000053 +#define MASK_FCVT_W_D 0xfff0007f +#define MATCH_FCVT_WU_D 0xc2100053 +#define MASK_FCVT_WU_D 0xfff0007f +#define MATCH_FCVT_L_D 0xc2200053 +#define MASK_FCVT_L_D 0xfff0007f +#define MATCH_FCVT_LU_D 0xc2300053 +#define MASK_FCVT_LU_D 0xfff0007f +#define MATCH_FMV_X_D 0xe2000053 +#define MASK_FMV_X_D 0xfff0707f +#define MATCH_FCLASS_D 0xe2001053 +#define MASK_FCLASS_D 0xfff0707f +#define MATCH_FCVT_W_Q 0xc6000053 +#define MASK_FCVT_W_Q 0xfff0007f +#define MATCH_FCVT_WU_Q 0xc6100053 +#define MASK_FCVT_WU_Q 0xfff0007f +#define MATCH_FCVT_L_Q 0xc6200053 +#define MASK_FCVT_L_Q 0xfff0007f +#define MATCH_FCVT_LU_Q 0xc6300053 +#define MASK_FCVT_LU_Q 0xfff0007f +#define MATCH_FMV_X_Q 0xe6000053 +#define MASK_FMV_X_Q 0xfff0707f +#define MATCH_FCLASS_Q 0xe6001053 +#define MASK_FCLASS_Q 0xfff0707f +#define MATCH_FCVT_S_W 0xd0000053 +#define MASK_FCVT_S_W 0xfff0007f +#define MATCH_FCVT_S_WU 0xd0100053 +#define MASK_FCVT_S_WU 0xfff0007f +#define MATCH_FCVT_S_L 0xd0200053 +#define MASK_FCVT_S_L 0xfff0007f +#define MATCH_FCVT_S_LU 0xd0300053 +#define MASK_FCVT_S_LU 0xfff0007f +#define MATCH_FMV_W_X 0xf0000053 +#define MASK_FMV_W_X 0xfff0707f +#define MATCH_FCVT_D_W 0xd2000053 +#define MASK_FCVT_D_W 0xfff0007f +#define MATCH_FCVT_D_WU 0xd2100053 +#define MASK_FCVT_D_WU 0xfff0007f +#define MATCH_FCVT_D_L 0xd2200053 +#define MASK_FCVT_D_L 0xfff0007f +#define MATCH_FCVT_D_LU 0xd2300053 +#define MASK_FCVT_D_LU 0xfff0007f +#define MATCH_FMV_D_X 0xf2000053 +#define MASK_FMV_D_X 0xfff0707f +#define MATCH_FCVT_Q_W 0xd6000053 +#define MASK_FCVT_Q_W 0xfff0007f +#define MATCH_FCVT_Q_WU 0xd6100053 +#define MASK_FCVT_Q_WU 0xfff0007f +#define MATCH_FCVT_Q_L 0xd6200053 +#define MASK_FCVT_Q_L 0xfff0007f +#define MATCH_FCVT_Q_LU 0xd6300053 +#define MASK_FCVT_Q_LU 0xfff0007f +#define MATCH_FMV_Q_X 0xf6000053 +#define MASK_FMV_Q_X 0xfff0707f +#define MATCH_FLW 0x2007 +#define MASK_FLW 0x707f +#define MATCH_FLD 0x3007 +#define MASK_FLD 0x707f +#define MATCH_FLQ 0x4007 +#define MASK_FLQ 0x707f +#define MATCH_FSW 0x2027 +#define MASK_FSW 0x707f +#define MATCH_FSD 0x3027 +#define MASK_FSD 0x707f +#define MATCH_FSQ 0x4027 +#define MASK_FSQ 0x707f +#define MATCH_FMADD_S 0x43 +#define MASK_FMADD_S 0x600007f +#define MATCH_FMSUB_S 0x47 +#define MASK_FMSUB_S 0x600007f +#define MATCH_FNMSUB_S 0x4b +#define MASK_FNMSUB_S 0x600007f +#define MATCH_FNMADD_S 0x4f +#define MASK_FNMADD_S 0x600007f +#define MATCH_FMADD_D 0x2000043 +#define MASK_FMADD_D 0x600007f +#define MATCH_FMSUB_D 0x2000047 +#define MASK_FMSUB_D 0x600007f +#define MATCH_FNMSUB_D 0x200004b +#define MASK_FNMSUB_D 0x600007f +#define MATCH_FNMADD_D 0x200004f +#define MASK_FNMADD_D 0x600007f +#define MATCH_FMADD_Q 0x6000043 +#define MASK_FMADD_Q 0x600007f +#define MATCH_FMSUB_Q 0x6000047 +#define MASK_FMSUB_Q 0x600007f +#define MATCH_FNMSUB_Q 0x600004b +#define MASK_FNMSUB_Q 0x600007f +#define MATCH_FNMADD_Q 0x600004f +#define MASK_FNMADD_Q 0x600007f +#define MATCH_C_NOP 0x1 +#define MASK_C_NOP 0xffff +#define MATCH_C_ADDI16SP 0x6101 +#define MASK_C_ADDI16SP 0xef83 +#define MATCH_C_JR 0x8002 +#define MASK_C_JR 0xf07f +#define MATCH_C_JALR 0x9002 +#define MASK_C_JALR 0xf07f +#define MATCH_C_EBREAK 0x9002 +#define MASK_C_EBREAK 0xffff +#define MATCH_C_LD 0x6000 +#define MASK_C_LD 0xe003 +#define MATCH_C_SD 0xe000 +#define MASK_C_SD 0xe003 +#define MATCH_C_ADDIW 0x2001 +#define MASK_C_ADDIW 0xe003 +#define MATCH_C_LDSP 0x6002 +#define MASK_C_LDSP 0xe003 +#define MATCH_C_SDSP 0xe002 +#define MASK_C_SDSP 0xe003 +#define MATCH_C_ADDI4SPN 0x0 +#define MASK_C_ADDI4SPN 0xe003 +#define MATCH_C_FLD 0x2000 +#define MASK_C_FLD 0xe003 +#define MATCH_C_LW 0x4000 +#define MASK_C_LW 0xe003 +#define MATCH_C_FLW 0x6000 +#define MASK_C_FLW 0xe003 +#define MATCH_C_FSD 0xa000 +#define MASK_C_FSD 0xe003 +#define MATCH_C_SW 0xc000 +#define MASK_C_SW 0xe003 +#define MATCH_C_FSW 0xe000 +#define MASK_C_FSW 0xe003 +#define MATCH_C_ADDI 0x1 +#define MASK_C_ADDI 0xe003 +#define MATCH_C_JAL 0x2001 +#define MASK_C_JAL 0xe003 +#define MATCH_C_LI 0x4001 +#define MASK_C_LI 0xe003 +#define MATCH_C_LUI 0x6001 +#define MASK_C_LUI 0xe003 +#define MATCH_C_SRLI 0x8001 +#define MASK_C_SRLI 0xec03 +#define MATCH_C_SRAI 0x8401 +#define MASK_C_SRAI 0xec03 +#define MATCH_C_ANDI 0x8801 +#define MASK_C_ANDI 0xec03 +#define MATCH_C_SUB 0x8c01 +#define MASK_C_SUB 0xfc63 +#define MATCH_C_XOR 0x8c21 +#define MASK_C_XOR 0xfc63 +#define MATCH_C_OR 0x8c41 +#define MASK_C_OR 0xfc63 +#define MATCH_C_AND 0x8c61 +#define MASK_C_AND 0xfc63 +#define MATCH_C_SUBW 0x9c01 +#define MASK_C_SUBW 0xfc63 +#define MATCH_C_ADDW 0x9c21 +#define MASK_C_ADDW 0xfc63 +#define MATCH_C_J 0xa001 +#define MASK_C_J 0xe003 +#define MATCH_C_BEQZ 0xc001 +#define MASK_C_BEQZ 0xe003 +#define MATCH_C_BNEZ 0xe001 +#define MASK_C_BNEZ 0xe003 +#define MATCH_C_SLLI 0x2 +#define MASK_C_SLLI 0xe003 +#define MATCH_C_FLDSP 0x2002 +#define MASK_C_FLDSP 0xe003 +#define MATCH_C_LWSP 0x4002 +#define MASK_C_LWSP 0xe003 +#define MATCH_C_FLWSP 0x6002 +#define MASK_C_FLWSP 0xe003 +#define MATCH_C_MV 0x8002 +#define MASK_C_MV 0xf003 +#define MATCH_C_ADD 0x9002 +#define MASK_C_ADD 0xf003 +#define MATCH_C_FSDSP 0xa002 +#define MASK_C_FSDSP 0xe003 +#define MATCH_C_SWSP 0xc002 +#define MASK_C_SWSP 0xe003 +#define MATCH_C_FSWSP 0xe002 +#define MASK_C_FSWSP 0xe003 +#define MATCH_CUSTOM0 0xb +#define MASK_CUSTOM0 0x707f +#define MATCH_CUSTOM0_RS1 0x200b +#define MASK_CUSTOM0_RS1 0x707f +#define MATCH_CUSTOM0_RS1_RS2 0x300b +#define MASK_CUSTOM0_RS1_RS2 0x707f +#define MATCH_CUSTOM0_RD 0x400b +#define MASK_CUSTOM0_RD 0x707f +#define MATCH_CUSTOM0_RD_RS1 0x600b +#define MASK_CUSTOM0_RD_RS1 0x707f +#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b +#define MASK_CUSTOM0_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM1 0x2b +#define MASK_CUSTOM1 0x707f +#define MATCH_CUSTOM1_RS1 0x202b +#define MASK_CUSTOM1_RS1 0x707f +#define MATCH_CUSTOM1_RS1_RS2 0x302b +#define MASK_CUSTOM1_RS1_RS2 0x707f +#define MATCH_CUSTOM1_RD 0x402b +#define MASK_CUSTOM1_RD 0x707f +#define MATCH_CUSTOM1_RD_RS1 0x602b +#define MASK_CUSTOM1_RD_RS1 0x707f +#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b +#define MASK_CUSTOM1_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM2 0x5b +#define MASK_CUSTOM2 0x707f +#define MATCH_CUSTOM2_RS1 0x205b +#define MASK_CUSTOM2_RS1 0x707f +#define MATCH_CUSTOM2_RS1_RS2 0x305b +#define MASK_CUSTOM2_RS1_RS2 0x707f +#define MATCH_CUSTOM2_RD 0x405b +#define MASK_CUSTOM2_RD 0x707f +#define MATCH_CUSTOM2_RD_RS1 0x605b +#define MASK_CUSTOM2_RD_RS1 0x707f +#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b +#define MASK_CUSTOM2_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM3 0x7b +#define MASK_CUSTOM3 0x707f +#define MATCH_CUSTOM3_RS1 0x207b +#define MASK_CUSTOM3_RS1 0x707f +#define MATCH_CUSTOM3_RS1_RS2 0x307b +#define MASK_CUSTOM3_RS1_RS2 0x707f +#define MATCH_CUSTOM3_RD 0x407b +#define MASK_CUSTOM3_RD 0x707f +#define MATCH_CUSTOM3_RD_RS1 0x607b +#define MASK_CUSTOM3_RD_RS1 0x707f +#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b +#define MASK_CUSTOM3_RD_RS1_RS2 0x707f +#define CSR_FFLAGS 0x1 +#define CSR_FRM 0x2 +#define CSR_FCSR 0x3 +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SCOUNTEREN 0x106 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 +#define CSR_SATP 0x180 +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MCOUNTEREN 0x306 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MTVAL 0x343 +#define CSR_MIP 0x344 +#define CSR_PMPCFG0 0x3a0 +#define CSR_PMPCFG1 0x3a1 +#define CSR_PMPCFG2 0x3a2 +#define CSR_PMPCFG3 0x3a3 +#define CSR_PMPADDR0 0x3b0 +#define CSR_PMPADDR1 0x3b1 +#define CSR_PMPADDR2 0x3b2 +#define CSR_PMPADDR3 0x3b3 +#define CSR_PMPADDR4 0x3b4 +#define CSR_PMPADDR5 0x3b5 +#define CSR_PMPADDR6 0x3b6 +#define CSR_PMPADDR7 0x3b7 +#define CSR_PMPADDR8 0x3b8 +#define CSR_PMPADDR9 0x3b9 +#define CSR_PMPADDR10 0x3ba +#define CSR_PMPADDR11 0x3bb +#define CSR_PMPADDR12 0x3bc +#define CSR_PMPADDR13 0x3bd +#define CSR_PMPADDR14 0x3be +#define CSR_PMPADDR15 0x3bf +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH 0x7b2 +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FETCH_ACCESS 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_LOAD_ACCESS 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_STORE_ACCESS 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_HYPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#define CAUSE_FETCH_PAGE_FAULT 0xc +#define CAUSE_LOAD_PAGE_FAULT 0xd +#define CAUSE_STORE_PAGE_FAULT 0xf +#endif +#ifdef DECLARE_INSN +DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) +DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) +DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) +DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) +DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) +DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) +DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) +DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) +DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) +DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) +DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) +DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) +DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) +DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) +DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) +DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) +DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) +DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) +DECLARE_INSN(add, MATCH_ADD, MASK_ADD) +DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) +DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) +DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) +DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) +DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) +DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) +DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) +DECLARE_INSN(or, MATCH_OR, MASK_OR) +DECLARE_INSN(and, MATCH_AND, MASK_AND) +DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) +DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) +DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) +DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) +DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) +DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) +DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) +DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) +DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) +DECLARE_INSN(lb, MATCH_LB, MASK_LB) +DECLARE_INSN(lh, MATCH_LH, MASK_LH) +DECLARE_INSN(lw, MATCH_LW, MASK_LW) +DECLARE_INSN(ld, MATCH_LD, MASK_LD) +DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) +DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) +DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) +DECLARE_INSN(sb, MATCH_SB, MASK_SB) +DECLARE_INSN(sh, MATCH_SH, MASK_SH) +DECLARE_INSN(sw, MATCH_SW, MASK_SW) +DECLARE_INSN(sd, MATCH_SD, MASK_SD) +DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) +DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) +DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) +DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) +DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) +DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) +DECLARE_INSN(div, MATCH_DIV, MASK_DIV) +DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) +DECLARE_INSN(rem, MATCH_REM, MASK_REM) +DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) +DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) +DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) +DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) +DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) +DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) +DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) +DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) +DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) +DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) +DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) +DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) +DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) +DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) +DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) +DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) +DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) +DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) +DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) +DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) +DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) +DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) +DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) +DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) +DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) +DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) +DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) +DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) +DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) +DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) +DECLARE_INSN(uret, MATCH_URET, MASK_URET) +DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) +DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) +DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) +DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) +DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) +DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) +DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) +DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) +DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) +DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) +DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) +DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) +DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) +DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) +DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) +DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) +DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) +DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) +DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) +DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) +DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) +DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) +DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) +DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) +DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) +DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) +DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) +DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) +DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) +DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) +DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) +DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) +DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) +DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q) +DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q) +DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q) +DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q) +DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q) +DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q) +DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q) +DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q) +DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q) +DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q) +DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S) +DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q) +DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D) +DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q) +DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) +DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) +DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) +DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) +DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) +DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) +DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q) +DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q) +DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q) +DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) +DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) +DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) +DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) +DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W) +DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) +DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) +DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) +DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) +DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) +DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) +DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) +DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q) +DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q) +DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q) +DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q) +DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q) +DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q) +DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) +DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) +DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) +DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) +DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X) +DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) +DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) +DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) +DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) +DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) +DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W) +DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU) +DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L) +DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU) +DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X) +DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) +DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) +DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ) +DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) +DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) +DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ) +DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) +DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) +DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) +DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) +DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) +DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) +DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) +DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) +DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q) +DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q) +DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q) +DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q) +DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) +DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) +DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) +DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) +DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) +DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) +DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) +DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) +DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) +DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) +DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) +DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) +DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) +DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) +DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) +DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) +DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) +DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) +DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) +DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) +DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) +DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) +DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) +DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) +DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) +DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) +DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) +DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) +DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) +DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) +DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) +DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) +DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) +DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) +DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) +DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) +DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) +DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) +DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) +DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) +DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) +DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) +DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) +DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) +DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) +DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) +DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) +DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) +DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) +DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) +DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) +DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) +DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) +DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) +DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) +DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) +DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) +DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) +DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) +DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) +DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) +DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) +DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) +DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) +DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) +DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) +#endif +#ifdef DECLARE_CSR +DECLARE_CSR(fflags, CSR_FFLAGS) +DECLARE_CSR(frm, CSR_FRM) +DECLARE_CSR(fcsr, CSR_FCSR) +DECLARE_CSR(cycle, CSR_CYCLE) +DECLARE_CSR(time, CSR_TIME) +DECLARE_CSR(instret, CSR_INSTRET) +DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) +DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) +DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) +DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) +DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) +DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) +DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) +DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) +DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) +DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) +DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) +DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) +DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) +DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) +DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) +DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) +DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) +DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) +DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) +DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) +DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) +DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) +DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) +DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) +DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) +DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) +DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) +DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) +DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) +DECLARE_CSR(sstatus, CSR_SSTATUS) +DECLARE_CSR(sie, CSR_SIE) +DECLARE_CSR(stvec, CSR_STVEC) +DECLARE_CSR(scounteren, CSR_SCOUNTEREN) +DECLARE_CSR(sscratch, CSR_SSCRATCH) +DECLARE_CSR(sepc, CSR_SEPC) +DECLARE_CSR(scause, CSR_SCAUSE) +DECLARE_CSR(stval, CSR_STVAL) +DECLARE_CSR(sip, CSR_SIP) +DECLARE_CSR(satp, CSR_SATP) +DECLARE_CSR(mstatus, CSR_MSTATUS) +DECLARE_CSR(misa, CSR_MISA) +DECLARE_CSR(medeleg, CSR_MEDELEG) +DECLARE_CSR(mideleg, CSR_MIDELEG) +DECLARE_CSR(mie, CSR_MIE) +DECLARE_CSR(mtvec, CSR_MTVEC) +DECLARE_CSR(mcounteren, CSR_MCOUNTEREN) +DECLARE_CSR(mscratch, CSR_MSCRATCH) +DECLARE_CSR(mepc, CSR_MEPC) +DECLARE_CSR(mcause, CSR_MCAUSE) +DECLARE_CSR(mtval, CSR_MTVAL) +DECLARE_CSR(mip, CSR_MIP) +DECLARE_CSR(pmpcfg0, CSR_PMPCFG0) +DECLARE_CSR(pmpcfg1, CSR_PMPCFG1) +DECLARE_CSR(pmpcfg2, CSR_PMPCFG2) +DECLARE_CSR(pmpcfg3, CSR_PMPCFG3) +DECLARE_CSR(pmpaddr0, CSR_PMPADDR0) +DECLARE_CSR(pmpaddr1, CSR_PMPADDR1) +DECLARE_CSR(pmpaddr2, CSR_PMPADDR2) +DECLARE_CSR(pmpaddr3, CSR_PMPADDR3) +DECLARE_CSR(pmpaddr4, CSR_PMPADDR4) +DECLARE_CSR(pmpaddr5, CSR_PMPADDR5) +DECLARE_CSR(pmpaddr6, CSR_PMPADDR6) +DECLARE_CSR(pmpaddr7, CSR_PMPADDR7) +DECLARE_CSR(pmpaddr8, CSR_PMPADDR8) +DECLARE_CSR(pmpaddr9, CSR_PMPADDR9) +DECLARE_CSR(pmpaddr10, CSR_PMPADDR10) +DECLARE_CSR(pmpaddr11, CSR_PMPADDR11) +DECLARE_CSR(pmpaddr12, CSR_PMPADDR12) +DECLARE_CSR(pmpaddr13, CSR_PMPADDR13) +DECLARE_CSR(pmpaddr14, CSR_PMPADDR14) +DECLARE_CSR(pmpaddr15, CSR_PMPADDR15) +DECLARE_CSR(tselect, CSR_TSELECT) +DECLARE_CSR(tdata1, CSR_TDATA1) +DECLARE_CSR(tdata2, CSR_TDATA2) +DECLARE_CSR(tdata3, CSR_TDATA3) +DECLARE_CSR(dcsr, CSR_DCSR) +DECLARE_CSR(dpc, CSR_DPC) +DECLARE_CSR(dscratch, CSR_DSCRATCH) +DECLARE_CSR(mcycle, CSR_MCYCLE) +DECLARE_CSR(minstret, CSR_MINSTRET) +DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) +DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) +DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) +DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) +DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) +DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) +DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) +DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) +DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) +DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) +DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) +DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) +DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) +DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) +DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) +DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) +DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) +DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) +DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) +DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) +DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) +DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) +DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) +DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) +DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) +DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) +DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) +DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) +DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) +DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) +DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) +DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) +DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) +DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) +DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) +DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) +DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) +DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) +DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) +DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) +DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) +DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) +DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) +DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) +DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) +DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) +DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) +DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) +DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) +DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) +DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) +DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) +DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) +DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) +DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) +DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) +DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) +DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) +DECLARE_CSR(mvendorid, CSR_MVENDORID) +DECLARE_CSR(marchid, CSR_MARCHID) +DECLARE_CSR(mimpid, CSR_MIMPID) +DECLARE_CSR(mhartid, CSR_MHARTID) +DECLARE_CSR(cycleh, CSR_CYCLEH) +DECLARE_CSR(timeh, CSR_TIMEH) +DECLARE_CSR(instreth, CSR_INSTRETH) +DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) +DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) +DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) +DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) +DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) +DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) +DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) +DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) +DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) +DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) +DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) +DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) +DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) +DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) +DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) +DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) +DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) +DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) +DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) +DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) +DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) +DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) +DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) +DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) +DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) +DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) +DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) +DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) +DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) +DECLARE_CSR(mcycleh, CSR_MCYCLEH) +DECLARE_CSR(minstreth, CSR_MINSTRETH) +DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) +DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) +DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) +DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) +DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) +DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) +DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) +DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) +DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) +DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) +DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) +DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) +DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) +DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) +DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) +DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) +DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) +DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) +DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) +DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) +DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) +DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) +DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) +DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) +DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) +DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) +DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) +DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) +DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) +#endif +#ifdef DECLARE_CAUSE +DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) +DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS) +DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) +DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) +DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) +DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS) +DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) +DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS) +DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) +DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) +DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) +DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) +DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT) +DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT) +DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT) +#endif diff --git a/VexRiscv/src/test/cpp/raw/deleg/src/ld b/VexRiscv/src/test/cpp/raw/deleg/src/ld new file mode 100644 index 0000000..93d8de8 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/deleg/src/ld @@ -0,0 +1,16 @@ +OUTPUT_ARCH( "riscv" ) + +MEMORY { + onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 128K +} + +SECTIONS +{ + + .crt_section : + { + . = ALIGN(4); + *crt.o(.text) + } > onChipRam + +} diff --git a/VexRiscv/src/test/cpp/raw/fpu/.gitignore b/VexRiscv/src/test/cpp/raw/fpu/.gitignore new file mode 100644 index 0000000..c12cb2c --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/fpu/.gitignore @@ -0,0 +1,4 @@ +*.map +*.v +*.elf +*.o
\ No newline at end of file diff --git a/VexRiscv/src/test/cpp/raw/fpu/build/amo.asm b/VexRiscv/src/test/cpp/raw/fpu/build/amo.asm new file mode 100644 index 0000000..d86b61c --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/fpu/build/amo.asm @@ -0,0 +1,247 @@ + +build/amo.elf: file format elf32-littleriscv + + +Disassembly of section .crt_section: + +80000000 <_start>: +80000000: 00100e13 li t3,1 +80000004: 00000097 auipc ra,0x0 +80000008: 27408093 addi ra,ra,628 # 80000278 <test1_data> +8000000c: 02d00113 li sp,45 +80000010: 0820a1af amoswap.w gp,sp,(ra) +80000014: 0000a203 lw tp,0(ra) +80000018: 02d00a13 li s4,45 +8000001c: 224a1663 bne s4,tp,80000248 <fail> +80000020: 00b00a13 li s4,11 +80000024: 223a1263 bne s4,gp,80000248 <fail> + +80000028 <test2>: +80000028: 00200e13 li t3,2 +8000002c: 00000097 auipc ra,0x0 +80000030: 25008093 addi ra,ra,592 # 8000027c <test2_data> +80000034: 03700113 li sp,55 +80000038: 0820a1af amoswap.w gp,sp,(ra) +8000003c: 0000a203 lw tp,0(ra) +80000040: 03700a13 li s4,55 +80000044: 204a1263 bne s4,tp,80000248 <fail> +80000048: 01600a13 li s4,22 +8000004c: 1e3a1e63 bne s4,gp,80000248 <fail> + +80000050 <test3>: +80000050: 00300e13 li t3,3 +80000054: 00000097 auipc ra,0x0 +80000058: 22c08093 addi ra,ra,556 # 80000280 <test3_data> +8000005c: 04200113 li sp,66 +80000060: 0020a1af amoadd.w gp,sp,(ra) +80000064: 0000a203 lw tp,0(ra) +80000068: 08b00a13 li s4,139 +8000006c: 1c4a1e63 bne s4,tp,80000248 <fail> +80000070: 04900a13 li s4,73 +80000074: 1c3a1a63 bne s4,gp,80000248 <fail> + +80000078 <test4>: +80000078: 00400e13 li t3,4 +8000007c: 00000097 auipc ra,0x0 +80000080: 20808093 addi ra,ra,520 # 80000284 <test4_data> +80000084: 05700113 li sp,87 +80000088: 2020a1af amoxor.w gp,sp,(ra) +8000008c: 0000a203 lw tp,0(ra) +80000090: 06d00a13 li s4,109 +80000094: 1a4a1a63 bne s4,tp,80000248 <fail> +80000098: 03a00a13 li s4,58 +8000009c: 1a3a1663 bne s4,gp,80000248 <fail> + +800000a0 <test5>: +800000a0: 00500e13 li t3,5 +800000a4: 00000097 auipc ra,0x0 +800000a8: 1e408093 addi ra,ra,484 # 80000288 <test5_data> +800000ac: 02c00113 li sp,44 +800000b0: 6020a1af amoand.w gp,sp,(ra) +800000b4: 0000a203 lw tp,0(ra) +800000b8: 02800a13 li s4,40 +800000bc: 184a1663 bne s4,tp,80000248 <fail> +800000c0: 03800a13 li s4,56 +800000c4: 183a1263 bne s4,gp,80000248 <fail> + +800000c8 <test6>: +800000c8: 00600e13 li t3,6 +800000cc: 00000097 auipc ra,0x0 +800000d0: 1c008093 addi ra,ra,448 # 8000028c <test6_data> +800000d4: 01800113 li sp,24 +800000d8: 4020a1af amoor.w gp,sp,(ra) +800000dc: 0000a203 lw tp,0(ra) +800000e0: 05b00a13 li s4,91 +800000e4: 164a1263 bne s4,tp,80000248 <fail> +800000e8: 04b00a13 li s4,75 +800000ec: 143a1e63 bne s4,gp,80000248 <fail> + +800000f0 <test7>: +800000f0: 00700e13 li t3,7 +800000f4: 00000097 auipc ra,0x0 +800000f8: 19c08093 addi ra,ra,412 # 80000290 <test7_data> +800000fc: 01800113 li sp,24 +80000100: 8020a1af amomin.w gp,sp,(ra) +80000104: 0000a203 lw tp,0(ra) +80000108: 01800a13 li s4,24 +8000010c: 124a1e63 bne s4,tp,80000248 <fail> +80000110: 03800a13 li s4,56 +80000114: 123a1a63 bne s4,gp,80000248 <fail> + +80000118 <test8>: +80000118: 00800e13 li t3,8 +8000011c: 00000097 auipc ra,0x0 +80000120: 17808093 addi ra,ra,376 # 80000294 <test8_data> +80000124: 05800113 li sp,88 +80000128: 8020a1af amomin.w gp,sp,(ra) +8000012c: 0000a203 lw tp,0(ra) +80000130: 05300a13 li s4,83 +80000134: 104a1a63 bne s4,tp,80000248 <fail> +80000138: 05300a13 li s4,83 +8000013c: 103a1663 bne s4,gp,80000248 <fail> + +80000140 <test9>: +80000140: 00900e13 li t3,9 +80000144: 00000097 auipc ra,0x0 +80000148: 15408093 addi ra,ra,340 # 80000298 <test9_data> +8000014c: fca00113 li sp,-54 +80000150: 8020a1af amomin.w gp,sp,(ra) +80000154: 0000a203 lw tp,0(ra) +80000158: fca00a13 li s4,-54 +8000015c: 0e4a1663 bne s4,tp,80000248 <fail> +80000160: 02100a13 li s4,33 +80000164: 0e3a1263 bne s4,gp,80000248 <fail> + +80000168 <test10>: +80000168: 00a00e13 li t3,10 +8000016c: 00000097 auipc ra,0x0 +80000170: 13008093 addi ra,ra,304 # 8000029c <test10_data> +80000174: 03400113 li sp,52 +80000178: 8020a1af amomin.w gp,sp,(ra) +8000017c: 0000a203 lw tp,0(ra) +80000180: fbf00a13 li s4,-65 +80000184: 0c4a1263 bne s4,tp,80000248 <fail> +80000188: fbf00a13 li s4,-65 +8000018c: 0a3a1e63 bne s4,gp,80000248 <fail> + +80000190 <test11>: +80000190: 00b00e13 li t3,11 +80000194: 00000097 auipc ra,0x0 +80000198: 10c08093 addi ra,ra,268 # 800002a0 <test11_data> +8000019c: fcc00113 li sp,-52 +800001a0: a020a1af amomax.w gp,sp,(ra) +800001a4: 0000a203 lw tp,0(ra) +800001a8: fcc00a13 li s4,-52 +800001ac: 084a1e63 bne s4,tp,80000248 <fail> +800001b0: fa900a13 li s4,-87 +800001b4: 083a1a63 bne s4,gp,80000248 <fail> + +800001b8 <test12>: +800001b8: 00c00e13 li t3,12 +800001bc: 00000097 auipc ra,0x0 +800001c0: 0e808093 addi ra,ra,232 # 800002a4 <test12_data> +800001c4: 03400113 li sp,52 +800001c8: a020a1af amomax.w gp,sp,(ra) +800001cc: 0000a203 lw tp,0(ra) +800001d0: 03400a13 li s4,52 +800001d4: 064a1a63 bne s4,tp,80000248 <fail> +800001d8: fc900a13 li s4,-55 +800001dc: 063a1663 bne s4,gp,80000248 <fail> + +800001e0 <test13>: +800001e0: 00d00e13 li t3,13 +800001e4: 00000097 auipc ra,0x0 +800001e8: 0c408093 addi ra,ra,196 # 800002a8 <test13_data> +800001ec: ffff0137 lui sp,0xffff0 +800001f0: c020a1af amominu.w gp,sp,(ra) +800001f4: 0000a203 lw tp,0(ra) +800001f8: ffff0a37 lui s4,0xffff0 +800001fc: 044a1663 bne s4,tp,80000248 <fail> +80000200: ffff0a37 lui s4,0xffff0 +80000204: 004a0a13 addi s4,s4,4 # ffff0004 <test14_data+0x7ffefd58> +80000208: 043a1063 bne s4,gp,80000248 <fail> +8000020c: 0480006f j 80000254 <pass> + +80000210 <test14>: +80000210: 00e00e13 li t3,14 +80000214: 00000097 auipc ra,0x0 +80000218: 09808093 addi ra,ra,152 # 800002ac <test14_data> +8000021c: ffff0137 lui sp,0xffff0 +80000220: 00c10113 addi sp,sp,12 # ffff000c <test14_data+0x7ffefd60> +80000224: e020a1af amomaxu.w gp,sp,(ra) +80000228: 0000a203 lw tp,0(ra) +8000022c: ffff0a37 lui s4,0xffff0 +80000230: 00ca0a13 addi s4,s4,12 # ffff000c <test14_data+0x7ffefd60> +80000234: 004a1a63 bne s4,tp,80000248 <fail> +80000238: ffff0a37 lui s4,0xffff0 +8000023c: 005a0a13 addi s4,s4,5 # ffff0005 <test14_data+0x7ffefd59> +80000240: 003a1463 bne s4,gp,80000248 <fail> +80000244: 0100006f j 80000254 <pass> + +80000248 <fail>: +80000248: f0100137 lui sp,0xf0100 +8000024c: f2410113 addi sp,sp,-220 # f00fff24 <test14_data+0x700ffc78> +80000250: 01c12023 sw t3,0(sp) + +80000254 <pass>: +80000254: f0100137 lui sp,0xf0100 +80000258: f2010113 addi sp,sp,-224 # f00fff20 <test14_data+0x700ffc74> +8000025c: 00012023 sw zero,0(sp) +80000260: 00000013 nop +80000264: 00000013 nop +80000268: 00000013 nop +8000026c: 00000013 nop +80000270: 00000013 nop +80000274: 00000013 nop + +80000278 <test1_data>: +80000278: 0000000b 0xb + +8000027c <test2_data>: +8000027c: 0016 c.slli zero,0x5 + ... + +80000280 <test3_data>: +80000280: 0049 c.nop 18 + ... + +80000284 <test4_data>: +80000284: 003a c.slli zero,0xe + ... + +80000288 <test5_data>: +80000288: 0038 addi a4,sp,8 + ... + +8000028c <test6_data>: +8000028c: 0000004b fnmsub.s ft0,ft0,ft0,ft0,rne + +80000290 <test7_data>: +80000290: 0038 addi a4,sp,8 + ... + +80000294 <test8_data>: +80000294: 00000053 fadd.s ft0,ft0,ft0,rne + +80000298 <test9_data>: +80000298: 0021 c.nop 8 + ... + +8000029c <test10_data>: +8000029c: ffffffbf 0xffffffbf + +800002a0 <test11_data>: +800002a0: ffa9 bnez a5,800001fa <test13+0x1a> +800002a2: ffff 0xffff + +800002a4 <test12_data>: +800002a4: ffc9 bnez a5,8000023e <test14+0x2e> +800002a6: ffff 0xffff + +800002a8 <test13_data>: +800002a8: 0004 0x4 +800002aa: ffff 0xffff + +800002ac <test14_data>: +800002ac: 0005 c.nop 1 +800002ae: ffff 0xffff diff --git a/VexRiscv/src/test/cpp/raw/fpu/build/amo.hex b/VexRiscv/src/test/cpp/raw/fpu/build/amo.hex new file mode 100644 index 0000000..74d3567 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/fpu/build/amo.hex @@ -0,0 +1,45 @@ +:0200000480007A
+:10000000130E100097000000938040271301D002C8
+:10001000AFA1200803A20000130AD00263164A22EF
+:10002000130AB00063123A22130E2000970000005A
+:100030009380002513017003AFA1200803A20000E4
+:10004000130A700363124A20130A6001631E3A1EEA
+:10005000130E3000970000009380C022130120048B
+:10006000AFA1200003A20000130AB008631E4A1CBF
+:10007000130A9004631A3A1C130E40009700000004
+:100080009380802013017005AFA1202003A20000FF
+:10009000130AD006631A4A1A130AA00363163A1AFF
+:1000A000130E5000970000009380401E1301C00201
+:1000B000AFA1206003A20000130A800263164A1851
+:1000C000130A800363123A18130E600097000000B1
+:1000D0009380001C13018001AFA1204003A2000007
+:1000E000130AB00563124A16130AB004631E3A14C9
+:1000F000130E7000970000009380C0191301800157
+:10010000AFA1208003A20000130A8001631E4A12DF
+:10011000130A8003631A3A12130E8000970000003E
+:100120009380801713018005AFA1208003A20000F7
+:10013000130A3005631A4A10130A300563163A1081
+:10014000130E900097000000938040151301A0FC4F
+:10015000AFA1208003A20000130AA0FC63164A0E80
+:10016000130A100263123A0E130EA000970000004B
+:100170009380001313014003AFA1208003A200006D
+:10018000130AF0FB63124A0C130AF0FB631E3A0ACF
+:10019000130EB000970000009380C0101301C0FC44
+:1001A000AFA120A003A20000130AC0FC631E4A08EE
+:1001B000130A90FA631A3A08130EC0009700000061
+:1001C0009380800E13014003AFA120A003A2000082
+:1001D000130A4003631A4A06130A90FC63163A0690
+:1001E000130ED000970000009380400C3701FFFFF2
+:1001F000AFA120C003A20000370AFFFF63164A0424
+:10020000370AFFFF130A4A0063103A046F008004A4
+:10021000130EE00097000000938080093701FFFF74
+:100220001301C100AFA120E003A20000370AFFFFC5
+:10023000130ACA00631A4A00370AFFFF130A5A005A
+:1002400063143A006F000001370110F0130141F20E
+:100250002320C101370110F0130101F22320010016
+:100260001300000013000000130000001300000042
+:1002700013000000130000000B0000001600000037
+:10028000490000003A000000380000004B00000068
+:10029000380000005300000021000000BFFFFFFFF6
+:1002A000A9FFFFFFC9FFFFFF0400FFFF0500FFFFDD
+:00000001FF
diff --git a/VexRiscv/src/test/cpp/raw/fpu/build/fpu.asm b/VexRiscv/src/test/cpp/raw/fpu/build/fpu.asm new file mode 100644 index 0000000..b769972 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/fpu/build/fpu.asm @@ -0,0 +1,276 @@ + +build/fpu.elf: file format elf32-littleriscv + + +Disassembly of section .crt_section: + +80000000 <_start>: +80000000: 00100e13 li t3,1 +80000004: 00000013 nop +80000008: 00000013 nop +8000000c: 00000013 nop +80000010: 00000013 nop +80000014: 00107153 fadd.s ft2,ft0,ft1 +80000018: 00000013 nop +8000001c: 00000013 nop +80000020: 00000013 nop +80000024: 00000013 nop +80000028: 0180006f j 80000040 <test2> +8000002c: 00000013 nop +80000030: 00000013 nop +80000034: 00000013 nop +80000038: 00000013 nop +8000003c: 00000013 nop + +80000040 <test2>: +80000040: 00200e13 li t3,2 +80000044: 00000097 auipc ra,0x0 +80000048: 2e80a083 lw ra,744(ra) # 8000032c <test1_data> +8000004c: 00107153 fadd.s ft2,ft0,ft1 +80000050: 00000013 nop +80000054: 00000013 nop +80000058: 00000013 nop +8000005c: 00000013 nop +80000060: 0200006f j 80000080 <test3> +80000064: 00000013 nop +80000068: 00000013 nop +8000006c: 00000013 nop +80000070: 00000013 nop +80000074: 00000013 nop +80000078: 00000013 nop +8000007c: 00000013 nop + +80000080 <test3>: +80000080: 00300e13 li t3,3 +80000084: 00000013 nop +80000088: 00000013 nop +8000008c: 00000013 nop +80000090: 00000013 nop +80000094: 0080006f j 8000009c <skip> +80000098: 00107153 fadd.s ft2,ft0,ft1 + +8000009c <skip>: +8000009c: 0240006f j 800000c0 <test4> +800000a0: 00000013 nop +800000a4: 00000013 nop +800000a8: 00000013 nop +800000ac: 00000013 nop +800000b0: 00000013 nop +800000b4: 00000013 nop +800000b8: 00000013 nop +800000bc: 00000013 nop + +800000c0 <test4>: +800000c0: 00400e13 li t3,4 +800000c4: 00000013 nop +800000c8: 00000013 nop +800000cc: 00000013 nop +800000d0: 00000013 nop +800000d4: 00000097 auipc ra,0x0 +800000d8: 25808093 addi ra,ra,600 # 8000032c <test1_data> +800000dc: 0000a107 flw ft2,0(ra) +800000e0: 00000013 nop +800000e4: 00000013 nop +800000e8: 00000013 nop +800000ec: 00000013 nop +800000f0: 0100006f j 80000100 <test5> +800000f4: 00000013 nop +800000f8: 00000013 nop +800000fc: 00000013 nop + +80000100 <test5>: +80000100: 00500e13 li t3,5 +80000104: 00000013 nop +80000108: 00000013 nop +8000010c: 00000013 nop +80000110: 00000013 nop +80000114: 00000097 auipc ra,0x0 +80000118: 21808093 addi ra,ra,536 # 8000032c <test1_data> +8000011c: 00000117 auipc sp,0x0 +80000120: 21410113 addi sp,sp,532 # 80000330 <test2_data> +80000124: 0000a087 flw ft1,0(ra) +80000128: 00012107 flw ft2,0(sp) +8000012c: 0020f1d3 fadd.s ft3,ft1,ft2 +80000130: 00000013 nop +80000134: 00000013 nop +80000138: 00000013 nop +8000013c: 00000013 nop +80000140: 0400006f j 80000180 <test6> +80000144: 00000013 nop +80000148: 00000013 nop +8000014c: 00000013 nop +80000150: 00000013 nop +80000154: 00000013 nop +80000158: 00000013 nop +8000015c: 00000013 nop +80000160: 00000013 nop +80000164: 00000013 nop +80000168: 00000013 nop +8000016c: 00000013 nop +80000170: 00000013 nop +80000174: 00000013 nop +80000178: 00000013 nop +8000017c: 00000013 nop + +80000180 <test6>: +80000180: 00600e13 li t3,6 +80000184: 00000013 nop +80000188: 00000013 nop +8000018c: 00000013 nop +80000190: 00000013 nop +80000194: 00000097 auipc ra,0x0 +80000198: 1a008093 addi ra,ra,416 # 80000334 <test3_data> +8000019c: 0030a027 fsw ft3,0(ra) +800001a0: 00000013 nop +800001a4: 00000013 nop +800001a8: 00000013 nop +800001ac: 00000013 nop +800001b0: 0100006f j 800001c0 <test7> +800001b4: 00000013 nop +800001b8: 00000013 nop +800001bc: 00000013 nop + +800001c0 <test7>: +800001c0: 00700e13 li t3,7 +800001c4: 00000097 auipc ra,0x0 +800001c8: 17008093 addi ra,ra,368 # 80000334 <test3_data> +800001cc: 00000117 auipc sp,0x0 +800001d0: 16c10113 addi sp,sp,364 # 80000338 <test4_data> +800001d4: 00000197 auipc gp,0x0 +800001d8: 16818193 addi gp,gp,360 # 8000033c <test5_data> +800001dc: 00000217 auipc tp,0x0 +800001e0: 16420213 addi tp,tp,356 # 80000340 <test6_data> +800001e4: 0000a207 flw ft4,0(ra) +800001e8: 00427253 fadd.s ft4,ft4,ft4 +800001ec: 0040f2d3 fadd.s ft5,ft1,ft4 +800001f0: 00412027 fsw ft4,0(sp) +800001f4: 0051a027 fsw ft5,0(gp) +800001f8: 00122027 fsw ft1,0(tp) # 0 <_start-0x80000000> +800001fc: 00000013 nop +80000200: 00000013 nop +80000204: 00000013 nop +80000208: 00000013 nop +8000020c: 0340006f j 80000240 <test8> +80000210: 00000013 nop +80000214: 00000013 nop +80000218: 00000013 nop +8000021c: 00000013 nop +80000220: 00000013 nop +80000224: 00000013 nop +80000228: 00000013 nop +8000022c: 00000013 nop +80000230: 00000013 nop +80000234: 00000013 nop +80000238: 00000013 nop +8000023c: 00000013 nop + +80000240 <test8>: +80000240: 00800e13 li t3,8 +80000244: c011f0d3 fcvt.wu.s ra,ft3 +80000248: 00000013 nop +8000024c: 00000013 nop +80000250: 00000013 nop +80000254: 00000013 nop +80000258: 0280006f j 80000280 <test9> +8000025c: 00000013 nop +80000260: 00000013 nop +80000264: 00000013 nop +80000268: 00000013 nop +8000026c: 00000013 nop +80000270: 00000013 nop +80000274: 00000013 nop +80000278: 00000013 nop +8000027c: 00000013 nop + +80000280 <test9>: +80000280: 00900e13 li t3,9 +80000284: a03100d3 fle.s ra,ft2,ft3 +80000288: a0218153 fle.s sp,ft3,ft2 +8000028c: a03181d3 fle.s gp,ft3,ft3 +80000290: 00000013 nop +80000294: 00000013 nop +80000298: 00000013 nop +8000029c: 00000013 nop +800002a0: 0200006f j 800002c0 <test10> +800002a4: 00000013 nop +800002a8: 00000013 nop +800002ac: 00000013 nop +800002b0: 00000013 nop +800002b4: 00000013 nop +800002b8: 00000013 nop +800002bc: 00000013 nop + +800002c0 <test10>: +800002c0: 00a00e13 li t3,10 +800002c4: 01000093 li ra,16 +800002c8: d010f0d3 fcvt.s.wu ft1,ra +800002cc: 01200113 li sp,18 +800002d0: 20000193 li gp,512 +800002d4: d0117153 fcvt.s.wu ft2,sp +800002d8: d011f1d3 fcvt.s.wu ft3,gp +800002dc: 00000217 auipc tp,0x0 +800002e0: 0a422203 lw tp,164(tp) # 80000380 <test10_data> +800002e4: d01272d3 fcvt.s.wu ft5,tp +800002e8: 00000013 nop +800002ec: 00000013 nop +800002f0: 00000013 nop +800002f4: 00000013 nop +800002f8: 0100006f j 80000308 <pass> + +800002fc <fail>: +800002fc: f0100137 lui sp,0xf0100 +80000300: f2410113 addi sp,sp,-220 # f00fff24 <test10_data+0x700ffba4> +80000304: 01c12023 sw t3,0(sp) + +80000308 <pass>: +80000308: f0100137 lui sp,0xf0100 +8000030c: f2010113 addi sp,sp,-224 # f00fff20 <test10_data+0x700ffba0> +80000310: 00012023 sw zero,0(sp) +80000314: 00000013 nop +80000318: 00000013 nop +8000031c: 00000013 nop +80000320: 00000013 nop +80000324: 00000013 nop +80000328: 00000013 nop + +8000032c <test1_data>: +8000032c: 0000 unimp +8000032e: 3fc0 fld fs0,184(a5) + +80000330 <test2_data>: +80000330: 0000 unimp +80000332: 40a0 lw s0,64(s1) + +80000334 <test3_data>: +80000334: 0049 c.nop 18 + ... + +80000338 <test4_data>: +80000338: 003a c.slli zero,0xe + ... + +8000033c <test5_data>: +8000033c: 0038 addi a4,sp,8 + ... + +80000340 <test6_data>: +80000340: 0000004b fnmsub.s ft0,ft0,ft0,ft0,rne +80000344: 00000013 nop +80000348: 00000013 nop +8000034c: 00000013 nop +80000350: 00000013 nop +80000354: 00000013 nop +80000358: 00000013 nop +8000035c: 00000013 nop +80000360: 00000013 nop +80000364: 00000013 nop +80000368: 00000013 nop +8000036c: 00000013 nop +80000370: 00000013 nop +80000374: 00000013 nop +80000378: 00000013 nop +8000037c: 00000013 nop + +80000380 <test10_data>: +80000380: 01d4 addi a3,sp,196 + ... diff --git a/VexRiscv/src/test/cpp/raw/fpu/build/fpu.hex b/VexRiscv/src/test/cpp/raw/fpu/build/fpu.hex new file mode 100644 index 0000000..4b83443 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/fpu/build/fpu.hex @@ -0,0 +1,62 @@ +:0200000480007A
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diff --git a/VexRiscv/src/test/cpp/raw/fpu/makefile b/VexRiscv/src/test/cpp/raw/fpu/makefile new file mode 100644 index 0000000..4892095 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/fpu/makefile @@ -0,0 +1,5 @@ +PROJ_NAME=fpu + +FLOATING=yes + +include ../common/asm.mk
\ No newline at end of file diff --git a/VexRiscv/src/test/cpp/raw/fpu/src/crt.S b/VexRiscv/src/test/cpp/raw/fpu/src/crt.S new file mode 100644 index 0000000..302b98c --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/fpu/src/crt.S @@ -0,0 +1,193 @@ +.globl _star +#define TEST_ID x28 + +_start: + +#define assert(reg, value) \ + li x20, value; \ + bne x20, reg, fail; + + +test1: + li TEST_ID, 1 + nop + nop + nop + nop + fadd.s f2, f0, f1 + nop + nop + nop + nop + j test2 + +.align 6 +test2: + li TEST_ID, 2 + lw x1, test1_data + fadd.s f2, f0, f1 + nop + nop + nop + nop + + j test3 + + +.align 6 +test3: + li TEST_ID, 3 + nop + nop + nop + nop + j skip + fadd.s f2, f0, f1 +skip: + j test4 + + + +.align 6 +test4: + li TEST_ID, 4 + nop + nop + nop + nop + la x1, test1_data + flw f2, 0(x1) + nop + nop + nop + nop + + j test5 + +.align 6 +test5: + li TEST_ID, 5 + nop + nop + nop + nop + la x1, test1_data + la x2, test2_data + flw f1, 0(x1) + flw f2, 0(x2) + fadd.s f3, f1, f2 + nop + nop + nop + nop + j test6 + +.align 6 +test6: + li TEST_ID, 6 + nop + nop + nop + nop + la x1, test3_data + fsw f3, 0(x1) + nop + nop + nop + nop + j test7 + +.align 6 +test7: + li TEST_ID, 7 + la x1, test3_data + la x2, test4_data + la x3, test5_data + la x4, test6_data + flw f4, 0(x1) + fadd.s f4, f4, f4 + fadd.s f5, f1, f4 + fsw f4, 0(x2) + fsw f5, 0(x3) + fsw f1, 0(x4) + nop + nop + nop + nop + j test8 + +.align 6 +test8: + li TEST_ID, 8 + fcvt.wu.s x1, f3 + nop + nop + nop + nop + j test9 + +.align 6 +test9: + li TEST_ID, 9 + fle.s x1, f2, f3 + fle.s x2, f3, f2 + fle.s x3, f3, f3 + nop + nop + nop + nop + j test10 + +.align 6 +test10: + li TEST_ID, 10 + li x1, 16 + fcvt.s.wu f1, x1 + li x2, 18 + li x3, 512 + fcvt.s.wu f2, x2 + fcvt.s.wu f3, x3 + lw x4, test10_data + fcvt.s.wu f5, x4 + nop + nop + nop + nop + + /* la x1, test1_data + li x2, 45 + amoswap.w x3,x2,(x1) + lw x4, 0(x1) + assert(x4, 45) + assert(x3, 11)*/ + + + + + j pass + + +fail: + li x2, 0xF00FFF24 + sw TEST_ID, 0(x2) + +pass: + li x2, 0xF00FFF20 + sw x0, 0(x2) + + nop + nop + nop + nop + nop + nop + + +test1_data: .word 0x3fc00000 //1.5f +test2_data: .word 0x40a00000 //5.0f +test3_data: .word 73 +test4_data: .word 58 +test5_data: .word 56 +test6_data: .word 75 +.align 6 +test10_data: .word 468 diff --git a/VexRiscv/src/test/cpp/raw/fpu/src/ld b/VexRiscv/src/test/cpp/raw/fpu/src/ld new file mode 100644 index 0000000..93d8de8 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/fpu/src/ld @@ -0,0 +1,16 @@ +OUTPUT_ARCH( "riscv" ) + +MEMORY { + onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 128K +} + +SECTIONS +{ + + .crt_section : + { + . = ALIGN(4); + *crt.o(.text) + } > onChipRam + +} diff --git a/VexRiscv/src/test/cpp/raw/icache/.gitignore b/VexRiscv/src/test/cpp/raw/icache/.gitignore new file mode 100644 index 0000000..c12cb2c --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/icache/.gitignore @@ -0,0 +1,4 @@ +*.map +*.v +*.elf +*.o
\ No newline at end of file diff --git a/VexRiscv/src/test/cpp/raw/icache/build/icache.asm b/VexRiscv/src/test/cpp/raw/icache/build/icache.asm new file mode 100644 index 0000000..993f21b --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/icache/build/icache.asm @@ -0,0 +1,51 @@ + +build/icache.elf: file format elf32-littleriscv + + +Disassembly of section .crt_section: + +80000000 <_start>: +80000000: 00000097 auipc ra,0x0 +80000004: 04c08093 addi ra,ra,76 # 8000004c <fail> + +80000008 <test1>: +80000008: 00100e13 li t3,1 +8000000c: 00100093 li ra,1 +80000010: 00300113 li sp,3 +80000014: 00208093 addi ra,ra,2 +80000018: 02209a63 bne ra,sp,8000004c <fail> + +8000001c <test2>: +8000001c: 00200e13 li t3,2 +80000020: 01300093 li ra,19 +80000024: 00000117 auipc sp,0x0 +80000028: 02010113 addi sp,sp,32 # 80000044 <test2_trigger> +8000002c: 0040006f j 80000030 <test2_aligned> + +80000030 <test2_aligned>: +80000030: 00112023 sw ra,0(sp) +80000034: 0000100f fence.i +80000038: 00800a13 li s4,8 +8000003c: fffa0a13 addi s4,s4,-1 +80000040: fe0a1ee3 bnez s4,8000003c <test2_aligned+0xc> + +80000044 <test2_trigger>: +80000044: 0080006f j 8000004c <fail> +80000048: 0100006f j 80000058 <pass> + +8000004c <fail>: +8000004c: f0100137 lui sp,0xf0100 +80000050: f2410113 addi sp,sp,-220 # f00fff24 <pass+0x700ffecc> +80000054: 01c12023 sw t3,0(sp) + +80000058 <pass>: +80000058: f0100137 lui sp,0xf0100 +8000005c: f2010113 addi sp,sp,-224 # f00fff20 <pass+0x700ffec8> +80000060: 00012023 sw zero,0(sp) +80000064: 00000013 nop +80000068: 00000013 nop +8000006c: 00000013 nop +80000070: 00000013 nop +80000074: 00000013 nop +80000078: 00000013 nop + ... diff --git a/VexRiscv/src/test/cpp/raw/icache/build/icache.hex b/VexRiscv/src/test/cpp/raw/icache/build/icache.hex new file mode 100644 index 0000000..2588f0e --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/icache/build/icache.hex @@ -0,0 +1,11 @@ +:0200000480007A
+:10000000970000009380C004130E100093001000AE
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diff --git a/VexRiscv/src/test/cpp/raw/icache/makefile b/VexRiscv/src/test/cpp/raw/icache/makefile new file mode 100644 index 0000000..08779a2 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/icache/makefile @@ -0,0 +1,3 @@ +PROJ_NAME=icache + +include ../common/asm.mk
\ No newline at end of file diff --git a/VexRiscv/src/test/cpp/raw/icache/src/crt.S b/VexRiscv/src/test/cpp/raw/icache/src/crt.S new file mode 100644 index 0000000..b0b2425 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/icache/src/crt.S @@ -0,0 +1,49 @@ +.globl _star +#define TEST_ID x28 + +#define delay \ + li x20, 8; \ +1: addi x20, x20, -1; \ + bne x20, x0, 1b; + +_start: + la x1, fail + // csrw mtvec, x1 + +test1: //Dummy test + li TEST_ID, 1 + li x1, 1 + li x2, 3 + addi x1, x1, 2 + bne x1, x2, fail + +test2: + li TEST_ID, 2 + li x1, 0x13 //nop + la x2, test2_trigger + j test2_aligned +.align(4) +test2_aligned: + sw x1, 0(x2) + fence.i + delay +test2_trigger: + j fail + + + j pass + +fail: + li x2, 0xF00FFF24 + sw TEST_ID, 0(x2) + +pass: + li x2, 0xF00FFF20 + sw x0, 0(x2) + + nop + nop + nop + nop + nop + nop diff --git a/VexRiscv/src/test/cpp/raw/icache/src/ld b/VexRiscv/src/test/cpp/raw/icache/src/ld new file mode 100644 index 0000000..93d8de8 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/icache/src/ld @@ -0,0 +1,16 @@ +OUTPUT_ARCH( "riscv" ) + +MEMORY { + onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 128K +} + +SECTIONS +{ + + .crt_section : + { + . = ALIGN(4); + *crt.o(.text) + } > onChipRam + +} diff --git a/VexRiscv/src/test/cpp/raw/lrsc/.gitignore b/VexRiscv/src/test/cpp/raw/lrsc/.gitignore new file mode 100644 index 0000000..c12cb2c --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/lrsc/.gitignore @@ -0,0 +1,4 @@ +*.map +*.v +*.elf +*.o
\ No newline at end of file diff --git a/VexRiscv/src/test/cpp/raw/lrsc/build/lrsc.asm b/VexRiscv/src/test/cpp/raw/lrsc/build/lrsc.asm new file mode 100644 index 0000000..a2ba4c7 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/lrsc/build/lrsc.asm @@ -0,0 +1,180 @@ + +build/lrsc.elf: file format elf32-littleriscv + + +Disassembly of section .crt_section: + +80000000 <trap_entry-0x20>: +80000000: 06c0006f j 8000006c <_start> +80000004: 00000013 nop +80000008: 00000013 nop +8000000c: 00000013 nop +80000010: 00000013 nop +80000014: 00000013 nop +80000018: 00000013 nop +8000001c: 00000013 nop + +80000020 <trap_entry>: +80000020: 30002ef3 csrr t4,mstatus +80000024: 080efe93 andi t4,t4,128 +80000028: 000e8a63 beqz t4,8000003c <notExternalInterrupt> +8000002c: 00002eb7 lui t4,0x2 +80000030: 800e8e93 addi t4,t4,-2048 # 1800 <trap_entry-0x7fffe820> +80000034: 300e9073 csrw mstatus,t4 +80000038: 30200073 mret + +8000003c <notExternalInterrupt>: +8000003c: 34102ef3 csrr t4,mepc +80000040: 004e8e93 addi t4,t4,4 +80000044: 341e9073 csrw mepc,t4 +80000048: 30200073 mret + +8000004c <flush>: +8000004c: 200002b7 lui t0,0x20000 +80000050: 00001337 lui t1,0x1 +80000054: 02000393 li t2,32 + +80000058 <flushLoop>: +80000058: 0002ae03 lw t3,0(t0) # 20000000 <trap_entry-0x60000020> +8000005c: 006282b3 add t0,t0,t1 +80000060: fff38393 addi t2,t2,-1 +80000064: fe039ae3 bnez t2,80000058 <flushLoop> +80000068: 00008067 ret + +8000006c <_start>: +8000006c: 00100e13 li t3,1 +80000070: 10000537 lui a0,0x10000 +80000074: 06400593 li a1,100 +80000078: 06500613 li a2,101 +8000007c: 06600693 li a3,102 +80000080: 00d52023 sw a3,0(a0) # 10000000 <trap_entry-0x70000020> +80000084: 18b5262f sc.w a2,a1,(a0) +80000088: 00100713 li a4,1 +8000008c: 18e61863 bne a2,a4,8000021c <fail> +80000090: 00052703 lw a4,0(a0) +80000094: 18e69463 bne a3,a4,8000021c <fail> + +80000098 <test2>: +80000098: 00200e13 li t3,2 +8000009c: 10000537 lui a0,0x10000 +800000a0: 00450513 addi a0,a0,4 # 10000004 <trap_entry-0x7000001c> +800000a4: 06700593 li a1,103 +800000a8: 06800613 li a2,104 +800000ac: 06900693 li a3,105 +800000b0: 00d52023 sw a3,0(a0) +800000b4: 18b5262f sc.w a2,a1,(a0) +800000b8: 00100713 li a4,1 +800000bc: 16e61063 bne a2,a4,8000021c <fail> +800000c0: 00052703 lw a4,0(a0) +800000c4: 14e69c63 bne a3,a4,8000021c <fail> +800000c8: f85ff0ef jal ra,8000004c <flush> +800000cc: 00052703 lw a4,0(a0) +800000d0: 14e69663 bne a3,a4,8000021c <fail> + +800000d4 <test3>: +800000d4: 00300e13 li t3,3 +800000d8: 10000537 lui a0,0x10000 +800000dc: 00450513 addi a0,a0,4 # 10000004 <trap_entry-0x7000001c> +800000e0: 06700593 li a1,103 +800000e4: 06800613 li a2,104 +800000e8: 06900693 li a3,105 +800000ec: 18b5262f sc.w a2,a1,(a0) +800000f0: 00100713 li a4,1 +800000f4: 12e61463 bne a2,a4,8000021c <fail> +800000f8: 00052703 lw a4,0(a0) +800000fc: 12e69063 bne a3,a4,8000021c <fail> +80000100: f4dff0ef jal ra,8000004c <flush> +80000104: 00052703 lw a4,0(a0) +80000108: 10e69a63 bne a3,a4,8000021c <fail> + +8000010c <test4>: +8000010c: 00400e13 li t3,4 +80000110: 10000537 lui a0,0x10000 +80000114: 00850513 addi a0,a0,8 # 10000008 <trap_entry-0x70000018> +80000118: 06a00593 li a1,106 +8000011c: 06b00613 li a2,107 +80000120: 06c00693 li a3,108 +80000124: 00d52023 sw a3,0(a0) +80000128: 100527af lr.w a5,(a0) +8000012c: 18b5262f sc.w a2,a1,(a0) +80000130: 0ed79663 bne a5,a3,8000021c <fail> +80000134: 0e061463 bnez a2,8000021c <fail> +80000138: 00052703 lw a4,0(a0) +8000013c: 0ee59063 bne a1,a4,8000021c <fail> +80000140: f0dff0ef jal ra,8000004c <flush> +80000144: 00052703 lw a4,0(a0) +80000148: 0ce59a63 bne a1,a4,8000021c <fail> + +8000014c <test5>: +8000014c: 00500e13 li t3,5 +80000150: 10000537 lui a0,0x10000 +80000154: 00850513 addi a0,a0,8 # 10000008 <trap_entry-0x70000018> +80000158: 06d00593 li a1,109 +8000015c: 06e00613 li a2,110 +80000160: 06f00693 li a3,111 +80000164: 00d52023 sw a3,0(a0) +80000168: 18b5262f sc.w a2,a1,(a0) +8000016c: 0a060863 beqz a2,8000021c <fail> +80000170: 00052703 lw a4,0(a0) +80000174: 0ae69463 bne a3,a4,8000021c <fail> +80000178: ed5ff0ef jal ra,8000004c <flush> +8000017c: 00052703 lw a4,0(a0) +80000180: 08e69e63 bne a3,a4,8000021c <fail> +80000184: 00700e13 li t3,7 +80000188: 10000537 lui a0,0x10000 +8000018c: 01450513 addi a0,a0,20 # 10000014 <trap_entry-0x7000000c> +80000190: 07800593 li a1,120 +80000194: 07900613 li a2,121 +80000198: 07a00693 li a3,122 +8000019c: 01000e93 li t4,16 + +800001a0 <test7>: +800001a0: 00d52023 sw a3,0(a0) +800001a4: 100527af lr.w a5,(a0) +800001a8: 18b5262f sc.w a2,a1,(a0) +800001ac: 06d79863 bne a5,a3,8000021c <fail> +800001b0: 06061663 bnez a2,8000021c <fail> +800001b4: 00052703 lw a4,0(a0) +800001b8: 06e59263 bne a1,a4,8000021c <fail> +800001bc: fffe8e93 addi t4,t4,-1 +800001c0: 00450513 addi a0,a0,4 +800001c4: 00358593 addi a1,a1,3 +800001c8: 00360613 addi a2,a2,3 +800001cc: 00368693 addi a3,a3,3 +800001d0: fc0e98e3 bnez t4,800001a0 <test7> + +800001d4 <test9>: +800001d4: 00900e13 li t3,9 +800001d8: 10000537 lui a0,0x10000 +800001dc: 10050513 addi a0,a0,256 # 10000100 <trap_entry-0x6fffff20> +800001e0: 07b00593 li a1,123 +800001e4: 07c00613 li a2,124 +800001e8: 07d00693 li a3,125 +800001ec: 00d52023 sw a3,0(a0) +800001f0: 100527af lr.w a5,(a0) +800001f4: 00000073 ecall +800001f8: 18b527af sc.w a5,a1,(a0) +800001fc: 00000713 li a4,0 +80000200: 00e79e63 bne a5,a4,8000021c <fail> +80000204: 00052703 lw a4,0(a0) +80000208: 00e59a63 bne a1,a4,8000021c <fail> +8000020c: e41ff0ef jal ra,8000004c <flush> +80000210: 00052703 lw a4,0(a0) +80000214: 00e59463 bne a1,a4,8000021c <fail> +80000218: 0100006f j 80000228 <pass> + +8000021c <fail>: +8000021c: f0100137 lui sp,0xf0100 +80000220: f2410113 addi sp,sp,-220 # f00fff24 <pass+0x700ffcfc> +80000224: 01c12023 sw t3,0(sp) + +80000228 <pass>: +80000228: f0100137 lui sp,0xf0100 +8000022c: f2010113 addi sp,sp,-224 # f00fff20 <pass+0x700ffcf8> +80000230: 00012023 sw zero,0(sp) +80000234: 00000013 nop +80000238: 00000013 nop +8000023c: 00000013 nop +80000240: 00000013 nop +80000244: 00000013 nop +80000248: 00000013 nop diff --git a/VexRiscv/src/test/cpp/raw/lrsc/build/lrsc.hex b/VexRiscv/src/test/cpp/raw/lrsc/build/lrsc.hex new file mode 100644 index 0000000..b0ee273 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/lrsc/build/lrsc.hex @@ -0,0 +1,40 @@ +:0200000480007A
+:100000006F00C00613000000130000001300000082
+:100010001300000013000000130000001300000094
+:10002000F32E003093FE0E08638A0E00B72E0000F8
+:10003000938E0E8073900E3073002030F32E1034A8
+:10004000938E4E0073901E3473002030B702002050
+:10005000371300009303000203AE0200B382620074
+:100060009383F3FFE39A03FE67800000130E1000F2
+:1000700037050010930540061306500693066006E8
+:100080002320D5002F26B518130710006318E61893
+:10009000032705006394E618130E200037050010AF
+:1000A0001305450093057006130680069306900617
+:1000B0002320D5002F26B518130710006310E6166D
+:1000C00003270500639CE614EFF05FF803270500A3
+:1000D0006396E614130E3000370500101305450033
+:1000E0009305700613068006930690062F26B51812
+:1000F000130710006314E612032705006390E6124D
+:10010000EFF0DFF403270500639AE610130E4000BA
+:1001100037050010130585009305A0061306B006E9
+:100120009306C0062320D500AF2705102F26B5184B
+:100130006396D70E6314060E032705006390E50E41
+:10014000EFF0DFF003270500639AE50C130E500073
+:1001500037050010130585009305D0061306E00649
+:100160009306F0062320D5002F26B5186308060A4B
+:10017000032705006394E60AEFF05FED032705000F
+:10018000639EE608130E7000370500101305450145
+:1001900093058007130690079306A007930E0001AE
+:1001A0002320D500AF2705102F26B5186398D70652
+:1001B00063160606032705006392E506938EFEFF8D
+:1001C00013054500938535001306360093863600E7
+:1001D000E3980EFC130E9000370500101305051070
+:1001E0009305B0071306C0079306D0072320D50058
+:1001F000AF27051073000000AF27B51813070000E4
+:10020000639EE70003270500639AE500EFF01FE413
+:10021000032705006394E5006F000001370110F02B
+:10022000130141F22320C101370110F0130101F243
+:100230002320010013000000130000001300000041
+:0C02400013000000130000001300000079
+:040000058000006C0B
+:00000001FF
diff --git a/VexRiscv/src/test/cpp/raw/lrsc/makefile b/VexRiscv/src/test/cpp/raw/lrsc/makefile new file mode 100644 index 0000000..eafdb26 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/lrsc/makefile @@ -0,0 +1,5 @@ +PROJ_NAME=lrsc + +ATOMIC=yes + +include ../common/asm.mk
\ No newline at end of file diff --git a/VexRiscv/src/test/cpp/raw/lrsc/src/crt.S b/VexRiscv/src/test/cpp/raw/lrsc/src/crt.S new file mode 100644 index 0000000..a19663f --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/lrsc/src/crt.S @@ -0,0 +1,213 @@ +.globl _start + + + j _start + nop + nop + nop + nop + nop + nop + nop + +.global trap_entry +trap_entry: + csrr x29, mstatus + and x29, x29, 0x080 + beqz x29, notExternalInterrupt + li x29, 0x1800 //000 disable interrupts + csrw mstatus,x29 + mret + +notExternalInterrupt: + csrr x29, mepc + addi x29, x29, 4 + csrw mepc, x29 + mret + +flush: + li t0, 0x20000000 + li t1, 0x1000 + li t2, 32 +flushLoop: + lw t3, 0(t0) + add t0, t0, t1 + addi t2,t2,-1 + bnez t2, flushLoop + ret + +_start: +test1: //Test 1 SC on unreserved area should fail and not write memory + li x28, 1 + li a0, 0x10000000 + li a1, 100 + li a2, 101 + li a3, 102 + sw a3, 0(a0) + sc.w a2, a1, (a0) + li a4, 1 + bne a2, a4, fail + lw a4, 0(a0) + bne a3, a4, fail + +test2: //Test 2 SC on another unreserved area should fail and not write memory + li x28, 2 + li a0, 0x10000004 + li a1, 103 + li a2, 104 + li a3, 105 + sw a3, 0(a0) + sc.w a2, a1, (a0) + li a4, 1 + bne a2, a4, fail + lw a4, 0(a0) + bne a3, a4, fail + call flush + lw a4, 0(a0) + bne a3, a4, fail + + +test3: //Test 3 retrying SC on unreserved area should fail and not write memory + li x28, 3 + li a0, 0x10000004 + li a1, 103 + li a2, 104 + li a3, 105 + sc.w a2, a1, (a0) + li a4, 1 + bne a2, a4, fail + lw a4, 0(a0) + bne a3, a4, fail + call flush + lw a4, 0(a0) + bne a3, a4, fail + + +test4: //Test 4 SC on reserved area should pass and should be written write memory + li x28, 4 + li a0, 0x10000008 + li a1, 106 + li a2, 107 + li a3, 108 + sw a3, 0(a0) + lr.w a5, (a0) + sc.w a2, a1, (a0) + bne a5, a3, fail + bne a2, x0, fail + lw a4, 0(a0) + bne a1, a4, fail + call flush + lw a4, 0(a0) + bne a1, a4, fail + + +test5: //Test 5 redo SC on reserved area should fail + li x28, 5 + li a0, 0x10000008 + li a1, 109 + li a2, 110 + li a3, 111 + sw a3, 0(a0) + sc.w a2, a1, (a0) + beq a2, x0, fail + lw a4, 0(a0) + bne a3, a4, fail + call flush + lw a4, 0(a0) + bne a3, a4, fail + + +//Test 7 do a lot of allocation to clear the entries + li x28, 7 + li a0, 0x10000014 + li a1, 120 + li a2, 121 + li a3, 122 + li x29, 16 +test7: + sw a3, 0(a0) + lr.w a5, (a0) + sc.w a2, a1, (a0) + bne a5, a3, fail + bne a2, x0, fail + lw a4, 0(a0) + bne a1, a4, fail + add x29, x29, -1 + add a0, a0, 4 + add a1, a1, 3 + add a2, a2, 3 + add a3, a3, 3 + bnez x29, test7 + + +//Test 8 SC on discarded entries should fail + /* li x28, 8 + li a0, 0x10000018 + li a1, 120 + li a2, 121 + li a3, 122 + lw a5, 0(a0) + sc.w a2, a1, (a0) + li a4, 1 + bne a2, a4, fail + lw a4, 0(a0) + bne a5, a4, fail*/ + + +test9: //Test 9 SC should pass after a context switching + li x28, 9 + li a0, 0x10000100 + li a1, 123 + li a2, 124 + li a3, 125 + sw a3, 0(a0) + lr.w a5, (a0) + scall + sc.w a5, a1, (a0) + li a4, 0 + bne a5, a4, fail + lw a4, 0(a0) + bne a1, a4, fail + call flush + lw a4, 0(a0) + bne a1, a4, fail + + + +//Test 10 SC should fail if the address doesn't match + /* li x28, 10 + li a0, 0x10000200 + li a6, 0x10000204 + li a1, 126 + li a2, 127 + li a3, 128 + li a7, 129 + sw a3, 0(a0) + sw a7, 0(a6) + lr.w a5, (a6) + sc.w a2, a1, (a0) + li a4, 1 + bne a2, a4, fail + lw a4, 0(a6) + bne a7, a4, fail*/ + + + j pass + + +fail: //x28 => error code + li x2, 0xF00FFF24 + sw x28, 0(x2) + +pass: + li x2, 0xF00FFF20 + sw x0, 0(x2) + + + + nop + nop + nop + nop + nop + nop diff --git a/VexRiscv/src/test/cpp/raw/lrsc/src/ld b/VexRiscv/src/test/cpp/raw/lrsc/src/ld new file mode 100644 index 0000000..93d8de8 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/lrsc/src/ld @@ -0,0 +1,16 @@ +OUTPUT_ARCH( "riscv" ) + +MEMORY { + onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 128K +} + +SECTIONS +{ + + .crt_section : + { + . = ALIGN(4); + *crt.o(.text) + } > onChipRam + +} diff --git a/VexRiscv/src/test/cpp/raw/machineCsr/.gitignore b/VexRiscv/src/test/cpp/raw/machineCsr/.gitignore new file mode 100644 index 0000000..c12cb2c --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/machineCsr/.gitignore @@ -0,0 +1,4 @@ +*.map +*.v +*.elf +*.o
\ No newline at end of file diff --git a/VexRiscv/src/test/cpp/raw/machineCsr/build/machineCsr.asm b/VexRiscv/src/test/cpp/raw/machineCsr/build/machineCsr.asm new file mode 100644 index 0000000..679be70 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/machineCsr/build/machineCsr.asm @@ -0,0 +1,155 @@ + +build/machineCsr.elf: file format elf32-littleriscv + + +Disassembly of section .crt_section: + +80000000 <trap_entry-0x20>: +80000000: 0940006f j 80000094 <_start> +80000004: 00000013 nop +80000008: 00000013 nop +8000000c: 00000013 nop +80000010: 00000013 nop +80000014: 00000013 nop +80000018: 00000013 nop +8000001c: 00000013 nop + +80000020 <trap_entry>: +80000020: 34202e73 csrr t3,mcause +80000024: 000e1e63 bnez t3,80000040 <notICmdAlignementException> +80000028: ffc00f13 li t5,-4 +8000002c: 34102ef3 csrr t4,mepc +80000030: 01eefeb3 and t4,t4,t5 +80000034: 004e8e93 addi t4,t4,4 +80000038: 341e9073 csrw mepc,t4 +8000003c: 01c0006f j 80000058 <mepcFixed> + +80000040 <notICmdAlignementException>: +80000040: 80000eb7 lui t4,0x80000 +80000044: 01de7f33 and t5,t3,t4 +80000048: 000f1863 bnez t5,80000058 <mepcFixed> +8000004c: 34102ef3 csrr t4,mepc +80000050: 004e8e93 addi t4,t4,4 # 80000004 <unalignedPcA+0xfffffe28> +80000054: 341e9073 csrw mepc,t4 + +80000058 <mepcFixed>: +80000058: 80000eb7 lui t4,0x80000 +8000005c: 003e8e93 addi t4,t4,3 # 80000003 <unalignedPcA+0xfffffe27> +80000060: 01ce9863 bne t4,t3,80000070 <noSoftwareInterrupt> +80000064: f0013c37 lui s8,0xf0013 +80000068: 00000c93 li s9,0 +8000006c: 019c2023 sw s9,0(s8) # f0013000 <unalignedPcA+0x70012e24> + +80000070 <noSoftwareInterrupt>: +80000070: 80000eb7 lui t4,0x80000 +80000074: 007e8e93 addi t4,t4,7 # 80000007 <unalignedPcA+0xfffffe2b> +80000078: 01ce9463 bne t4,t3,80000080 <noTimerInterrupt> +8000007c: 30405073 csrwi mie,0 + +80000080 <noTimerInterrupt>: +80000080: 80000eb7 lui t4,0x80000 +80000084: 00be8e93 addi t4,t4,11 # 8000000b <unalignedPcA+0xfffffe2f> +80000088: 01ce9463 bne t4,t3,80000090 <noExernalInterrupt> +8000008c: 30405073 csrwi mie,0 + +80000090 <noExernalInterrupt>: +80000090: 30200073 mret + +80000094 <_start>: +80000094: 00100e13 li t3,1 +80000098: 00000073 ecall +8000009c: 00200e13 li t3,2 +800000a0: 00800293 li t0,8 +800000a4: 3002a073 csrs mstatus,t0 +800000a8: 00800293 li t0,8 +800000ac: 30429073 csrw mie,t0 +800000b0: f0013c37 lui s8,0xf0013 +800000b4: 00100c93 li s9,1 +800000b8: 019c2023 sw s9,0(s8) # f0013000 <unalignedPcA+0x70012e24> +800000bc: 00000013 nop +800000c0: 00000013 nop +800000c4: 00000013 nop +800000c8: 00000013 nop +800000cc: 00000013 nop +800000d0: 00000013 nop +800000d4: 00000013 nop +800000d8: 00000013 nop +800000dc: 00000013 nop +800000e0: 00000013 nop +800000e4: 00000013 nop +800000e8: 00000013 nop +800000ec: 00300e13 li t3,3 +800000f0: 08000293 li t0,128 +800000f4: 30429073 csrw mie,t0 +800000f8: 00000013 nop +800000fc: 00000013 nop +80000100: 00000013 nop +80000104: 00000013 nop +80000108: 00000013 nop +8000010c: 00000013 nop +80000110: 00000013 nop +80000114: 00400e13 li t3,4 +80000118: 000012b7 lui t0,0x1 +8000011c: 80028293 addi t0,t0,-2048 # 800 <trap_entry-0x7ffff820> +80000120: 30429073 csrw mie,t0 +80000124: 00000013 nop +80000128: 00000013 nop +8000012c: 00000013 nop +80000130: 00000013 nop +80000134: 00000013 nop +80000138: 00000013 nop +8000013c: 00000013 nop +80000140: 00500e13 li t3,5 +80000144: f01001b7 lui gp,0xf0100 +80000148: f4018193 addi gp,gp,-192 # f00fff40 <unalignedPcA+0x700ffd64> +8000014c: 0001a203 lw tp,0(gp) +80000150: 0041a283 lw t0,4(gp) +80000154: 3ff20213 addi tp,tp,1023 # 3ff <trap_entry-0x7ffffc21> +80000158: 0041a423 sw tp,8(gp) +8000015c: 0051a623 sw t0,12(gp) +80000160: 00000013 nop +80000164: 00000013 nop +80000168: 00000013 nop +8000016c: 00000013 nop +80000170: 00000013 nop +80000174: 00000013 nop +80000178: 00000013 nop +8000017c: 00000013 nop +80000180: 00000013 nop +80000184: 00000013 nop +80000188: 00000013 nop +8000018c: 00000013 nop +80000190: 00000013 nop +80000194: 00000013 nop +80000198: 00600e13 li t3,6 +8000019c: 08000213 li tp,128 +800001a0: 30421073 csrw mie,tp +800001a4: 00700e13 li t3,7 +800001a8: 10500073 wfi +800001ac: 00800e13 li t3,8 +800001b0: 00100193 li gp,1 +800001b4: 0041a023 sw tp,0(gp) +800001b8: 00900e13 li t3,9 +800001bc: 00419023 sh tp,0(gp) +800001c0: 00a00e13 li t3,10 +800001c4: 0001a203 lw tp,0(gp) +800001c8: 00b00e13 li t3,11 +800001cc: 00019203 lh tp,0(gp) +800001d0: 00c00e13 li t3,12 +800001d4: 00d00e13 li t3,13 +800001d8: 00002083 lw ra,0(zero) # 0 <trap_entry-0x80000020> + +800001dc <unalignedPcA>: +800001dc: 0020006f j 800001de <unalignedPcA+0x2> +800001e0: 00002083 lw ra,0(zero) # 0 <trap_entry-0x80000020> +800001e4: 00e00e13 li t3,14 +800001e8: 20200073 hret +800001ec: 00f00e13 li t3,15 +800001f0: f01000b7 lui ra,0xf0100 +800001f4: f6008093 addi ra,ra,-160 # f00fff60 <unalignedPcA+0x700ffd84> +800001f8: 0000a103 lw sp,0(ra) +800001fc: 01000e13 li t3,16 +80000200: 0020a023 sw sp,0(ra) +80000204: 01100e13 li t3,17 +80000208: 00008067 ret + ... diff --git a/VexRiscv/src/test/cpp/raw/machineCsr/build/machineCsr.hex b/VexRiscv/src/test/cpp/raw/machineCsr/build/machineCsr.hex new file mode 100644 index 0000000..d6c33e7 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/machineCsr/build/machineCsr.hex @@ -0,0 +1,37 @@ +:0200000480007A
+:100000006F004009130000001300000013000000FF
+:100010001300000013000000130000001300000094
+:10002000732E2034631E0E00130FC0FFF32E103406
+:10003000B3FEEE01938E4E0073901E346F00C0012C
+:10004000B70E0080337FDE0163180F00F32E1034EB
+:10005000938E4E0073901E34B70E0080938E3E0038
+:100060006398CE01373C01F0930C000023209C01E3
+:10007000B70E0080938E7E006394CE0173504030A3
+:10008000B70E0080938EBE006394CE017350403053
+:1000900073002030130E100073000000130E2000B8
+:1000A0009302800073A0023093028000739042306C
+:1000B000373C01F0930C100023209C01130000003A
+:1000C00013000000130000001300000013000000E4
+:1000D00013000000130000001300000013000000D4
+:1000E000130000001300000013000000130E300086
+:1000F00093020008739042301300000013000000C8
+:1001000013000000130000001300000013000000A3
+:1001100013000000130E4000B7120000938202800B
+:100120007390423013000000130000001300000021
+:100130001300000013000000130000001300000073
+:10014000130E5000B70110F0938101F403A20100D7
+:1001500083A241001302F23F23A4410023A65100D1
+:100160001300000013000000130000001300000043
+:100170001300000013000000130000001300000033
+:100180001300000013000000130000001300000023
+:100190001300000013000000130E6000130200089B
+:1001A00073104230130E700073005010130E800055
+:1001B0009301100023A04100130E900023904100F2
+:1001C000130EA00003A20100130EB0000392010061
+:1001D000130EC000130ED000832000006F0020001B
+:1001E00083200000130EE00073002020130EF000A7
+:1001F000B70010F0938000F603A10000130E000179
+:1002000023A02000130E10016780000000000000F2
+:1002100000000000000000000000000000000000DE
+:0400000580000094E3
+:00000001FF
diff --git a/VexRiscv/src/test/cpp/raw/machineCsr/build/machineCsrCompressed.asm b/VexRiscv/src/test/cpp/raw/machineCsr/build/machineCsrCompressed.asm new file mode 100644 index 0000000..097f4e3 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/machineCsr/build/machineCsrCompressed.asm @@ -0,0 +1,155 @@ + +build/machineCsrCompressed.elf: file format elf32-littleriscv + + +Disassembly of section .crt_section: + +80000000 <trap_entry-0x20>: +80000000: 0940006f j 80000094 <_start> +80000004: 00000013 nop +80000008: 00000013 nop +8000000c: 00000013 nop +80000010: 00000013 nop +80000014: 00000013 nop +80000018: 00000013 nop +8000001c: 00000013 nop + +80000020 <trap_entry>: +80000020: 34202e73 csrr t3,mcause +80000024: 000e1e63 bnez t3,80000040 <notICmdAlignementException> +80000028: ffc00f13 li t5,-4 +8000002c: 34102ef3 csrr t4,mepc +80000030: 01eefeb3 and t4,t4,t5 +80000034: 004e8e93 addi t4,t4,4 +80000038: 341e9073 csrw mepc,t4 +8000003c: 01c0006f j 80000058 <mepcFixed> + +80000040 <notICmdAlignementException>: +80000040: 80000eb7 lui t4,0x80000 +80000044: 01de7f33 and t5,t3,t4 +80000048: 000f1863 bnez t5,80000058 <mepcFixed> +8000004c: 34102ef3 csrr t4,mepc +80000050: 004e8e93 addi t4,t4,4 # 80000004 <unalignedPcA+0xfffffe28> +80000054: 341e9073 csrw mepc,t4 + +80000058 <mepcFixed>: +80000058: 80000eb7 lui t4,0x80000 +8000005c: 003e8e93 addi t4,t4,3 # 80000003 <unalignedPcA+0xfffffe27> +80000060: 01ce9863 bne t4,t3,80000070 <noSoftwareInterrupt> +80000064: f0013c37 lui s8,0xf0013 +80000068: 00000c93 li s9,0 +8000006c: 019c2023 sw s9,0(s8) # f0013000 <unalignedPcA+0x70012e24> + +80000070 <noSoftwareInterrupt>: +80000070: 80000eb7 lui t4,0x80000 +80000074: 007e8e93 addi t4,t4,7 # 80000007 <unalignedPcA+0xfffffe2b> +80000078: 01ce9463 bne t4,t3,80000080 <noTimerInterrupt> +8000007c: 30405073 csrwi mie,0 + +80000080 <noTimerInterrupt>: +80000080: 80000eb7 lui t4,0x80000 +80000084: 00be8e93 addi t4,t4,11 # 8000000b <unalignedPcA+0xfffffe2f> +80000088: 01ce9463 bne t4,t3,80000090 <noExernalInterrupt> +8000008c: 30405073 csrwi mie,0 + +80000090 <noExernalInterrupt>: +80000090: 30200073 mret + +80000094 <_start>: +80000094: 00100e13 li t3,1 +80000098: 00000073 ecall +8000009c: 00200e13 li t3,2 +800000a0: 00800293 li t0,8 +800000a4: 3002a073 csrs mstatus,t0 +800000a8: 00800293 li t0,8 +800000ac: 30429073 csrw mie,t0 +800000b0: f0013c37 lui s8,0xf0013 +800000b4: 00100c93 li s9,1 +800000b8: 019c2023 sw s9,0(s8) # f0013000 <unalignedPcA+0x70012e24> +800000bc: 00000013 nop +800000c0: 00000013 nop +800000c4: 00000013 nop +800000c8: 00000013 nop +800000cc: 00000013 nop +800000d0: 00000013 nop +800000d4: 00000013 nop +800000d8: 00000013 nop +800000dc: 00000013 nop +800000e0: 00000013 nop +800000e4: 00000013 nop +800000e8: 00000013 nop +800000ec: 00300e13 li t3,3 +800000f0: 08000293 li t0,128 +800000f4: 30429073 csrw mie,t0 +800000f8: 00000013 nop +800000fc: 00000013 nop +80000100: 00000013 nop +80000104: 00000013 nop +80000108: 00000013 nop +8000010c: 00000013 nop +80000110: 00000013 nop +80000114: 00400e13 li t3,4 +80000118: 000012b7 lui t0,0x1 +8000011c: 80028293 addi t0,t0,-2048 # 800 <trap_entry-0x7ffff820> +80000120: 30429073 csrw mie,t0 +80000124: 00000013 nop +80000128: 00000013 nop +8000012c: 00000013 nop +80000130: 00000013 nop +80000134: 00000013 nop +80000138: 00000013 nop +8000013c: 00000013 nop +80000140: 00500e13 li t3,5 +80000144: f01001b7 lui gp,0xf0100 +80000148: f4018193 addi gp,gp,-192 # f00fff40 <unalignedPcA+0x700ffd64> +8000014c: 0001a203 lw tp,0(gp) +80000150: 0041a283 lw t0,4(gp) +80000154: 3ff20213 addi tp,tp,1023 # 3ff <trap_entry-0x7ffffc21> +80000158: 0041a423 sw tp,8(gp) +8000015c: 0051a623 sw t0,12(gp) +80000160: 00000013 nop +80000164: 00000013 nop +80000168: 00000013 nop +8000016c: 00000013 nop +80000170: 00000013 nop +80000174: 00000013 nop +80000178: 00000013 nop +8000017c: 00000013 nop +80000180: 00000013 nop +80000184: 00000013 nop +80000188: 00000013 nop +8000018c: 00000013 nop +80000190: 00000013 nop +80000194: 00000013 nop +80000198: 00600e13 li t3,6 +8000019c: 08000213 li tp,128 +800001a0: 30421073 csrw mie,tp +800001a4: 00700e13 li t3,7 +800001a8: 10500073 wfi +800001ac: 00800e13 li t3,8 +800001b0: 00100193 li gp,1 +800001b4: 0041a023 sw tp,0(gp) +800001b8: 00900e13 li t3,9 +800001bc: 00419023 sh tp,0(gp) +800001c0: 00a00e13 li t3,10 +800001c4: 0001a203 lw tp,0(gp) +800001c8: 00b00e13 li t3,11 +800001cc: 00019203 lh tp,0(gp) +800001d0: 00c00e13 li t3,12 +800001d4: 00d00e13 li t3,13 +800001d8: 00002083 lw ra,0(zero) # 0 <trap_entry-0x80000020> + +800001dc <unalignedPcA>: +800001dc: 0020006f j 800001de <unalignedPcA+0x2> +800001e0: 00002083 lw ra,0(zero) # 0 <trap_entry-0x80000020> +800001e4: 00e00e13 li t3,14 +800001e8: 20200073 hret +800001ec: 00f00e13 li t3,15 +800001f0: f01000b7 lui ra,0xf0100 +800001f4: f6008093 addi ra,ra,-160 # f00fff60 <unalignedPcA+0x700ffd84> +800001f8: 0000a103 lw sp,0(ra) +800001fc: 01000e13 li t3,16 +80000200: 0020a023 sw sp,0(ra) +80000204: 01100e13 li t3,17 +80000208: 00008067 ret + ... diff --git a/VexRiscv/src/test/cpp/raw/machineCsr/build/machineCsrCompressed.hex b/VexRiscv/src/test/cpp/raw/machineCsr/build/machineCsrCompressed.hex new file mode 100644 index 0000000..d6c33e7 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/machineCsr/build/machineCsrCompressed.hex @@ -0,0 +1,37 @@ +:0200000480007A
+:100000006F004009130000001300000013000000FF
+:100010001300000013000000130000001300000094
+:10002000732E2034631E0E00130FC0FFF32E103406
+:10003000B3FEEE01938E4E0073901E346F00C0012C
+:10004000B70E0080337FDE0163180F00F32E1034EB
+:10005000938E4E0073901E34B70E0080938E3E0038
+:100060006398CE01373C01F0930C000023209C01E3
+:10007000B70E0080938E7E006394CE0173504030A3
+:10008000B70E0080938EBE006394CE017350403053
+:1000900073002030130E100073000000130E2000B8
+:1000A0009302800073A0023093028000739042306C
+:1000B000373C01F0930C100023209C01130000003A
+:1000C00013000000130000001300000013000000E4
+:1000D00013000000130000001300000013000000D4
+:1000E000130000001300000013000000130E300086
+:1000F00093020008739042301300000013000000C8
+:1001000013000000130000001300000013000000A3
+:1001100013000000130E4000B7120000938202800B
+:100120007390423013000000130000001300000021
+:100130001300000013000000130000001300000073
+:10014000130E5000B70110F0938101F403A20100D7
+:1001500083A241001302F23F23A4410023A65100D1
+:100160001300000013000000130000001300000043
+:100170001300000013000000130000001300000033
+:100180001300000013000000130000001300000023
+:100190001300000013000000130E6000130200089B
+:1001A00073104230130E700073005010130E800055
+:1001B0009301100023A04100130E900023904100F2
+:1001C000130EA00003A20100130EB0000392010061
+:1001D000130EC000130ED000832000006F0020001B
+:1001E00083200000130EE00073002020130EF000A7
+:1001F000B70010F0938000F603A10000130E000179
+:1002000023A02000130E10016780000000000000F2
+:1002100000000000000000000000000000000000DE
+:0400000580000094E3
+:00000001FF
diff --git a/VexRiscv/src/test/cpp/raw/machineCsr/makefile b/VexRiscv/src/test/cpp/raw/machineCsr/makefile new file mode 100644 index 0000000..4fc2c84 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/machineCsr/makefile @@ -0,0 +1,11 @@ +ifeq ($(COMPRESSED),yes) + PROJ_NAME=machineCsrCompressed + CFLAGS=-DCOMPRESSED +else + PROJ_NAME=machineCsr +endif + + + + +include ../common/asm.mk
\ No newline at end of file diff --git a/VexRiscv/src/test/cpp/raw/machineCsr/src/crt.S b/VexRiscv/src/test/cpp/raw/machineCsr/src/crt.S new file mode 100644 index 0000000..91429db --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/machineCsr/src/crt.S @@ -0,0 +1,157 @@ + j _start + +#define writeSoftwareInterrupt(value) \ + li x24, 0xF0013000; \ + li x25, value; \ + sw x25, 0(x24); \ + +.align 5 +.global trap_entry +trap_entry: + csrr x28, mcause + + bnez x28, notICmdAlignementException + li x30, 0xFFFFFFFC + csrr x29, mepc + and x29,x29,x30 + addi x29, x29, 4 + csrw mepc, x29 + j mepcFixed + +notICmdAlignementException: + li x29, 0x80000000 + and x30, x28, x29 + bnez x30, mepcFixed + csrr x29, mepc + addi x29, x29, 4 + csrw mepc, x29 +mepcFixed: + + + li x29, 0x80000003u + bne x29, x28, noSoftwareInterrupt + writeSoftwareInterrupt(0) + +noSoftwareInterrupt: + + li x29, 0x80000007u + bne x29, x28, noTimerInterrupt + csrw mie, 0 +noTimerInterrupt: + + li x29, 0x8000000bu + bne x29, x28, noExernalInterrupt + csrw mie, 0 +noExernalInterrupt: + + mret + + + .text + .globl _start +_start: + li x28, 1 + ecall + + li x28, 2 + li t0, 0x008 + csrs mstatus,t0 + li t0, 0x008 + csrw mie,t0 + writeSoftwareInterrupt(1) + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + + + li x28, 3 + li t0, 0x080 + csrw mie,t0 + nop + nop + nop + nop + nop + nop + nop + + li x28, 4 + li t0, 0x800 + csrw mie,t0 + nop + nop + nop + nop + nop + nop + nop + + li x28, 5 + li x3, 0xF00FFF40 + lw x4, 0(x3) + lw x5, 4(x3) + addi x4, x4, 1023 + sw x4, 8(x3) + sw x5, 12(x3) + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + li x28, 6 + li x4, 0x080 + csrw mie,x4 + li x28, 7 + wfi + + + li x28, 8 + li x3, 1 + sw x4,0(x3) + li x28, 9 + sh x4,0(x3) + li x28, 10 + lw x4,0(x3) + li x28, 11 + lh x4,0(x3) + li x28, 12 + + + + li x28, 13 + lw x1,0(x0) +#ifndef COMPRESSED +unalignedPcA: + j unalignedPcA+2 +#endif + lw x1,0(x0) + + li x28, 14 + hret + li x28, 15 + + + li x1, 0xF00FFF60 + lw x2, 0(x1) + li x28, 16 + sw x2, 0(x1) + li x28, 17 + jr x1 diff --git a/VexRiscv/src/test/cpp/raw/machineCsr/src/ld b/VexRiscv/src/test/cpp/raw/machineCsr/src/ld new file mode 100644 index 0000000..93d8de8 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/machineCsr/src/ld @@ -0,0 +1,16 @@ +OUTPUT_ARCH( "riscv" ) + +MEMORY { + onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 128K +} + +SECTIONS +{ + + .crt_section : + { + . = ALIGN(4); + *crt.o(.text) + } > onChipRam + +} diff --git a/VexRiscv/src/test/cpp/raw/mmu/.gitignore b/VexRiscv/src/test/cpp/raw/mmu/.gitignore new file mode 100644 index 0000000..c12cb2c --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/mmu/.gitignore @@ -0,0 +1,4 @@ +*.map +*.v +*.elf +*.o
\ No newline at end of file diff --git a/VexRiscv/src/test/cpp/raw/mmu/build/mmu.asm b/VexRiscv/src/test/cpp/raw/mmu/build/mmu.asm new file mode 100644 index 0000000..9bbf17f --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/mmu/build/mmu.asm @@ -0,0 +1,12430 @@ + +build/mmu.elf: file format elf32-littleriscv + + +Disassembly of section .crt_section: + +80000000 <_start>: +80000000: 00000e93 li t4,0 +80000004: 00000097 auipc ra,0x0 +80000008: 59008093 addi ra,ra,1424 # 80000594 <trap> +8000000c: 30509073 csrw mtvec,ra + +80000010 <test1>: +80000010: 00100e13 li t3,1 +80000014: 00007097 auipc ra,0x7 +80000018: fec08093 addi ra,ra,-20 # 80007000 <ROM_2> +8000001c: 27262137 lui sp,0x27262 +80000020: 52410113 addi sp,sp,1316 # 27262524 <_start-0x58d9dadc> +80000024: 0040a083 lw ra,4(ra) +80000028: 54209263 bne ra,sp,8000056c <fail> + +8000002c <test2>: +8000002c: 00200e13 li t3,2 +80000030: 00000097 auipc ra,0x0 +80000034: 02008093 addi ra,ra,32 # 80000050 <test3> +80000038: 34109073 csrw mepc,ra +8000003c: 000020b7 lui ra,0x2 +80000040: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> +80000044: 30009073 csrw mstatus,ra +80000048: 30200073 mret +8000004c: 5200006f j 8000056c <fail> + +80000050 <test3>: +80000050: 00300e13 li t3,3 +80000054: 000010b7 lui ra,0x1 +80000058: 80008093 addi ra,ra,-2048 # 800 <_start-0x7ffff800> +8000005c: 30009073 csrw mstatus,ra +80000060: 00000097 auipc ra,0x0 +80000064: 01408093 addi ra,ra,20 # 80000074 <test4> +80000068: 34109073 csrw mepc,ra +8000006c: 30200073 mret +80000070: 4fc0006f j 8000056c <fail> + +80000074 <test4>: +80000074: 00400e13 li t3,4 +80000078: 00008097 auipc ra,0x8 +8000007c: f8808093 addi ra,ra,-120 # 80008000 <ROM_3> +80000080: 37363137 lui sp,0x37363 +80000084: 53410113 addi sp,sp,1332 # 37363534 <_start-0x48c9cacc> +80000088: 0040a083 lw ra,4(ra) +8000008c: 4e209063 bne ra,sp,8000056c <fail> + +80000090 <test5>: +80000090: 00500e13 li t3,5 +80000094: 00001097 auipc ra,0x1 +80000098: 76c08093 addi ra,ra,1900 # 80001800 <MMU_TABLE_0+0x800> +8000009c: 00002117 auipc sp,0x2 +800000a0: f6410113 addi sp,sp,-156 # 80002000 <MMU_TABLE_1> +800000a4: 00215113 srli sp,sp,0x2 +800000a8: 01116113 ori sp,sp,17 +800000ac: 0020a023 sw sp,0(ra) +800000b0: 00002097 auipc ra,0x2 +800000b4: f5008093 addi ra,ra,-176 # 80002000 <MMU_TABLE_1> +800000b8: 80000137 lui sp,0x80000 +800000bc: 00215113 srli sp,sp,0x2 +800000c0: 00f16113 ori sp,sp,15 +800000c4: 0020a023 sw sp,0(ra) +800000c8: 00500e13 li t3,5 +800000cc: 00002097 auipc ra,0x2 +800000d0: 83408093 addi ra,ra,-1996 # 80001900 <MMU_TABLE_0+0x900> +800000d4: 00003117 auipc sp,0x3 +800000d8: f2c10113 addi sp,sp,-212 # 80003000 <MMU_TABLE_2> +800000dc: 00215113 srli sp,sp,0x2 +800000e0: 01116113 ori sp,sp,17 +800000e4: 0020a023 sw sp,0(ra) +800000e8: 00003097 auipc ra,0x3 +800000ec: f4008093 addi ra,ra,-192 # 80003028 <MMU_TABLE_2+0x28> +800000f0: 00009117 auipc sp,0x9 +800000f4: f1010113 addi sp,sp,-240 # 80009000 <ROM_4> +800000f8: 00215113 srli sp,sp,0x2 +800000fc: 01f16113 ori sp,sp,31 +80000100: 0020a023 sw sp,0(ra) +80000104: 00003097 auipc ra,0x3 +80000108: f3c08093 addi ra,ra,-196 # 80003040 <MMU_TABLE_2+0x40> +8000010c: 0000a117 auipc sp,0xa +80000110: ef410113 addi sp,sp,-268 # 8000a000 <ROM_5> +80000114: 00215113 srli sp,sp,0x2 +80000118: 01316113 ori sp,sp,19 +8000011c: 0020a023 sw sp,0(ra) +80000120: 00003097 auipc ra,0x3 +80000124: f2408093 addi ra,ra,-220 # 80003044 <MMU_TABLE_2+0x44> +80000128: 0000a117 auipc sp,0xa +8000012c: ed810113 addi sp,sp,-296 # 8000a000 <ROM_5> +80000130: 00215113 srli sp,sp,0x2 +80000134: 01716113 ori sp,sp,23 +80000138: 0020a023 sw sp,0(ra) +8000013c: 00003097 auipc ra,0x3 +80000140: f0c08093 addi ra,ra,-244 # 80003048 <MMU_TABLE_2+0x48> +80000144: 0000a117 auipc sp,0xa +80000148: ebc10113 addi sp,sp,-324 # 8000a000 <ROM_5> +8000014c: 00215113 srli sp,sp,0x2 +80000150: 01916113 ori sp,sp,25 +80000154: 0020a023 sw sp,0(ra) +80000158: 00003097 auipc ra,0x3 +8000015c: ef408093 addi ra,ra,-268 # 8000304c <MMU_TABLE_2+0x4c> +80000160: 0000a117 auipc sp,0xa +80000164: ea010113 addi sp,sp,-352 # 8000a000 <ROM_5> +80000168: 00215113 srli sp,sp,0x2 +8000016c: 01b16113 ori sp,sp,27 +80000170: 0020a023 sw sp,0(ra) +80000174: 00003097 auipc ra,0x3 +80000178: edc08093 addi ra,ra,-292 # 80003050 <MMU_TABLE_2+0x50> +8000017c: 0000a117 auipc sp,0xa +80000180: e8410113 addi sp,sp,-380 # 8000a000 <ROM_5> +80000184: 00215113 srli sp,sp,0x2 +80000188: 00f16113 ori sp,sp,15 +8000018c: 0020a023 sw sp,0(ra) +80000190: 00500e13 li t3,5 +80000194: 00002097 auipc ra,0x2 +80000198: 86c08093 addi ra,ra,-1940 # 80001a00 <MMU_TABLE_0+0xa00> +8000019c: 00000117 auipc sp,0x0 +800001a0: e6410113 addi sp,sp,-412 # 80000000 <_start> +800001a4: 00215113 srli sp,sp,0x2 +800001a8: 01f16113 ori sp,sp,31 +800001ac: 0020a023 sw sp,0(ra) +800001b0: 00500e13 li t3,5 +800001b4: 00002097 auipc ra,0x2 +800001b8: 94c08093 addi ra,ra,-1716 # 80001b00 <MMU_TABLE_0+0xb00> +800001bc: 0000a023 sw zero,0(ra) +800001c0: 000400b7 lui ra,0x40 +800001c4: 1000a073 csrs sstatus,ra +800001c8: 00001097 auipc ra,0x1 +800001cc: e3808093 addi ra,ra,-456 # 80001000 <MMU_TABLE_0> +800001d0: 00c0d093 srli ra,ra,0xc +800001d4: 80000137 lui sp,0x80000 +800001d8: 0020e0b3 or ra,ra,sp +800001dc: 18009073 csrw satp,ra + +800001e0 <test6>: +800001e0: 00600e13 li t3,6 +800001e4: 9000a0b7 lui ra,0x9000a +800001e8: 00808093 addi ra,ra,8 # 9000a008 <ROM_7+0xfffe008> +800001ec: 4b4a5137 lui sp,0x4b4a5 +800001f0: 94810113 addi sp,sp,-1720 # 4b4a4948 <_start-0x34b5b6b8> +800001f4: 0000a083 lw ra,0(ra) +800001f8: 36209a63 bne ra,sp,8000056c <fail> + +800001fc <test7>: +800001fc: 00700e13 li t3,7 +80000200: 9000a0b7 lui ra,0x9000a +80000204: 36008093 addi ra,ra,864 # 9000a360 <ROM_7+0xfffe360> +80000208: aaee0137 lui sp,0xaaee0 +8000020c: 00110113 addi sp,sp,1 # aaee0001 <ROM_7+0x2aed4001> +80000210: 0020a023 sw sp,0(ra) +80000214: 0000a083 lw ra,0(ra) +80000218: 34209a63 bne ra,sp,8000056c <fail> + +8000021c <test8>: +8000021c: 00800e13 li t3,8 +80000220: 2000c097 auipc ra,0x2000c +80000224: de408093 addi ra,ra,-540 # a000c004 <ROM_7+0x20000004> +80000228: 77767137 lui sp,0x77767 +8000022c: 57410113 addi sp,sp,1396 # 77767574 <_start-0x8898a8c> +80000230: 0000a083 lw ra,0(ra) +80000234: 32209c63 bne ra,sp,8000056c <fail> + +80000238 <test9>: +80000238: 00900e13 li t3,9 +8000023c: a000a0b7 lui ra,0xa000a +80000240: 36008093 addi ra,ra,864 # a000a360 <ROM_7+0x1fffe360> +80000244: aaee0137 lui sp,0xaaee0 +80000248: 00210113 addi sp,sp,2 # aaee0002 <ROM_7+0x2aed4002> +8000024c: 0020a023 sw sp,0(ra) +80000250: 0000a083 lw ra,0(ra) +80000254: 30209c63 bne ra,sp,8000056c <fail> + +80000258 <test10>: +80000258: 00a00e13 li t3,10 +8000025c: 18005073 csrwi satp,0 +80000260: 00009097 auipc ra,0x9 +80000264: 10008093 addi ra,ra,256 # 80009360 <ROM_4+0x360> +80000268: aaee0137 lui sp,0xaaee0 +8000026c: 00110113 addi sp,sp,1 # aaee0001 <ROM_7+0x2aed4001> +80000270: 0000a083 lw ra,0(ra) +80000274: 2e209c63 bne ra,sp,8000056c <fail> + +80000278 <test11>: +80000278: 00b00e13 li t3,11 +8000027c: 0000a097 auipc ra,0xa +80000280: 0e408093 addi ra,ra,228 # 8000a360 <ROM_5+0x360> +80000284: aaee0137 lui sp,0xaaee0 +80000288: 00210113 addi sp,sp,2 # aaee0002 <ROM_7+0x2aed4002> +8000028c: 0000a083 lw ra,0(ra) +80000290: 2c209e63 bne ra,sp,8000056c <fail> +80000294: 00001097 auipc ra,0x1 +80000298: d6c08093 addi ra,ra,-660 # 80001000 <MMU_TABLE_0> +8000029c: 00c0d093 srli ra,ra,0xc +800002a0: 80000137 lui sp,0x80000 +800002a4: 0020e0b3 or ra,ra,sp +800002a8: 18009073 csrw satp,ra + +800002ac <test12>: +800002ac: 00c00e13 li t3,12 +800002b0: 00100e93 li t4,1 +800002b4: 00000f17 auipc t5,0x0 +800002b8: 010f0f13 addi t5,t5,16 # 800002c4 <test13> +800002bc: 00000073 ecall +800002c0: 2ac0006f j 8000056c <fail> + +800002c4 <test13>: +800002c4: 00d00e13 li t3,13 +800002c8: 00000f17 auipc t5,0x0 +800002cc: 014f0f13 addi t5,t5,20 # 800002dc <test14> +800002d0: b00000b7 lui ra,0xb0000 +800002d4: 0080a083 lw ra,8(ra) # b0000008 <ROM_7+0x2fff4008> +800002d8: 2940006f j 8000056c <fail> + +800002dc <test14>: +800002dc: 00e00e13 li t3,14 +800002e0: 00000f17 auipc t5,0x0 +800002e4: 014f0f13 addi t5,t5,20 # 800002f4 <test15> +800002e8: b00000b7 lui ra,0xb0000 +800002ec: 0010a423 sw ra,8(ra) # b0000008 <ROM_7+0x2fff4008> +800002f0: 27c0006f j 8000056c <fail> + +800002f4 <test15>: +800002f4: 00f00e13 li t3,15 +800002f8: 00000f17 auipc t5,0x0 +800002fc: 014f0f13 addi t5,t5,20 # 8000030c <test15_end> +80000300: b00000b7 lui ra,0xb0000 +80000304: 00008067 ret +80000308: 2640006f j 8000056c <fail> + +8000030c <test15_end>: +8000030c: 01000e13 li t3,16 +80000310: 00000e93 li t4,0 +80000314: 900100b7 lui ra,0x90010 +80000318: 00808093 addi ra,ra,8 # 90010008 <ROM_7+0x10004008> +8000031c: 5b5a6137 lui sp,0x5b5a6 +80000320: 95810113 addi sp,sp,-1704 # 5b5a5958 <_start-0x24a5a6a8> +80000324: 0000a083 lw ra,0(ra) +80000328: 24209263 bne ra,sp,8000056c <fail> +8000032c: 900110b7 lui ra,0x90011 +80000330: 00808093 addi ra,ra,8 # 90011008 <ROM_7+0x10005008> +80000334: 5b5a6137 lui sp,0x5b5a6 +80000338: 95810113 addi sp,sp,-1704 # 5b5a5958 <_start-0x24a5a6a8> +8000033c: 0000a083 lw ra,0(ra) +80000340: 22209663 bne ra,sp,8000056c <fail> +80000344: 900130b7 lui ra,0x90013 +80000348: 00808093 addi ra,ra,8 # 90013008 <ROM_7+0x10007008> +8000034c: 5b5a6137 lui sp,0x5b5a6 +80000350: 95810113 addi sp,sp,-1704 # 5b5a5958 <_start-0x24a5a6a8> +80000354: 0000a083 lw ra,0(ra) +80000358: 20209a63 bne ra,sp,8000056c <fail> + +8000035c <test17>: +8000035c: 01100e13 li t3,17 +80000360: 900110b7 lui ra,0x90011 +80000364: 36008093 addi ra,ra,864 # 90011360 <ROM_7+0x10005360> +80000368: aaee0137 lui sp,0xaaee0 +8000036c: 00310113 addi sp,sp,3 # aaee0003 <ROM_7+0x2aed4003> +80000370: 0020a023 sw sp,0(ra) +80000374: 0000a083 lw ra,0(ra) +80000378: 1e209a63 bne ra,sp,8000056c <fail> + +8000037c <test18>: +8000037c: 01200e13 li t3,18 +80000380: 00000097 auipc ra,0x0 +80000384: 01808093 addi ra,ra,24 # 80000398 <test18_end> +80000388: 90012137 lui sp,0x90012 +8000038c: 01010113 addi sp,sp,16 # 90012010 <ROM_7+0x10006010> +80000390: 00010067 jr sp +80000394: 1d80006f j 8000056c <fail> + +80000398 <test18_end>: +80000398: 01300e13 li t3,19 +8000039c: 00100e93 li t4,1 +800003a0: 00000f17 auipc t5,0x0 +800003a4: 018f0f13 addi t5,t5,24 # 800003b8 <test19_readTrap> +800003a8: 900120b7 lui ra,0x90012 +800003ac: 01008093 addi ra,ra,16 # 90012010 <ROM_7+0x10006010> +800003b0: 0000a083 lw ra,0(ra) +800003b4: 1b80006f j 8000056c <fail> + +800003b8 <test19_readTrap>: +800003b8: 00000f17 auipc t5,0x0 +800003bc: 018f0f13 addi t5,t5,24 # 800003d0 <test19_writeTrap> +800003c0: 900130b7 lui ra,0x90013 +800003c4: 01008093 addi ra,ra,16 # 90013010 <ROM_7+0x10007010> +800003c8: 0010a023 sw ra,0(ra) +800003cc: 1a00006f j 8000056c <fail> + +800003d0 <test19_writeTrap>: +800003d0: 00000f17 auipc t5,0x0 +800003d4: 018f0f13 addi t5,t5,24 # 800003e8 <test19_executeTrap> +800003d8: 900110b7 lui ra,0x90011 +800003dc: 01008093 addi ra,ra,16 # 90011010 <ROM_7+0x10005010> +800003e0: 00008067 ret +800003e4: 1880006f j 8000056c <fail> + +800003e8 <test19_executeTrap>: +800003e8: 01500e13 li t3,21 +800003ec: 00000e93 li t4,0 +800003f0: 000800b7 lui ra,0x80 +800003f4: 1000a073 csrs sstatus,ra +800003f8: 900120b7 lui ra,0x90012 +800003fc: 00808093 addi ra,ra,8 # 90012008 <ROM_7+0x10006008> +80000400: 5b5a6137 lui sp,0x5b5a6 +80000404: 95810113 addi sp,sp,-1704 # 5b5a5958 <_start-0x24a5a6a8> +80000408: 0000a083 lw ra,0(ra) +8000040c: 16209063 bne ra,sp,8000056c <fail> +80000410: 000800b7 lui ra,0x80 +80000414: 1000b073 csrc sstatus,ra + +80000418 <test21>: +80000418: 00000e93 li t4,0 +8000041c: 01400e13 li t3,20 +80000420: 900140b7 lui ra,0x90014 +80000424: 38008093 addi ra,ra,896 # 90014380 <ROM_7+0x10008380> +80000428: aaee0137 lui sp,0xaaee0 +8000042c: 00510113 addi sp,sp,5 # aaee0005 <ROM_7+0x2aed4005> +80000430: 0020a023 sw sp,0(ra) +80000434: 0000a083 lw ra,0(ra) +80000438: 12209a63 bne ra,sp,8000056c <fail> +8000043c: 000400b7 lui ra,0x40 +80000440: 1000b073 csrc sstatus,ra +80000444: 00100e93 li t4,1 +80000448: 00000f17 auipc t5,0x0 +8000044c: 018f0f13 addi t5,t5,24 # 80000460 <test21_pass> +80000450: 900110b7 lui ra,0x90011 +80000454: 64808093 addi ra,ra,1608 # 90011648 <ROM_7+0x10005648> +80000458: 0010a023 sw ra,0(ra) +8000045c: 1100006f j 8000056c <fail> + +80000460 <test21_pass>: +80000460: 03200e13 li t3,50 +80000464: 00000e93 li t4,0 +80000468: 000400b7 lui ra,0x40 +8000046c: 1000a073 csrs sstatus,ra +80000470: 18002573 csrr a0,satp +80000474: 18001073 csrw satp,zero +80000478: 00002097 auipc ra,0x2 +8000047c: b8808093 addi ra,ra,-1144 # 80002000 <MMU_TABLE_1> +80000480: 80000137 lui sp,0x80000 +80000484: 00215113 srli sp,sp,0x2 +80000488: 01f16113 ori sp,sp,31 +8000048c: 0020a023 sw sp,0(ra) +80000490: 18051073 csrw satp,a0 +80000494: 10000093 li ra,256 +80000498: 1000b073 csrc sstatus,ra +8000049c: 00000097 auipc ra,0x0 +800004a0: 01808093 addi ra,ra,24 # 800004b4 <test51> +800004a4: 14109073 csrw sepc,ra +800004a8: 12000073 sfence.vma +800004ac: 10200073 sret +800004b0: 0bc0006f j 8000056c <fail> + +800004b4 <test51>: +800004b4: 03300e13 li t3,51 +800004b8: 900110b7 lui ra,0x90011 +800004bc: 00808093 addi ra,ra,8 # 90011008 <ROM_7+0x10005008> +800004c0: 5b5a6137 lui sp,0x5b5a6 +800004c4: 95810113 addi sp,sp,-1704 # 5b5a5958 <_start-0x24a5a6a8> +800004c8: 0000a083 lw ra,0(ra) +800004cc: 0a209063 bne ra,sp,8000056c <fail> +800004d0: a000a0b7 lui ra,0xa000a +800004d4: 32408093 addi ra,ra,804 # a000a324 <ROM_7+0x1fffe324> +800004d8: aaee0137 lui sp,0xaaee0 +800004dc: 00810113 addi sp,sp,8 # aaee0008 <ROM_7+0x2aed4008> +800004e0: 0020a023 sw sp,0(ra) +800004e4: 0000a083 lw ra,0(ra) +800004e8: 08209263 bne ra,sp,8000056c <fail> + +800004ec <test52>: +800004ec: 03400e13 li t3,52 +800004f0: 00000097 auipc ra,0x0 +800004f4: 01808093 addi ra,ra,24 # 80000508 <test53> +800004f8: 90012137 lui sp,0x90012 +800004fc: 01010113 addi sp,sp,16 # 90012010 <ROM_7+0x10006010> +80000500: 00010067 jr sp +80000504: 0680006f j 8000056c <fail> + +80000508 <test53>: +80000508: 03500e13 li t3,53 +8000050c: 00100e93 li t4,1 +80000510: 00000f17 auipc t5,0x0 +80000514: 018f0f13 addi t5,t5,24 # 80000528 <test54> +80000518: 900140b7 lui ra,0x90014 +8000051c: 39008093 addi ra,ra,912 # 90014390 <ROM_7+0x10008390> +80000520: 00008067 ret +80000524: 0480006f j 8000056c <fail> + +80000528 <test54>: +80000528: 03600e13 li t3,54 +8000052c: 00100e93 li t4,1 +80000530: 00000f17 auipc t5,0x0 +80000534: 018f0f13 addi t5,t5,24 # 80000548 <test55> +80000538: 900140b7 lui ra,0x90014 +8000053c: 39408093 addi ra,ra,916 # 90014394 <ROM_7+0x10008394> +80000540: 0000a083 lw ra,0(ra) +80000544: 0280006f j 8000056c <fail> + +80000548 <test55>: +80000548: 03700e13 li t3,55 +8000054c: 00100e93 li t4,1 +80000550: 00000f17 auipc t5,0x0 +80000554: 018f0f13 addi t5,t5,24 # 80000568 <test56> +80000558: 900140b7 lui ra,0x90014 +8000055c: 39808093 addi ra,ra,920 # 90014398 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diff --git a/VexRiscv/src/test/cpp/raw/mmu/makefile b/VexRiscv/src/test/cpp/raw/mmu/makefile new file mode 100644 index 0000000..961e3bc --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/mmu/makefile @@ -0,0 +1,3 @@ +PROJ_NAME=mmu + +include ../common/asm.mk
\ No newline at end of file diff --git a/VexRiscv/src/test/cpp/raw/mmu/src/crt.S b/VexRiscv/src/test/cpp/raw/mmu/src/crt.S new file mode 100644 index 0000000..2f85bbe --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/mmu/src/crt.S @@ -0,0 +1,526 @@ +.globl _start + +#define TEST_ID x28 +#define TRAP_OK x29 +#define TRAP_RET x30 + + +ROM_SUPER_0: + +_start: + li TRAP_OK, 0 //Do not allow trap + la x1, trap + csrw mtvec, x1 + +test1: //test ram + li TEST_ID, 1 + la x1, ROM_2 + li x2, 0x27262524 + lw x1, 4(x1) + bne x1, x2, fail + +test2: //dummy mret + li TEST_ID, 2 + la x1, test3 + csrw mepc, x1 + li x1, 0x1800 + csrw mstatus, x1 + mret + j fail + + +test3: // jump to supervisor + li TEST_ID, 3 + li x1, 0x0800 + csrw mstatus, x1 + la x1, test4 + csrw mepc, x1 + mret + j fail + + + +test4: //test ram mmu off + li TEST_ID, 4 + la x1, ROM_3 + li x2, 0x37363534 + lw x1, 4(x1) + bne x1, x2, fail + +test5: //setup MMU + + li TEST_ID, 5 + la x1, MMU_TABLE_0 + 0x800 + la x2, MMU_TABLE_1 + srli x2, x2, 2 + ori x2, x2, 0x11 + sw x2, 0(x1) + + la x1, MMU_TABLE_1 + 0x000*4 + li x2, 0x80000000 + srli x2, x2, 2 + ori x2, x2, 0x0F + sw x2, 0(x1) + + + li TEST_ID, 5 + la x1, MMU_TABLE_0 + 0x900 + la x2, MMU_TABLE_2 + srli x2, x2, 2 + ori x2, x2, 0x11 + sw x2, 0(x1) + + la x1, MMU_TABLE_2 + 0x00A*4 + la x2, ROM_4 + srli x2, x2, 2 + ori x2, x2, 0x1F + sw x2, 0(x1) + + la x1, MMU_TABLE_2 + 0x010*4 // Read Only + la x2, ROM_5 + srli x2, x2, 2 + ori x2, x2, 0x11 + (0x1 << 1) + sw x2, 0(x1) + + la x1, MMU_TABLE_2 + 0x011*4 // Read Write + la x2, ROM_5 + srli x2, x2, 2 + ori x2, x2, 0x11 + (0x3 << 1) + sw x2, 0(x1) + + la x1, MMU_TABLE_2 + 0x012*4 // Execute only + la x2, ROM_5 + srli x2, x2, 2 + ori x2, x2, 0x11 + (0x4 << 1) + sw x2, 0(x1) + + la x1, MMU_TABLE_2 + 0x013*4 //Read Execute + la x2, ROM_5 + srli x2, x2, 2 + ori x2, x2, 0x11 + (0x5 << 1) + sw x2, 0(x1) + + la x1, MMU_TABLE_2 + 0x014*4 //no user + la x2, ROM_5 + srli x2, x2, 2 + ori x2, x2, 0x01 + (0x7 << 1) + sw x2, 0(x1) + + li TEST_ID, 5 + la x1, MMU_TABLE_0 + 0xA00 + la x2, ROM_SUPER_0 + srli x2, x2, 2 + ori x2, x2, 0x1F + sw x2, 0(x1) + + li TEST_ID, 5 + la x1, MMU_TABLE_0 + 0xB00 + sw x0, 0(x1) + + li x1, 1 << 18 //SUM + csrs sstatus, x1 + + la x1, MMU_TABLE_0 + srli x1, x1, 12 + li x2, 0x80000000 + or x1, x1, x2 + csrw satp, x1 + + +test6: //read through MMU + li TEST_ID, 6 + li x1, 0x9000A008 + li x2, 0x4B4A4948 + lw x1, 0(x1) + bne x1, x2, fail + + + +test7: //write-read through MMU + li TEST_ID, 7 + li x1, 0x9000A360 + li x2, 0xAAEE0001 + sw x2, 0(x1) + lw x1, 0(x1) + bne x1, x2, fail + + +test8: //read through MMU super page + li TEST_ID, 8 + la x1, ROM_7 + 0x20000004 + li x2, 0x77767574 + lw x1, 0(x1) + bne x1, x2, fail + + + +test9: //write-read through MMU super page + li TEST_ID, 9 + li x1, 0xA000A360 + li x2, 0xAAEE0002 + sw x2, 0(x1) + lw x1, 0(x1) + bne x1, x2, fail + + + +test10: //check previously written value without the MMU + li TEST_ID, 10 + csrwi satp, 0 + + la x1, ROM_4 + 0x360 + li x2, 0xAAEE0001 + lw x1, 0(x1) + bne x1, x2, fail + + +test11: + li TEST_ID, 11 + la x1, ROM_SUPER_0 + 0xA360 + li x2, 0xAAEE0002 + lw x1, 0(x1) + bne x1, x2, fail + + + la x1, MMU_TABLE_0 + srli x1, x1, 12 + li x2, 0x80000000 + or x1, x1, x2 + csrw satp, x1 + + +test12: //Dummy trap + li TEST_ID, 12 + li TRAP_OK, 1 //Allow trap + la TRAP_RET, test13 // trap return address + ecall + j fail + + +test13: //Trap load page fault + li TEST_ID, 13 + la TRAP_RET, test14 + li x1, 0xB0000000 + lw x1, 8(x1) + j fail + + +test14: //Trap store page fault + li TEST_ID, 14 + la TRAP_RET, test15 + li x1, 0xB0000000 + sw x1, 8(x1) + j fail + + +test15: //Trap instruction fetch + li TEST_ID, 15 + la TRAP_RET, test15_end + li x1, 0xB0000000 + jr x1 + j fail + +test15_end: + + +test16: //Test limited read access + li TEST_ID, 16 + li TRAP_OK, 0 //disable trap + + li x1, 0x90010008 + li x2, 0x5B5A5958 + lw x1, 0(x1) + bne x1, x2, fail + + + li x1, 0x90011008 + li x2, 0x5B5A5958 + lw x1, 0(x1) + bne x1, x2, fail + + li x1, 0x90013008 + li x2, 0x5B5A5958 + lw x1, 0(x1) + bne x1, x2, fail + +test17: //Test limited write access + li TEST_ID, 17 + + li x1, 0x90011360 + li x2, 0xAAEE0003 + sw x2, 0(x1) + lw x1, 0(x1) + bne x1, x2, fail + +test18: //Test limited execute access + li TEST_ID, 18 + + la x1, test18_end + li x2, 0x90012010 + jr x2 + j fail +test18_end: + + +test19: //exception by access limitations + li TEST_ID, 19 + li TRAP_OK, 1 //Allow trap + la TRAP_RET, test19_readTrap + li x1, 0x90012010 + lw x1, 0(x1) + j fail +test19_readTrap: + la TRAP_RET, test19_writeTrap + li x1, 0x90013010 + sw x1, 0(x1) + j fail +test19_writeTrap: + la TRAP_RET, test19_executeTrap + li x1, 0x90011010 + jr x1 + j fail +test19_executeTrap: + + +test20: //mxr set, read executable + li TEST_ID, 21 + li TRAP_OK, 0 + li x1, 1 << 19 + csrs sstatus, x1 + li x1, 0x90012008 + li x2, 0x5B5A5958 + lw x1, 0(x1) + bne x1, x2, fail + li x1, 1 << 19 + csrc sstatus, x1 + + +test21: //supervisor accessing not user + li TRAP_OK, 0 + li TEST_ID, 20 + li x1, 0x90014380 + li x2, 0xAAEE0005 + sw x2, 0(x1) + lw x1, 0(x1) + bne x1, x2, fail + + + + li x1, 1 << 18 //clear SUM + csrc sstatus, x1 + li TRAP_OK, 1 + la TRAP_RET, test21_pass + li x1, 0x90011648 + sw x1, 0(x1) + j fail + +test21_pass: + + + + + +test50: //User mode setup + li TEST_ID, 50 + li TRAP_OK, 0 + + //set SUM + li x1, 1 << 18 + csrs sstatus, x1 + + //remap code tlb into userspace + csrr x10, satp + csrw satp, x0 + la x1, MMU_TABLE_1 + 0x000*4 + li x2, 0x80000000 + srli x2, x2, 2 + ori x2, x2, 0x1F + sw x2, 0(x1) + csrw satp, x10 + + li x1, 1 << 8 + csrc sstatus, x1 //clear SPP + + la x1, test51 + csrw sepc, x1 + sfence.vma + sret + j fail + +test51: //user read/write + li TEST_ID, 51 + li x1, 0x90011008 + li x2, 0x5B5A5958 + lw x1, 0(x1) + bne x1, x2, fail + + li x1, 0xA000A324 + li x2, 0xAAEE0008 + sw x2, 0(x1) + lw x1, 0(x1) + bne x1, x2, fail + +test52: //user fetch + li TEST_ID, 52 + la x1, test53 + li x2, 0x90012010 + jr x2 + j fail + +test53: // user fetch page fault + li TEST_ID, 53 + li TRAP_OK, 1 + la TRAP_RET, test54 + li x1, 0x90014390 + jr x1 + j fail + +test54: //user load page fault + li TEST_ID, 54 + li TRAP_OK, 1 + la TRAP_RET, test55 + li x1, 0x90014394 + lw x1, 0(x1) + j fail + +test55: //user store page fault + li TEST_ID, 55 + li TRAP_OK, 1 + la TRAP_RET, test56 + li x1, 0x90014398 + sw x1, 0(x1) + j fail + +test56: + + + + + + + + j pass + +fail: //TEST_ID => error code + li TRAP_OK, 0 + ecall +failFence: + li x2, 0xF00FFF24 + sw TEST_ID, 0(x2) + +pass: + li TRAP_OK, 2 + ecall +passFence: + li x2, 0xF00FFF20 + sw x0, 0(x2) + + +trap: + beq TRAP_OK, x0, failFence + csrr x1, mcause + csrr x1, mepc + csrr x1, mstatus + csrr x1, mbadaddr + li x1, 2 + beq TRAP_OK, x1, passFence + csrw mepc, TRAP_RET + mret + + + nop + nop + nop + nop + nop + nop + +.align 12 +MMU_TABLE_0: +.word 0 + +.align 12 +MMU_TABLE_1: +.word 0 + +.align 12 +MMU_TABLE_2: +.word 0 + +.align 12 +MMU_TABLE_3: +.word 0 + +.align 12 +ROM_0: +.word 0x03020100 +.word 0x07060504 +.word 0x0B0A0908 +.word 0x0F0E0D0C + +.align 12 +ROM_1: +.word 0x13121110 +.word 0x17161514 +.word 0x1B1A1918 +.word 0x1F1E1D1C + +.align 12 +ROM_2: +.word 0x23222120 +.word 0x27262524 +.word 0x2B2A2928 +.word 0x2F2E2D2C + +.align 12 +ROM_3: +.word 0x33323130 +.word 0x37363534 +.word 0x3B3A3938 +.word 0x3F3E3D3C + +.align 12 +ROM_4: +.word 0x43424140 +.word 0x47464544 +.word 0x4B4A4948 +.word 0x4F4E4D4C + +.align 12 +ROM_5: +.word 0x53525150 +.word 0x57565554 +.word 0x5B5A5958 +.word 0x5F5E5D5C + jr x1 + +.align 12 +ROM_6: +.word 0x63626160 +.word 0x67666564 +.word 0x6B6A6968 +.word 0x6F6E6D6C + +.align 12 +ROM_7: +.word 0x73727170 +.word 0x77767574 +.word 0x7B7A7978 +.word 0x7F7E7D7C + +/* +.align 22 +ROM_SUPER_0: +.word 0x83828180 +.word 0x87868584 +.word 0x8B8A8988 +.word 0x8F8E8D8C + +.align 12 +ROM_SUPER_1: +.word 0x93929190 +.word 0x97969594 +.word 0x9B9A9998 +.word 0x9F9E9D9C*/ + + diff --git a/VexRiscv/src/test/cpp/raw/mmu/src/ld b/VexRiscv/src/test/cpp/raw/mmu/src/ld new file mode 100644 index 0000000..93d8de8 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/mmu/src/ld @@ -0,0 +1,16 @@ +OUTPUT_ARCH( "riscv" ) + +MEMORY { + onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 128K +} + +SECTIONS +{ + + .crt_section : + { + . = ALIGN(4); + *crt.o(.text) + } > onChipRam + +} diff --git a/VexRiscv/src/test/cpp/raw/pmp/build/pmp.asm b/VexRiscv/src/test/cpp/raw/pmp/build/pmp.asm new file mode 100644 index 0000000..f8a30e2 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/pmp/build/pmp.asm @@ -0,0 +1,258 @@ + +build/pmp.elf: file format elf32-littleriscv + + +Disassembly of section .crt_section: + +80000000 <_start>: +80000000: 00000493 li s1,0 +80000004: 00000097 auipc ra,0x0 +80000008: 01008093 addi ra,ra,16 # 80000014 <trap> +8000000c: 30509073 csrw mtvec,ra +80000010: 0140006f j 80000024 <test0> + +80000014 <trap>: +80000014: 341f1073 csrw mepc,t5 +80000018: 00049463 bnez s1,80000020 <trap_exit> +8000001c: 30200073 mret + +80000020 <trap_exit>: +80000020: 000f0067 jr t5 + +80000024 <test0>: +80000024: 00000e13 li t3,0 +80000028: 00000f17 auipc t5,0x0 +8000002c: 324f0f13 addi t5,t5,804 # 8000034c <fail> +80000030: 800000b7 lui ra,0x80000 +80000034: 80008237 lui tp,0x80008 +80000038: deadc137 lui sp,0xdeadc +8000003c: eef10113 addi sp,sp,-273 # deadbeef <pass+0x5eadbb97> +80000040: 0020a023 sw sp,0(ra) # 80000000 <pass+0xfffffca8> +80000044: 00222023 sw sp,0(tp) # 80008000 <pass+0x7ca8> +80000048: 0000a183 lw gp,0(ra) +8000004c: 30311063 bne sp,gp,8000034c <fail> +80000050: 00022183 lw gp,0(tp) # 0 <_start-0x80000000> +80000054: 2e311c63 bne sp,gp,8000034c <fail> +80000058: 071a02b7 lui t0,0x71a0 +8000005c: 3a029073 csrw pmpcfg0,t0 +80000060: 3a002373 csrr t1,pmpcfg0 +80000064: 2e629463 bne t0,t1,8000034c <fail> +80000068: 1a1902b7 lui t0,0x1a190 +8000006c: 30428293 addi t0,t0,772 # 1a190304 <_start-0x65e6fcfc> +80000070: 3a129073 csrw pmpcfg1,t0 +80000074: 000f12b7 lui t0,0xf1 +80000078: 90a28293 addi t0,t0,-1782 # f090a <_start-0x7ff0f6f6> +8000007c: 3a229073 csrw pmpcfg2,t0 +80000080: 3a202373 csrr t1,pmpcfg2 +80000084: 2c629463 bne t0,t1,8000034c <fail> +80000088: 1c1e22b7 lui t0,0x1c1e2 +8000008c: 90028293 addi t0,t0,-1792 # 1c1e1900 <_start-0x63e1e700> +80000090: 3a329073 csrw pmpcfg3,t0 +80000094: 200002b7 lui t0,0x20000 +80000098: 3b029073 csrw pmpaddr0,t0 +8000009c: 3b002373 csrr t1,pmpaddr0 +800000a0: 2a629663 bne t0,t1,8000034c <fail> +800000a4: fff00293 li t0,-1 +800000a8: 3b129073 csrw pmpaddr1,t0 +800000ac: 202002b7 lui t0,0x20200 +800000b0: 3b229073 csrw pmpaddr2,t0 +800000b4: 200042b7 lui t0,0x20004 +800000b8: fff28293 addi t0,t0,-1 # 20003fff <_start-0x5fffc001> +800000bc: 3b329073 csrw pmpaddr3,t0 +800000c0: 200042b7 lui t0,0x20004 +800000c4: fff28293 addi t0,t0,-1 # 20003fff <_start-0x5fffc001> +800000c8: 3b429073 csrw pmpaddr4,t0 +800000cc: 200042b7 lui t0,0x20004 +800000d0: fff28293 addi t0,t0,-1 # 20003fff <_start-0x5fffc001> +800000d4: 3b529073 csrw pmpaddr5,t0 +800000d8: 230002b7 lui t0,0x23000 +800000dc: fff28293 addi t0,t0,-1 # 22ffffff <_start-0x5d000001> +800000e0: 3b629073 csrw pmpaddr6,t0 +800000e4: 220402b7 lui t0,0x22040 +800000e8: fff28293 addi t0,t0,-1 # 2203ffff <_start-0x5dfc0001> +800000ec: 3b729073 csrw pmpaddr7,t0 +800000f0: 200d02b7 lui t0,0x200d0 +800000f4: 3b829073 csrw pmpaddr8,t0 +800000f8: 200e02b7 lui t0,0x200e0 +800000fc: 3b929073 csrw pmpaddr9,t0 +80000100: fff00293 li t0,-1 +80000104: 3ba29073 csrw pmpaddr10,t0 +80000108: 00000293 li t0,0 +8000010c: 3bb29073 csrw pmpaddr11,t0 +80000110: 00000293 li t0,0 +80000114: 3bc29073 csrw pmpaddr12,t0 +80000118: 00000293 li t0,0 +8000011c: 3bd29073 csrw pmpaddr13,t0 +80000120: 00000293 li t0,0 +80000124: 3be29073 csrw pmpaddr14,t0 +80000128: fff00293 li t0,-1 +8000012c: 3bf29073 csrw pmpaddr15,t0 +80000130: 00c10137 lui sp,0xc10 +80000134: fee10113 addi sp,sp,-18 # c0ffee <_start-0x7f3f0012> +80000138: 0020a023 sw sp,0(ra) +8000013c: 00222023 sw sp,0(tp) # 0 <_start-0x80000000> +80000140: 0000a183 lw gp,0(ra) +80000144: 20311463 bne sp,gp,8000034c <fail> +80000148: 00000193 li gp,0 +8000014c: 00022183 lw gp,0(tp) # 0 <_start-0x80000000> +80000150: 1e311e63 bne sp,gp,8000034c <fail> + +80000154 <test1>: +80000154: 00100e13 li t3,1 +80000158: 00000f17 auipc t5,0x0 +8000015c: 1f4f0f13 addi t5,t5,500 # 8000034c <fail> +80000160: 079a12b7 lui t0,0x79a1 +80000164: 80828293 addi t0,t0,-2040 # 79a0808 <_start-0x7865f7f8> +80000168: 3a029073 csrw pmpcfg0,t0 +8000016c: 3a002373 csrr t1,pmpcfg0 +80000170: 1c629e63 bne t0,t1,8000034c <fail> +80000174: 808000b7 lui ra,0x80800 +80000178: deadc137 lui sp,0xdeadc +8000017c: eef10113 addi sp,sp,-273 # deadbeef <pass+0x5eadbb97> +80000180: 0020a023 sw sp,0(ra) # 80800000 <pass+0x7ffca8> +80000184: 00000f17 auipc t5,0x0 +80000188: 010f0f13 addi t5,t5,16 # 80000194 <test2> +8000018c: 0000a183 lw gp,0(ra) +80000190: 1bc0006f j 8000034c <fail> + +80000194 <test2>: +80000194: 00200e13 li t3,2 +80000198: 00000f17 auipc t5,0x0 +8000019c: 1b4f0f13 addi t5,t5,436 # 8000034c <fail> +800001a0: 071a02b7 lui t0,0x71a0 +800001a4: 3a029073 csrw pmpcfg0,t0 +800001a8: 3a002373 csrr t1,pmpcfg0 +800001ac: 1a628063 beq t0,t1,8000034c <fail> +800001b0: 3b305073 csrwi pmpaddr3,0 +800001b4: 3b302373 csrr t1,pmpaddr3 +800001b8: 18031a63 bnez t1,8000034c <fail> +800001bc: 3b205073 csrwi pmpaddr2,0 +800001c0: 3b202373 csrr t1,pmpaddr2 +800001c4: 18030463 beqz t1,8000034c <fail> +800001c8: 808000b7 lui ra,0x80800 +800001cc: deadc137 lui sp,0xdeadc +800001d0: eef10113 addi sp,sp,-273 # deadbeef <pass+0x5eadbb97> +800001d4: 0020a023 sw sp,0(ra) # 80800000 <pass+0x7ffca8> +800001d8: 00000f17 auipc t5,0x0 +800001dc: 010f0f13 addi t5,t5,16 # 800001e8 <test3> +800001e0: 0000a183 lw gp,0(ra) +800001e4: 1680006f j 8000034c <fail> + +800001e8 <test3>: +800001e8: 00300e13 li t3,3 +800001ec: 00000f17 auipc t5,0x0 +800001f0: 160f0f13 addi t5,t5,352 # 8000034c <fail> +800001f4: 00ff02b7 lui t0,0xff0 +800001f8: 3b32a073 csrs pmpaddr3,t0 +800001fc: 3b302373 csrr t1,pmpaddr3 +80000200: 14629663 bne t0,t1,8000034c <fail> +80000204: 0ff00293 li t0,255 +80000208: 3b32a073 csrs pmpaddr3,t0 +8000020c: 3b302373 csrr t1,pmpaddr3 +80000210: 00ff02b7 lui t0,0xff0 +80000214: 0ff28293 addi t0,t0,255 # ff00ff <_start-0x7f00ff01> +80000218: 12629a63 bne t0,t1,8000034c <fail> +8000021c: 00ff02b7 lui t0,0xff0 +80000220: 3b32b073 csrc pmpaddr3,t0 +80000224: 3b302373 csrr t1,pmpaddr3 +80000228: 0ff00293 li t0,255 +8000022c: 12629063 bne t0,t1,8000034c <fail> +80000230: 00ff02b7 lui t0,0xff0 +80000234: 0ff28293 addi t0,t0,255 # ff00ff <_start-0x7f00ff01> +80000238: 3a02b073 csrc pmpcfg0,t0 +8000023c: 3a002373 csrr t1,pmpcfg0 +80000240: 079a02b7 lui t0,0x79a0 +80000244: 10629463 bne t0,t1,8000034c <fail> +80000248: 00ff02b7 lui t0,0xff0 +8000024c: 70728293 addi t0,t0,1799 # ff0707 <_start-0x7f00f8f9> +80000250: 3a02a073 csrs pmpcfg0,t0 +80000254: 3a002373 csrr t1,pmpcfg0 +80000258: 079a02b7 lui t0,0x79a0 +8000025c: 70728293 addi t0,t0,1799 # 79a0707 <_start-0x7865f8f9> +80000260: 0e629663 bne t0,t1,8000034c <fail> + +80000264 <test4>: +80000264: 00400e13 li t3,4 +80000268: 00000f17 auipc t5,0x0 +8000026c: 0e4f0f13 addi t5,t5,228 # 8000034c <fail> +80000270: 00000117 auipc sp,0x0 +80000274: 01010113 addi sp,sp,16 # 80000280 <test5> +80000278: 34111073 csrw mepc,sp +8000027c: 30200073 mret + +80000280 <test5>: +80000280: 00500e13 li t3,5 +80000284: 00000f17 auipc t5,0x0 +80000288: 0c8f0f13 addi t5,t5,200 # 8000034c <fail> +8000028c: deadc137 lui sp,0xdeadc +80000290: eef10113 addi sp,sp,-273 # deadbeef <pass+0x5eadbb97> +80000294: 808000b7 lui ra,0x80800 +80000298: 0020a023 sw sp,0(ra) # 80800000 <pass+0x7ffca8> +8000029c: 00000f17 auipc t5,0x0 +800002a0: 010f0f13 addi t5,t5,16 # 800002ac <test6> +800002a4: 0000a183 lw gp,0(ra) +800002a8: 0a40006f j 8000034c <fail> + +800002ac <test6>: +800002ac: 00600e13 li t3,6 + +800002b0 <test7>: +800002b0: 00700e13 li t3,7 +800002b4: 00000f17 auipc t5,0x0 +800002b8: 098f0f13 addi t5,t5,152 # 8000034c <fail> +800002bc: 890000b7 lui ra,0x89000 +800002c0: ff008093 addi ra,ra,-16 # 88fffff0 <pass+0x8fffc98> +800002c4: 0000a183 lw gp,0(ra) +800002c8: 00000f17 auipc t5,0x0 +800002cc: 010f0f13 addi t5,t5,16 # 800002d8 <test8a> +800002d0: 0030a023 sw gp,0(ra) +800002d4: 0780006f j 8000034c <fail> + +800002d8 <test8a>: +800002d8: 00800e13 li t3,8 +800002dc: 00000f17 auipc t5,0x0 +800002e0: 014f0f13 addi t5,t5,20 # 800002f0 <test8b> +800002e4: 00100493 li s1,1 +800002e8: 3a305073 csrwi pmpcfg3,0 +800002ec: 0600006f j 8000034c <fail> + +800002f0 <test8b>: +800002f0: 00800e13 li t3,8 +800002f4: 1c1e22b7 lui t0,0x1c1e2 +800002f8: 90028293 addi t0,t0,-1792 # 1c1e1900 <_start-0x63e1e700> +800002fc: 3a302373 csrr t1,pmpcfg3 +80000300: 04629663 bne t0,t1,8000034c <fail> + +80000304 <test9a>: +80000304: 00900e13 li t3,9 +80000308: 00000f17 auipc t5,0x0 +8000030c: 044f0f13 addi t5,t5,68 # 8000034c <fail> +80000310: 00000493 li s1,0 +80000314: 00000117 auipc sp,0x0 +80000318: 01010113 addi sp,sp,16 # 80000324 <test9b> +8000031c: 34111073 csrw mepc,sp +80000320: 30200073 mret + +80000324 <test9b>: +80000324: 00900e13 li t3,9 +80000328: 00000f17 auipc t5,0x0 +8000032c: 014f0f13 addi t5,t5,20 # 8000033c <test9c> +80000330: 00100493 li s1,1 +80000334: 3ba05073 csrwi pmpaddr10,0 +80000338: 0140006f j 8000034c <fail> + +8000033c <test9c>: +8000033c: 00900e13 li t3,9 +80000340: fff00293 li t0,-1 +80000344: 3ba02373 csrr t1,pmpaddr10 +80000348: 00628863 beq t0,t1,80000358 <pass> + +8000034c <fail>: +8000034c: f0100137 lui sp,0xf0100 +80000350: f2410113 addi sp,sp,-220 # f00fff24 <pass+0x700ffbcc> +80000354: 01c12023 sw t3,0(sp) + +80000358 <pass>: +80000358: f0100137 lui sp,0xf0100 +8000035c: f2010113 addi sp,sp,-224 # f00fff20 <pass+0x700ffbc8> +80000360: 00012023 sw zero,0(sp) diff --git a/VexRiscv/src/test/cpp/raw/pmp/build/pmp.elf b/VexRiscv/src/test/cpp/raw/pmp/build/pmp.elf Binary files differnew file mode 100755 index 0000000..f6c3c69 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/pmp/build/pmp.elf diff --git a/VexRiscv/src/test/cpp/raw/pmp/build/pmp.hex b/VexRiscv/src/test/cpp/raw/pmp/build/pmp.hex new file mode 100644 index 0000000..509c291 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/pmp/build/pmp.hex @@ -0,0 +1,58 @@ +:0200000480007A
+:10000000930400009700000093800001739050302B
+:100010006F00400173101F3463940400730020309C
+:1000200067000F00130E0000170F0000130F4F3270
+:10003000B70000803782008037C1ADDE1301F1EEDA
+:1000400023A020002320220083A100006310313070
+:1000500083210200631C312EB7021A077390023A03
+:100060007323003A6394622EB702191A93824230C6
+:100070007390123AB7120F009382A2907390223AB3
+:100080007323203A6394622CB7221E1C9382029041
+:100090007390323AB70200207390023B7323003B07
+:1000A0006396622A9302F0FF7390123BB7022020FE
+:1000B0007390223BB74200209382F2FF7390323B51
+:1000C000B74200209382F2FF7390423BB742002078
+:1000D0009382F2FF7390523BB70200239382F2FFA8
+:1000E0007390623BB70204229382F2FF7390723BDB
+:1000F000B7020D207390823BB7020E207390923BA3
+:100100009302F0FF7390A23B930200007390B23B06
+:10011000930200007390C23B930200007390D23BA5
+:10012000930200007390E23B9302F0FF7390F23B66
+:100130003701C1001301E1FE23A02000232022008B
+:1001400083A1000063143120930100008321020089
+:10015000631E311E130E1000170F0000130F4F1FE8
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+:100190006F00C01B130E2000170F0000130F4F1B22
+:1001A000B7021A077390023A7323003A6380621A07
+:1001B0007350303B7323303B631A03187350203B5A
+:1001C0007323203B63040318B700808037C1ADDE82
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+:10020000639662149302F00F73A0323B7323303B6A
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+:1002200073B0323B7323303B9302F00F6390621242
+:10023000B702FF009382F20F73B0023A7323003AC1
+:10024000B7029A0763946210B702FF00938272703C
+:1002500073A0023A7323003AB7029A07938272702E
+:100260006396620E130E4000170F0000130F4F0E1F
+:1002700017010000130101017310113473002030C5
+:10028000130E5000170F0000130F8F0C37C1ADDE97
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+:1002B000130E7000170F0000130F8F09B70000898D
+:1002C000938000FF83A10000170F0000130F0F01A0
+:1002D00023A030006F008007130E8000170F00006E
+:1002E000130F4F01930410007350303A6F00000653
+:1002F000130E8000B7221E1C938202907323303AA3
+:1003000063966204130E9000170F0000130F4F0442
+:100310009304000017010000130101017310113450
+:1003200073002030130E9000170F0000130F4F01C1
+:10033000930410007350A03B6F004001130E900017
+:100340009302F0FF7323A03B63886200370110F033
+:10035000130141F22320C101370110F0130101F212
+:040360002320010055
+:040000058000000077
+:00000001FF
diff --git a/VexRiscv/src/test/cpp/raw/pmp/build/pmp.map b/VexRiscv/src/test/cpp/raw/pmp/build/pmp.map new file mode 100644 index 0000000..ab2c78d --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/pmp/build/pmp.map @@ -0,0 +1,35 @@ + +Memory Configuration + +Name Origin Length Attributes +onChipRam 0x0000000080000000 0x0000000000020000 w !xr +*default* 0x0000000000000000 0xffffffffffffffff + +Linker script and memory map + +LOAD build/src/crt.o +LOAD /opt/riscv_10092021/bin/../lib/gcc/riscv64-unknown-elf/8.3.0/rv32i/ilp32/libgcc.a +START GROUP +LOAD /opt/riscv_10092021/bin/../lib/gcc/riscv64-unknown-elf/8.3.0/../../../../riscv64-unknown-elf/lib/rv32i/ilp32/libc.a +LOAD /opt/riscv_10092021/bin/../lib/gcc/riscv64-unknown-elf/8.3.0/../../../../riscv64-unknown-elf/lib/rv32i/ilp32/libgloss.a +END GROUP +LOAD /opt/riscv_10092021/bin/../lib/gcc/riscv64-unknown-elf/8.3.0/rv32i/ilp32/libgcc.a + +.crt_section 0x0000000080000000 0x364 + 0x0000000080000000 . = ALIGN (0x4) + *crt.o(.text) + .text 0x0000000080000000 0x364 build/src/crt.o + 0x0000000080000000 _start + 0x0000000080000014 trap +OUTPUT(build/pmp.elf elf32-littleriscv) + +.data 0x0000000080000364 0x0 + .data 0x0000000080000364 0x0 build/src/crt.o + +.bss 0x0000000080000364 0x0 + .bss 0x0000000080000364 0x0 build/src/crt.o + +.riscv.attributes + 0x0000000000000000 0x1a + .riscv.attributes + 0x0000000000000000 0x1a build/src/crt.o diff --git a/VexRiscv/src/test/cpp/raw/pmp/makefile b/VexRiscv/src/test/cpp/raw/pmp/makefile new file mode 100644 index 0000000..0069df4 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/pmp/makefile @@ -0,0 +1,3 @@ +PROJ_NAME=pmp + +include ../common/asm.mk diff --git a/VexRiscv/src/test/cpp/raw/pmp/src/crt.S b/VexRiscv/src/test/cpp/raw/pmp/src/crt.S new file mode 100644 index 0000000..ce10ad7 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/pmp/src/crt.S @@ -0,0 +1,269 @@ +/* + * Copyright (c) 2020 Samuel Lindemer <samuel.lindemer@ri.se> + * + * SPDX-License-Identifier: MIT + */ + +#define TEST_ID x28 +#define TRAP_RETURN x30 +#define TRAP_EXIT x9 + +#define PMPCFG0 0x071a0000 +#define PMPCFG0_ 0x079a0808 +#define PMPCFG1 0x1a190304 +#define PMPCFG2 0x000f090a +#define PMPCFG3 0x1c1e1900 + +#define PMPADDR0 0x20000000 // OFF (test0) -> TOR (test1) -> OFF (test2) +#define PMPADDR1 0xffffffff // OFF (test0) -> TOR (test1) -> OFF (test2) +#define PMPADDR2 0x20200000 // NAPOT W +#define PMPADDR3 0x20003fff // OFF RWX -> 0x00000000 OFF RWX (test2) +#define PMPADDR4 0x20003fff // OFF X +#define PMPADDR5 0x20003fff // OFF RW +#define PMPADDR6 0x22ffffff // NAPOT R +#define PMPADDR7 0x2203ffff // NAPOT W +#define PMPADDR8 0x200d0000 // TOR W +#define PMPADDR9 0x200e0000 // TOR R +#define PMPADDR10 0xffffffff // TOR RWX +#define PMPADDR11 0x00000000 // OFF +#define PMPADDR12 0x00000000 // OFF +#define PMPADDR13 0x00000000 // NAPOT R +#define PMPADDR14 0x00000000 // NAPOT WX +#define PMPADDR15 0xffffffff // NAPOT X + +.global _start +_start: + li TRAP_EXIT, 0x0 + la x1, trap + csrw mtvec, x1 + j test0 + +.global trap +trap: + csrw mepc, TRAP_RETURN + bnez TRAP_EXIT, trap_exit + mret + +// return from trap, but stay in M-mode +trap_exit: + jr TRAP_RETURN + +// configure PMP, attempt read/write from machine mode +test0: + li TEST_ID, 0 + la TRAP_RETURN, fail + + li x1, 0x80000000 + li x4, 0x80008000 + li x2, 0xdeadbeef + sw x2, 0x0(x1) + sw x2, 0x0(x4) + lw x3, 0x0(x1) + bne x2, x3, fail + lw x3, 0x0(x4) + bne x2, x3, fail + + li x5, PMPCFG0 + csrw pmpcfg0, x5 + csrr x6, pmpcfg0 + bne x5, x6, fail + li x5, PMPCFG1 + csrw pmpcfg1, x5 + li x5, PMPCFG2 + csrw pmpcfg2, x5 + csrr x6, pmpcfg2 + bne x5, x6, fail + li x5, PMPCFG3 + csrw pmpcfg3, x5 + li x5, PMPADDR0 + csrw pmpaddr0, x5 + csrr x6, pmpaddr0 + bne x5, x6, fail + li x5, PMPADDR1 + csrw pmpaddr1, x5 + li x5, PMPADDR2 + csrw pmpaddr2, x5 + li x5, PMPADDR3 + csrw pmpaddr3, x5 + li x5, PMPADDR4 + csrw pmpaddr4, x5 + li x5, PMPADDR5 + csrw pmpaddr5, x5 + li x5, PMPADDR6 + csrw pmpaddr6, x5 + li x5, PMPADDR7 + csrw pmpaddr7, x5 + li x5, PMPADDR8 + csrw pmpaddr8, x5 + li x5, PMPADDR9 + csrw pmpaddr9, x5 + li x5, PMPADDR10 + csrw pmpaddr10, x5 + li x5, PMPADDR11 + csrw pmpaddr11, x5 + li x5, PMPADDR12 + csrw pmpaddr12, x5 + li x5, PMPADDR13 + csrw pmpaddr13, x5 + li x5, PMPADDR14 + csrw pmpaddr14, x5 + li x5, PMPADDR15 + csrw pmpaddr15, x5 + + li x2, 0xc0ffee + sw x2, 0x0(x1) + sw x2, 0x0(x4) + lw x3, 0x0(x1) + bne x2, x3, fail + li x3, 0x0 + lw x3, 0x0(x4) + bne x2, x3, fail + +// lock region 2, attempt read/write from machine mode +test1: + li TEST_ID, 1 + la TRAP_RETURN, fail + li x5, PMPCFG0_ + csrw pmpcfg0, x5 // lock region 2 + csrr x6, pmpcfg0 + bne x5, x6, fail + li x1, 0x80800000 + li x2, 0xdeadbeef + sw x2, 0x0(x1) // should be OK (write region 2) + la TRAP_RETURN, test2 + lw x3, 0x0(x1) // should fault (read region 2) + j fail + +// "unlock" region 2, attempt read/write from machine mode +test2: + li TEST_ID, 2 + la TRAP_RETURN, fail + li x5, PMPCFG0 + csrw pmpcfg0, x5 // "unlock" region 2 + csrr x6, pmpcfg0 + beq x5, x6, fail + csrwi pmpaddr3, 0x0 + csrr x6, pmpaddr3 + bnez x6, fail + csrwi pmpaddr2, 0x0 + csrr x6, pmpaddr2 + beqz x6, fail + li x1, 0x80800000 + li x2, 0xdeadbeef + sw x2, 0x0(x1) // should still be OK (write region 2) + la TRAP_RETURN, test3 + lw x3, 0x0(x1) // should still fault (read region 2) + j fail + +// verify masked CSR read/write operations +test3: + li TEST_ID, 3 + la TRAP_RETURN, fail + li x5, 0x00ff0000 + csrs pmpaddr3, x5 + csrr x6, pmpaddr3 + bne x5, x6, fail + li x5, 0x000000ff + csrs pmpaddr3, x5 + csrr x6, pmpaddr3 + li x5, 0x00ff00ff + bne x5, x6, fail + li x5, 0x00ff0000 + csrc pmpaddr3, x5 + csrr x6, pmpaddr3 + li x5, 0x000000ff + bne x5, x6, fail + li x5, 0x00ff00ff + csrc pmpcfg0, x5 + csrr x6, pmpcfg0 + li x5, 0x079a0000 + bne x5, x6, fail + li x5, 0x00ff0707 + csrs pmpcfg0, x5 + csrr x6, pmpcfg0 + li x5, 0x079a0707 + bne x5, x6, fail + +// jump into U-mode +test4: + li TEST_ID, 4 + la TRAP_RETURN, fail + la x2, test5 + csrw mepc, x2 + mret + +// attempt to read/write the locked region from U-mode +test5: + li TEST_ID, 5 + la TRAP_RETURN, fail + li x2, 0xdeadbeef + li x1, 0x80800000 + sw x2, 0x0(x1) // should be OK (write region 2) + la TRAP_RETURN, test6 + lw x3, 0x0(x1) // should fault (read region 2) + j fail + +// attempt to read/write overlapping regions from U-mode +test6: + li TEST_ID, 6 + //la TRAP_RETURN, fail + //li x2, 0xdeadbeef + //li x1, 0x88000000 + //sw x2, 0x0(x1) // should be OK (write region 6/7) + //lw x3, 0x0(x1) // should be OK (write region 6/7) + +test7: + li TEST_ID, 7 + la TRAP_RETURN, fail + li x1, 0x88fffff0 + lw x3, 0x0(x1) // should be OK (read region 6) + la TRAP_RETURN, test8a + sw x3, 0x0(x1) // should fault (write region 6) + j fail + +// attempt to write a pmpcfg# register from U-mode +test8a: + li TEST_ID, 8 + la TRAP_RETURN, test8b + li TRAP_EXIT, 0x1 + csrwi pmpcfg3, 0x0 + j fail + +// check the result from M-mode +test8b: + li TEST_ID, 8 + li x5, PMPCFG3 + csrr x6, pmpcfg3 + bne x5, x6, fail + +// jump back into U-mode +test9a: + li TEST_ID, 9 + la TRAP_RETURN, fail + li TRAP_EXIT, 0x0 + la x2, test9b + csrw mepc, x2 + mret + +// attempt to write a pmpaddr# register from U-mode +test9b: + li TEST_ID, 9 + la TRAP_RETURN, test9c + li TRAP_EXIT, 0x1 + csrwi pmpaddr10, 0x0 + j fail + +// check the result from M-mode +test9c: + li TEST_ID, 9 + li x5, PMPADDR10 + csrr x6, pmpaddr10 + beq x5, x6, pass + +fail: + li x2, 0xf00fff24 + sw TEST_ID, 0(x2) + +pass: + li x2, 0xf00fff20 + sw x0, 0(x2)
\ No newline at end of file diff --git a/VexRiscv/src/test/cpp/raw/pmp/src/ld b/VexRiscv/src/test/cpp/raw/pmp/src/ld new file mode 100644 index 0000000..93d8de8 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/pmp/src/ld @@ -0,0 +1,16 @@ +OUTPUT_ARCH( "riscv" ) + +MEMORY { + onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 128K +} + +SECTIONS +{ + + .crt_section : + { + . = ALIGN(4); + *crt.o(.text) + } > onChipRam + +} diff --git a/VexRiscv/src/test/cpp/raw/smp/.gitignore b/VexRiscv/src/test/cpp/raw/smp/.gitignore new file mode 100644 index 0000000..a7caa3b --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/smp/.gitignore @@ -0,0 +1,6 @@ +*.map +*.v +*.elf +*.o +*.hex +!*.bin
\ No newline at end of file diff --git a/VexRiscv/src/test/cpp/raw/smp/build/smp.asm b/VexRiscv/src/test/cpp/raw/smp/build/smp.asm new file mode 100644 index 0000000..b0492f9 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/smp/build/smp.asm @@ -0,0 +1,441 @@ + +build/smp.elf: file format elf32-littleriscv + + +Disassembly of section .crt_section: + +80000000 <_start>: +80000000: f1402473 csrr s0,mhartid +80000004: f80002b7 lui t0,0xf8000 +80000008: f1402373 csrr t1,mhartid +8000000c: 01031313 slli t1,t1,0x10 +80000010: 006282b3 add t0,t0,t1 +80000014: 0082a023 sw s0,0(t0) # f8000000 <consistancy_done_call+0x77fffab8> + +80000018 <count_thread_start>: +80000018: 00100513 li a0,1 +8000001c: 00000597 auipc a1,0x0 +80000020: 42058593 addi a1,a1,1056 # 8000043c <thread_count> +80000024: 00a5a02f amoadd.w zero,a0,(a1) + +80000028 <count_thread_wait>: +80000028: 00000417 auipc s0,0x0 +8000002c: 41442403 lw s0,1044(s0) # 8000043c <thread_count> +80000030: 19000513 li a0,400 +80000034: 3fc000ef jal ra,80000430 <sleep> +80000038: 00000497 auipc s1,0x0 +8000003c: 4044a483 lw s1,1028(s1) # 8000043c <thread_count> +80000040: fe8494e3 bne s1,s0,80000028 <count_thread_wait> +80000044: f80002b7 lui t0,0xf8000 +80000048: 00428293 addi t0,t0,4 # f8000004 <consistancy_done_call+0x77fffabc> +8000004c: f1402373 csrr t1,mhartid +80000050: 01031313 slli t1,t1,0x10 +80000054: 006282b3 add t0,t0,t1 +80000058: 0092a023 sw s1,0(t0) + +8000005c <barrier_amo_test>: +8000005c: 00100513 li a0,1 +80000060: 290000ef jal ra,800002f0 <barrier_amo> +80000064: 00200513 li a0,2 +80000068: 288000ef jal ra,800002f0 <barrier_amo> +8000006c: 00300513 li a0,3 +80000070: 280000ef jal ra,800002f0 <barrier_amo> +80000074: 00400513 li a0,4 +80000078: 2f4000ef jal ra,8000036c <barrier_lrsc> +8000007c: 00500513 li a0,5 +80000080: 2ec000ef jal ra,8000036c <barrier_lrsc> +80000084: 00600513 li a0,6 +80000088: 2e4000ef jal ra,8000036c <barrier_lrsc> +8000008c: 00700513 li a0,7 +80000090: 260000ef jal ra,800002f0 <barrier_amo> +80000094: 00800513 li a0,8 +80000098: 2d4000ef jal ra,8000036c <barrier_lrsc> +8000009c: 00000197 auipc gp,0x0 +800000a0: 3ac1a183 lw gp,940(gp) # 80000448 <barrier_allocator> + +800000a4 <consistancy_test1>: +800000a4: 00000297 auipc t0,0x0 +800000a8: 06828293 addi t0,t0,104 # 8000010c <consistancy_init_load> +800000ac: 00000317 auipc t1,0x0 +800000b0: 48532a23 sw t0,1172(t1) # 80000540 <consistancy_init_call> +800000b4: 00000297 auipc t0,0x0 +800000b8: 06028293 addi t0,t0,96 # 80000114 <consistancy_do_simple_fence> +800000bc: 00000317 auipc t1,0x0 +800000c0: 48532423 sw t0,1160(t1) # 80000544 <consistancy_do_call> +800000c4: 00000297 auipc t0,0x0 +800000c8: 01428293 addi t0,t0,20 # 800000d8 <consistancy_test2> +800000cc: 00000317 auipc t1,0x0 +800000d0: 46532e23 sw t0,1148(t1) # 80000548 <consistancy_done_call> +800000d4: 0640006f j 80000138 <consistancy_start> + +800000d8 <consistancy_test2>: +800000d8: 00000297 auipc t0,0x0 +800000dc: 03428293 addi t0,t0,52 # 8000010c <consistancy_init_load> +800000e0: 00000317 auipc t1,0x0 +800000e4: 46532023 sw t0,1120(t1) # 80000540 <consistancy_init_call> +800000e8: 00000297 auipc t0,0x0 +800000ec: 04028293 addi t0,t0,64 # 80000128 <consistancy_do_rl_fence> +800000f0: 00000317 auipc t1,0x0 +800000f4: 44532a23 sw t0,1108(t1) # 80000544 <consistancy_do_call> +800000f8: 00000297 auipc t0,0x0 +800000fc: 2f428293 addi t0,t0,756 # 800003ec <success> +80000100: 00000317 auipc t1,0x0 +80000104: 44532423 sw t0,1096(t1) # 80000548 <consistancy_done_call> +80000108: 0300006f j 80000138 <consistancy_start> + +8000010c <consistancy_init_load>: +8000010c: 0004a983 lw s3,0(s1) +80000110: 0c40006f j 800001d4 <consistancy_do_init_done> + +80000114 <consistancy_do_simple_fence>: +80000114: 01242023 sw s2,0(s0) +80000118: 0120000f fence w,r +8000011c: 0004a983 lw s3,0(s1) +80000120: 05342023 sw s3,64(s0) +80000124: 0cc0006f j 800001f0 <consistancy_join> + +80000128 <consistancy_do_rl_fence>: +80000128: 01242023 sw s2,0(s0) +8000012c: 1204a9af lr.w.rl s3,(s1) +80000130: 05342023 sw s3,64(s0) +80000134: 0bc0006f j 800001f0 <consistancy_join> + +80000138 <consistancy_start>: +80000138: 00018513 mv a0,gp +8000013c: 00118193 addi gp,gp,1 +80000140: 22c000ef jal ra,8000036c <barrier_lrsc> +80000144: 00000297 auipc t0,0x0 +80000148: 3002a823 sw zero,784(t0) # 80000454 <consistancy_all_tested> + +8000014c <consistancy_loop>: +8000014c: 00018513 mv a0,gp +80000150: 00118193 addi gp,gp,1 +80000154: 218000ef jal ra,8000036c <barrier_lrsc> +80000158: 00000297 auipc t0,0x0 +8000015c: 2fc2a283 lw t0,764(t0) # 80000454 <consistancy_all_tested> +80000160: 03200313 li t1,50 +80000164: 1662da63 bge t0,t1,800002d8 <consistancy_passed> +80000168: 00000297 auipc t0,0x0 +8000016c: 2e42a283 lw t0,740(t0) # 8000044c <consistancy_a_hart> +80000170: 00000317 auipc t1,0x0 +80000174: 2e032303 lw t1,736(t1) # 80000450 <consistancy_b_hart> +80000178: 06628c63 beq t0,t1,800001f0 <consistancy_join> +8000017c: f14022f3 csrr t0,mhartid +80000180: 00000317 auipc t1,0x0 +80000184: 2cc32303 lw t1,716(t1) # 8000044c <consistancy_a_hart> +80000188: 00000417 auipc s0,0x0 +8000018c: 33840413 addi s0,s0,824 # 800004c0 <consistancy_a_value> +80000190: 00000497 auipc s1,0x0 +80000194: 33448493 addi s1,s1,820 # 800004c4 <consistancy_b_value> +80000198: 02628863 beq t0,t1,800001c8 <consistancy_do> +8000019c: 00000317 auipc t1,0x0 +800001a0: 2b432303 lw t1,692(t1) # 80000450 <consistancy_b_hart> +800001a4: 00000417 auipc s0,0x0 +800001a8: 32040413 addi s0,s0,800 # 800004c4 <consistancy_b_value> +800001ac: 00000497 auipc s1,0x0 +800001b0: 31448493 addi s1,s1,788 # 800004c0 <consistancy_a_value> +800001b4: 00628a63 beq t0,t1,800001c8 <consistancy_do> + +800001b8 <consistancy_hart_not_involved>: +800001b8: 00018513 mv a0,gp +800001bc: 00118193 addi gp,gp,1 +800001c0: 1ac000ef jal ra,8000036c <barrier_lrsc> +800001c4: 02c0006f j 800001f0 <consistancy_join> + +800001c8 <consistancy_do>: +800001c8: 00000297 auipc t0,0x0 +800001cc: 3782a283 lw t0,888(t0) # 80000540 <consistancy_init_call> +800001d0: 000280e7 jalr t0 + +800001d4 <consistancy_do_init_done>: +800001d4: 29a00913 li s2,666 +800001d8: 00018513 mv a0,gp +800001dc: 00118193 addi gp,gp,1 +800001e0: 18c000ef jal ra,8000036c <barrier_lrsc> +800001e4: 00000297 auipc t0,0x0 +800001e8: 3602a283 lw t0,864(t0) # 80000544 <consistancy_do_call> +800001ec: 000280e7 jalr t0 + +800001f0 <consistancy_join>: +800001f0: 0330000f fence rw,rw +800001f4: 00018513 mv a0,gp +800001f8: 00118193 addi gp,gp,1 +800001fc: 170000ef jal ra,8000036c <barrier_lrsc> +80000200: f14022f3 csrr t0,mhartid +80000204: f40294e3 bnez t0,8000014c <consistancy_loop> + +80000208 <consistancy_assert>: +80000208: 00000297 auipc t0,0x0 +8000020c: 2442a283 lw t0,580(t0) # 8000044c <consistancy_a_hart> +80000210: 00000317 auipc t1,0x0 +80000214: 24032303 lw t1,576(t1) # 80000450 <consistancy_b_hart> +80000218: 04628263 beq t0,t1,8000025c <consistancy_increment> +8000021c: 00000517 auipc a0,0x0 +80000220: 2e852503 lw a0,744(a0) # 80000504 <consistancy_a_readed> +80000224: f80002b7 lui t0,0xf8000 +80000228: 01428293 addi t0,t0,20 # f8000014 <consistancy_done_call+0x77fffacc> +8000022c: f1402373 csrr t1,mhartid +80000230: 01031313 slli t1,t1,0x10 +80000234: 006282b3 add t0,t0,t1 +80000238: 00a2a023 sw a0,0(t0) +8000023c: 00000517 auipc a0,0x0 +80000240: 2c452503 lw a0,708(a0) # 80000500 <consistancy_b_readed> +80000244: f80002b7 lui t0,0xf8000 +80000248: 01428293 addi t0,t0,20 # f8000014 <consistancy_done_call+0x77fffacc> +8000024c: f1402373 csrr t1,mhartid +80000250: 01031313 slli t1,t1,0x10 +80000254: 006282b3 add t0,t0,t1 +80000258: 00a2a023 sw a0,0(t0) + +8000025c <consistancy_increment>: +8000025c: f14022f3 csrr t0,mhartid +80000260: ee0296e3 bnez t0,8000014c <consistancy_loop> +80000264: 00000297 auipc t0,0x0 +80000268: 2402ae23 sw zero,604(t0) # 800004c0 <consistancy_a_value> +8000026c: 00000297 auipc t0,0x0 +80000270: 2402ac23 sw zero,600(t0) # 800004c4 <consistancy_b_value> +80000274: 00000417 auipc s0,0x0 +80000278: 1c842403 lw s0,456(s0) # 8000043c <thread_count> +8000027c: 00000297 auipc t0,0x0 +80000280: 1d42a283 lw t0,468(t0) # 80000450 <consistancy_b_hart> +80000284: 00128293 addi t0,t0,1 +80000288: 00000317 auipc t1,0x0 +8000028c: 1c532423 sw t0,456(t1) # 80000450 <consistancy_b_hart> +80000290: 04829063 bne t0,s0,800002d0 <consistancy_increment_fence> +80000294: 00000317 auipc t1,0x0 +80000298: 1a032e23 sw zero,444(t1) # 80000450 <consistancy_b_hart> +8000029c: 00000297 auipc t0,0x0 +800002a0: 1b02a283 lw t0,432(t0) # 8000044c <consistancy_a_hart> +800002a4: 00128293 addi t0,t0,1 +800002a8: 00000317 auipc t1,0x0 +800002ac: 1a532223 sw t0,420(t1) # 8000044c <consistancy_a_hart> +800002b0: 02829063 bne t0,s0,800002d0 <consistancy_increment_fence> +800002b4: 00000317 auipc t1,0x0 +800002b8: 18032c23 sw zero,408(t1) # 8000044c <consistancy_a_hart> +800002bc: 00000297 auipc t0,0x0 +800002c0: 1982a283 lw t0,408(t0) # 80000454 <consistancy_all_tested> +800002c4: 00128293 addi t0,t0,1 +800002c8: 00000317 auipc t1,0x0 +800002cc: 18532623 sw t0,396(t1) # 80000454 <consistancy_all_tested> + +800002d0 <consistancy_increment_fence>: +800002d0: 0130000f fence w,rw +800002d4: e79ff06f j 8000014c <consistancy_loop> + +800002d8 <consistancy_passed>: +800002d8: 00000417 auipc s0,0x0 +800002dc: 27042403 lw s0,624(s0) # 80000548 <consistancy_done_call> +800002e0: 00018513 mv a0,gp +800002e4: 00118193 addi gp,gp,1 +800002e8: 084000ef jal ra,8000036c <barrier_lrsc> +800002ec: 000400e7 jalr s0 + +800002f0 <barrier_amo>: +800002f0: f80002b7 lui t0,0xf8000 +800002f4: 00c28293 addi t0,t0,12 # f800000c <consistancy_done_call+0x77fffac4> +800002f8: f1402373 csrr t1,mhartid +800002fc: 01031313 slli t1,t1,0x10 +80000300: 006282b3 add t0,t0,t1 +80000304: 00a2a023 sw a0,0(t0) +80000308: 00000e97 auipc t4,0x0 +8000030c: 13ceae83 lw t4,316(t4) # 80000444 <barrier_phase> +80000310: 00000297 auipc t0,0x0 +80000314: 13028293 addi t0,t0,304 # 80000440 <barrier_value> +80000318: 00100313 li t1,1 +8000031c: 0062a2af amoadd.w t0,t1,(t0) +80000320: 00128293 addi t0,t0,1 +80000324: 00000317 auipc t1,0x0 +80000328: 11832303 lw t1,280(t1) # 8000043c <thread_count> +8000032c: 00629c63 bne t0,t1,80000344 <barrier_amo_wait> +80000330: 001e8293 addi t0,t4,1 +80000334: 00000317 auipc t1,0x0 +80000338: 10032623 sw zero,268(t1) # 80000440 <barrier_value> +8000033c: 00000317 auipc t1,0x0 +80000340: 10532423 sw t0,264(t1) # 80000444 <barrier_phase> + +80000344 <barrier_amo_wait>: +80000344: 00000297 auipc t0,0x0 +80000348: 1002a283 lw t0,256(t0) # 80000444 <barrier_phase> +8000034c: ffd28ce3 beq t0,t4,80000344 <barrier_amo_wait> +80000350: f80002b7 lui t0,0xf8000 +80000354: 01028293 addi t0,t0,16 # f8000010 <consistancy_done_call+0x77fffac8> +80000358: f1402373 csrr t1,mhartid +8000035c: 01031313 slli t1,t1,0x10 +80000360: 006282b3 add t0,t0,t1 +80000364: 00a2a023 sw a0,0(t0) +80000368: 00008067 ret + +8000036c <barrier_lrsc>: +8000036c: f80002b7 lui t0,0xf8000 +80000370: 00c28293 addi t0,t0,12 # f800000c <consistancy_done_call+0x77fffac4> +80000374: f1402373 csrr t1,mhartid +80000378: 01031313 slli t1,t1,0x10 +8000037c: 006282b3 add t0,t0,t1 +80000380: 00a2a023 sw a0,0(t0) +80000384: 00000e97 auipc t4,0x0 +80000388: 0c0eae83 lw t4,192(t4) # 80000444 <barrier_phase> +8000038c: 00000297 auipc t0,0x0 +80000390: 0b428293 addi t0,t0,180 # 80000440 <barrier_value> + +80000394 <barrier_lrsc_try>: +80000394: 1002a32f lr.w t1,(t0) +80000398: 00130313 addi t1,t1,1 +8000039c: 1862a3af sc.w t2,t1,(t0) +800003a0: fe039ae3 bnez t2,80000394 <barrier_lrsc_try> +800003a4: 00000297 auipc t0,0x0 +800003a8: 0982a283 lw t0,152(t0) # 8000043c <thread_count> +800003ac: 00629c63 bne t0,t1,800003c4 <barrier_lrsc_wait> +800003b0: 001e8293 addi t0,t4,1 +800003b4: 00000317 auipc t1,0x0 +800003b8: 08032623 sw zero,140(t1) # 80000440 <barrier_value> +800003bc: 00000317 auipc t1,0x0 +800003c0: 08532423 sw t0,136(t1) # 80000444 <barrier_phase> + +800003c4 <barrier_lrsc_wait>: +800003c4: 00000297 auipc t0,0x0 +800003c8: 0802a283 lw t0,128(t0) # 80000444 <barrier_phase> +800003cc: ffd28ce3 beq t0,t4,800003c4 <barrier_lrsc_wait> +800003d0: f80002b7 lui t0,0xf8000 +800003d4: 01028293 addi t0,t0,16 # f8000010 <consistancy_done_call+0x77fffac8> +800003d8: f1402373 csrr t1,mhartid +800003dc: 01031313 slli t1,t1,0x10 +800003e0: 006282b3 add t0,t0,t1 +800003e4: 00a2a023 sw a0,0(t0) +800003e8: 00008067 ret + +800003ec <success>: +800003ec: 00000413 li s0,0 +800003f0: f80002b7 lui t0,0xf8000 +800003f4: 00828293 addi t0,t0,8 # f8000008 <consistancy_done_call+0x77fffac0> +800003f8: f1402373 csrr t1,mhartid +800003fc: 01031313 slli t1,t1,0x10 +80000400: 006282b3 add t0,t0,t1 +80000404: 0082a023 sw s0,0(t0) +80000408: 0240006f j 8000042c <end> + +8000040c <failure>: +8000040c: 00100413 li s0,1 +80000410: f80002b7 lui t0,0xf8000 +80000414: 00828293 addi t0,t0,8 # f8000008 <consistancy_done_call+0x77fffac0> +80000418: f1402373 csrr t1,mhartid +8000041c: 01031313 slli t1,t1,0x10 +80000420: 006282b3 add t0,t0,t1 +80000424: 0082a023 sw s0,0(t0) +80000428: 0040006f j 8000042c <end> + +8000042c <end>: +8000042c: 0000006f j 8000042c <end> + +80000430 <sleep>: +80000430: fff50513 addi a0,a0,-1 +80000434: fe051ee3 bnez a0,80000430 <sleep> +80000438: 00008067 ret + +8000043c <thread_count>: +8000043c: 0000 unimp + ... + +80000440 <barrier_value>: +80000440: 0000 unimp + ... + +80000444 <barrier_phase>: +80000444: 0000 unimp + ... + +80000448 <barrier_allocator>: +80000448: 1000 addi s0,sp,32 + ... + +8000044c <consistancy_a_hart>: +8000044c: 0000 unimp + ... + +80000450 <consistancy_b_hart>: +80000450: 0000 unimp + ... + +80000454 <consistancy_all_tested>: +80000454: 0000 unimp +80000456: 0000 unimp +80000458: 00000013 nop +8000045c: 00000013 nop +80000460: 00000013 nop +80000464: 00000013 nop +80000468: 00000013 nop +8000046c: 00000013 nop +80000470: 00000013 nop +80000474: 00000013 nop +80000478: 00000013 nop +8000047c: 00000013 nop +80000480: 00000013 nop +80000484: 00000013 nop +80000488: 00000013 nop +8000048c: 00000013 nop +80000490: 00000013 nop +80000494: 00000013 nop +80000498: 00000013 nop +8000049c: 00000013 nop +800004a0: 00000013 nop +800004a4: 00000013 nop +800004a8: 00000013 nop +800004ac: 00000013 nop +800004b0: 00000013 nop +800004b4: 00000013 nop +800004b8: 00000013 nop +800004bc: 00000013 nop + +800004c0 <consistancy_a_value>: +800004c0: 0000 unimp + ... + +800004c4 <consistancy_b_value>: +800004c4: 0000 unimp +800004c6: 0000 unimp +800004c8: 00000013 nop +800004cc: 00000013 nop +800004d0: 00000013 nop +800004d4: 00000013 nop +800004d8: 00000013 nop +800004dc: 00000013 nop +800004e0: 00000013 nop +800004e4: 00000013 nop +800004e8: 00000013 nop +800004ec: 00000013 nop +800004f0: 00000013 nop +800004f4: 00000013 nop +800004f8: 00000013 nop +800004fc: 00000013 nop + +80000500 <consistancy_b_readed>: +80000500: 0000 unimp + ... + +80000504 <consistancy_a_readed>: +80000504: 0000 unimp +80000506: 0000 unimp +80000508: 00000013 nop +8000050c: 00000013 nop +80000510: 00000013 nop +80000514: 00000013 nop +80000518: 00000013 nop +8000051c: 00000013 nop +80000520: 00000013 nop +80000524: 00000013 nop +80000528: 00000013 nop +8000052c: 00000013 nop +80000530: 00000013 nop +80000534: 00000013 nop +80000538: 00000013 nop +8000053c: 00000013 nop + +80000540 <consistancy_init_call>: +80000540: 0000 unimp + ... + +80000544 <consistancy_do_call>: +80000544: 0000 unimp + ... + +80000548 <consistancy_done_call>: + ... diff --git a/VexRiscv/src/test/cpp/raw/smp/build/smp.bin b/VexRiscv/src/test/cpp/raw/smp/build/smp.bin Binary files differnew file mode 100755 index 0000000..5ce6918 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/smp/build/smp.bin diff --git a/VexRiscv/src/test/cpp/raw/smp/makefile b/VexRiscv/src/test/cpp/raw/smp/makefile new file mode 100644 index 0000000..0886c1b --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/smp/makefile @@ -0,0 +1,5 @@ +PROJ_NAME=smp + +ATOMIC=yes + +include ../common/asm.mk
\ No newline at end of file diff --git a/VexRiscv/src/test/cpp/raw/smp/src/crt.S b/VexRiscv/src/test/cpp/raw/smp/src/crt.S new file mode 100644 index 0000000..9a72bd7 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/smp/src/crt.S @@ -0,0 +1,287 @@ +#define CONSISTENCY_REDO_COUNT 50 + + +#define REPORT_OFFSET 0xF8000000 +#define REPORT_THREAD_ID 0x00 +#define REPORT_THREAD_COUNT 0x04 +#define REPORT_END 0x08 +#define REPORT_BARRIER_START 0x0C +#define REPORT_BARRIER_END 0x10 +#define REPORT_CONSISTENCY_VALUES 0x14 + +#define report(reg, id) \ + li t0, REPORT_OFFSET+id; \ + csrr t1, mhartid; \ + slli t1, t1, 16; \ + add t0, t0, t1; \ + sw reg, 0(t0); \ + +_start: + csrr s0, mhartid + report(s0, REPORT_THREAD_ID) + + +count_thread_start: + //Count up threads + li a0, 1 + la a1, thread_count + amoadd.w x0, a0, (a1) + +count_thread_wait: + //Wait everybody + lw s0, thread_count + li a0, 400 + call sleep + lw s1, thread_count + bne s1, s0, count_thread_wait + report(s1, REPORT_THREAD_COUNT) + + +barrier_amo_test: + li a0, 1 + call barrier_amo + li a0, 2 + call barrier_amo + li a0, 3 + call barrier_amo + + li a0, 4 + call barrier_lrsc + li a0, 5 + call barrier_lrsc + li a0, 6 + call barrier_lrsc + + li a0, 7 + call barrier_amo + li a0, 8 + call barrier_lrsc + + + lw gp, barrier_allocator + +consistancy_test1: + la t0, consistancy_init_load + sw t0, consistancy_init_call, t1 + la t0, consistancy_do_simple_fence + sw t0, consistancy_do_call, t1 + la t0, consistancy_test2 + sw t0, consistancy_done_call, t1 + j consistancy_start + +consistancy_test2: + la t0, consistancy_init_load + sw t0, consistancy_init_call, t1 + la t0, consistancy_do_rl_fence + sw t0, consistancy_do_call, t1 + la t0, success + sw t0, consistancy_done_call, t1 + j consistancy_start + + +consistancy_init_load: + lw s3, (s1) //Help getting the cache loaded for the consistancy check + j consistancy_do_init_done + +consistancy_do_simple_fence: + //Consistancy check : write to read ordering on two thread + sw s2, (s0) + fence w,r + lw s3, (s1) + sw s3, 64(s0) + j consistancy_join + +consistancy_do_rl_fence: + //Consistancy check : write to read ordering on two thread + sw s2, (s0) + lr.w.rl s3, (s1) + sw s3, 64(s0) + j consistancy_join + + +consistancy_start: + mv a0, gp + addi gp, gp, 1 + call barrier_lrsc + sw x0, consistancy_all_tested, t0 +consistancy_loop: + //Sync + mv a0, gp + addi gp, gp, 1 + call barrier_lrsc + + //all passed ? + lw t0, consistancy_all_tested + li t1, CONSISTENCY_REDO_COUNT + bge t0, t1, consistancy_passed + + //identify who is A, who is B + lw t0, consistancy_a_hart + lw t1, consistancy_b_hart + beq t0, t1, consistancy_join + csrr t0, mhartid + lw t1, consistancy_a_hart + la s0, consistancy_a_value + la s1, consistancy_b_value + beq t0, t1, consistancy_do + lw t1, consistancy_b_hart + la s0, consistancy_b_value + la s1, consistancy_a_value + beq t0, t1, consistancy_do + +consistancy_hart_not_involved: + mv a0, gp + addi gp, gp, 1 + call barrier_lrsc + j consistancy_join + +consistancy_do: + lw t0, consistancy_init_call + jalr t0 +consistancy_do_init_done: + li s2, 666 + mv a0, gp + addi gp, gp, 1 + call barrier_lrsc + + + lw t0, consistancy_do_call + jalr t0 + +consistancy_join: + fence rw, rw //ensure updated values + mv a0, gp + addi gp, gp, 1 + call barrier_lrsc + csrr t0, mhartid + bnez t0, consistancy_loop + +consistancy_assert: + lw t0, consistancy_a_hart + lw t1, consistancy_b_hart + beq t0, t1, consistancy_increment + lw a0, consistancy_a_readed + report(a0, REPORT_CONSISTENCY_VALUES) + lw a0, consistancy_b_readed + report(a0, REPORT_CONSISTENCY_VALUES) + +consistancy_increment: + csrr t0, mhartid + bnez t0, consistancy_loop + sw x0, (consistancy_a_value), t0 + sw x0, (consistancy_b_value), t0 + lw s0,thread_count + lw t0,consistancy_b_hart + addi t0, t0, 1 + sw t0, consistancy_b_hart, t1 + bne t0, s0, consistancy_increment_fence + sw x0, consistancy_b_hart, t1 + lw t0,consistancy_a_hart + addi t0, t0, 1 + sw t0, consistancy_a_hart, t1 + bne t0, s0, consistancy_increment_fence + sw x0, consistancy_a_hart, t1 + lw t0, consistancy_all_tested + addi t0, t0, 1 + sw t0, consistancy_all_tested, t1 +consistancy_increment_fence: + fence w, rw + j consistancy_loop + +consistancy_passed: + lw s0, consistancy_done_call + mv a0, gp + addi gp, gp, 1 + call barrier_lrsc + jalr s0 + + + +#define ENTRY_PHASE t4 +barrier_amo: + report(a0, REPORT_BARRIER_START) + lw ENTRY_PHASE, barrier_phase + la t0, barrier_value + li t1, 1 + amoadd.w t0, t1, (t0) + addi t0, t0, 1 + lw t1, thread_count + bne t0, t1, barrier_amo_wait + addi t0,ENTRY_PHASE,1 + sw x0, barrier_value, t1 + sw t0, barrier_phase, t1 +barrier_amo_wait: + lw t0, barrier_phase + beq t0, ENTRY_PHASE, barrier_amo_wait + report(a0, REPORT_BARRIER_END) + ret + +barrier_lrsc: + report(a0, REPORT_BARRIER_START) + lw ENTRY_PHASE, barrier_phase + la t0, barrier_value +barrier_lrsc_try: + lr.w t1, (t0) + addi t1, t1, 1 + sc.w t2, t1, (t0) + bnez t2, barrier_lrsc_try + lw t0, thread_count + bne t0, t1, barrier_lrsc_wait + addi t0,ENTRY_PHASE,1 + sw x0, barrier_value, t1 + sw t0, barrier_phase, t1 +barrier_lrsc_wait: + lw t0, barrier_phase + beq t0, ENTRY_PHASE, barrier_lrsc_wait + report(a0, REPORT_BARRIER_END) + ret + + + + +success: + li s0, 0 + report(s0, REPORT_END) + j end + +failure: + li s0, 1 + report(s0, REPORT_END) + j end + +end: + j end + + +sleep: + addi a0, a0, -1 + bnez a0, sleep + ret + + +thread_count: .word 0 + +.align 6 //Same cache line +barrier_value: .word 0 +barrier_phase: .word 0 +barrier_allocator: .word 0x1000 + +consistancy_a_hart: .word 0 +consistancy_b_hart: .word 0 +consistancy_all_tested: .word 0 + + +nop;nop;nop;nop;nop;nop;nop;nop; +nop;nop;nop;nop;nop;nop;nop;nop; +.align 6 //Same cache line +consistancy_a_value: .word 0 +consistancy_b_value: .word 0 + +.align 6 //Same cache line +consistancy_b_readed: .word 0 +consistancy_a_readed: .word 0 + +.align 6 //Same cache line +consistancy_init_call: .word 0 +consistancy_do_call: .word 0 +consistancy_done_call: .word 0
\ No newline at end of file diff --git a/VexRiscv/src/test/cpp/raw/smp/src/ld b/VexRiscv/src/test/cpp/raw/smp/src/ld new file mode 100644 index 0000000..93d8de8 --- /dev/null +++ b/VexRiscv/src/test/cpp/raw/smp/src/ld @@ -0,0 +1,16 @@ +OUTPUT_ARCH( "riscv" ) + +MEMORY { + onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 128K +} + +SECTIONS +{ + + .crt_section : + { + . = ALIGN(4); + *crt.o(.text) + } > onChipRam + +} |