3 files changed, 131 insertions, 0 deletions
diff --git a/VexRiscvSocSoftware/projects/briey/vga/makefile b/VexRiscvSocSoftware/projects/briey/vga/makefile
new file mode 100755
index 0000000..d065e5c
--- /dev/null
+++ b/VexRiscvSocSoftware/projects/briey/vga/makefile
@@ -0,0 +1,22 @@
+PROJ_NAME=vga
+DEBUG=yes
+BENCH=no
+MULDIV=no
+
+
+SRCS = 	$(wildcard src/*.c) \
+	    $(wildcard src/*.cpp)  \
+	    $(wildcard src/*.S)
+	    
+	    
+
+
+LDSCRIPT = ../libs/linker.ld
+INC += -I../../../libs/
+INC += -I../libs/
+
+include ../../../resources/gcc.mk
+include ../../../resources/subproject.mk
+
+
+			
diff --git a/VexRiscvSocSoftware/projects/briey/vga/src/crt.S b/VexRiscvSocSoftware/projects/briey/vga/src/crt.S
new file mode 100755
index 0000000..f4f1f23
--- /dev/null
+++ b/VexRiscvSocSoftware/projects/briey/vga/src/crt.S
@@ -0,0 +1,52 @@
+#include "../../../../resources/crt.S"
+
+#define regnum_zero 0
+#define regnum_ra   1
+#define regnum_sp   2
+#define regnum_gp   3
+#define regnum_tp   4
+#define regnum_t0   5
+#define regnum_t1   6
+#define regnum_t2   7
+#define regnum_s0   8
+#define regnum_s1   9
+#define regnum_a0  10
+#define regnum_a1  11
+#define regnum_a2  12
+#define regnum_a3  13
+#define regnum_a4  14
+#define regnum_a5  15
+#define regnum_a6  16
+#define regnum_a7  17
+#define regnum_s2  18
+#define regnum_s3  19
+#define regnum_s4  20
+#define regnum_s5  21
+#define regnum_s6  22
+#define regnum_s7  23
+#define regnum_s8  24
+#define regnum_s9  25
+#define regnum_s10 26
+#define regnum_s11 27
+#define regnum_t3  28
+#define regnum_t4  29
+#define regnum_t5  30
+#define regnum_t6  31
+
+#define r_type_insn(_f7, _rs2, _rs1, _f3, _rd, _opc) \
+.word (((_f7) << 25) | ((_rs2) << 20) | ((_rs1) << 15) | ((_f3) << 12) | ((_rd) << 7) | ((_opc) << 0))
+
+#define dataFlush(_data) \
+r_type_insn(0b0111000, 0, regnum_ ## _data, 0b101, 0, 0b0001111)
+
+
+.section .text
+.globl flushDataCache
+.type flushDataCache, @function
+flushDataCache:
+  li a0, 4096
+flushDataCacheLoop:
+  ADDI a0,a0,-32
+  dataFlush(a0)
+  bnez a0, flushDataCacheLoop
+  ret
diff --git a/VexRiscvSocSoftware/projects/briey/vga/src/main.c b/VexRiscvSocSoftware/projects/briey/vga/src/main.c
new file mode 100755
index 0000000..5501821
--- /dev/null
+++ b/VexRiscvSocSoftware/projects/briey/vga/src/main.c
@@ -0,0 +1,57 @@
+#include <stdio.h>
+#include <string.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+#include <briey.h>
+
+#define RES_X 640
+#define RES_Y 480
+
+//#define RES_X 160
+//#define RES_Y 120
+
+//#define RES_X 48
+//#define RES_Y 32
+
+__attribute__ ((section (".noinit"))) __attribute__ ((aligned (4*8))) uint16_t vgaFramebuffer[RES_Y][RES_X];
+
+extern void flushDataCache(uint32_t dummy);
+
+int main() {
+	Uart_Config uartConfig;
+	uartConfig.dataLength = 8;
+	uartConfig.parity = NONE;
+	uartConfig.stop = ONE;
+	uartConfig.clockDivider = 50000000/8/115200-1;
+	uart_applyConfig(UART,&uartConfig);
+
+
+    vga_stop(VGA_BASE);
+    VGA_BASE->TIMING = vga_h640_v480_r60;  // vga_simRes   vga_h640_v480_r60 vga_simRes_h160_v120
+    VGA_BASE->FRAME_SIZE = RES_X*RES_Y*2-1;
+    VGA_BASE->FRAME_BASE = (uint32_t)vgaFramebuffer;
+    vga_run(VGA_BASE);
+
+    uint16_t offset = 0;
+    while(1){
+    	uint16_t *ptr = &vgaFramebuffer[0][0];
+    	for(uint32_t y = 0;y < RES_Y;y++){
+    		uint16_t c = (((y + offset) & 0x1F) << 6);
+        	for(uint32_t x = 0;x < RES_X;x++){
+        		*ptr = ((uint16_t)(x & 0x1F)) + c;
+        		ptr++;
+        	}
+    	}
+    	offset+=4;
+    	flushDataCache(0);
+    	uart_write(UART, '\n');
+    }
+}
+
+
+void irqCallback(){
+
+}
+
+