3 files changed, 135 insertions, 0 deletions
diff --git a/VexRiscvSocSoftware/projects/raw/simple/makefile b/VexRiscvSocSoftware/projects/raw/simple/makefile
new file mode 100644
index 0000000..19e06cc
--- /dev/null
+++ b/VexRiscvSocSoftware/projects/raw/simple/makefile
@@ -0,0 +1,16 @@
+PROJ_NAME=simple
+DEBUG=no
+BENCH=no
+MULDIV?=yes
+
+SRCS = 	$(wildcard src/*.c)  \
+	$(wildcard src/*.S)
+
+LDSCRIPT = ../libs/simple.ld
+
+
+include ../../../resources/gcc.mk
+include ../../../resources/subproject.mk
+
+
+			
diff --git a/VexRiscvSocSoftware/projects/raw/simple/src/crt.S b/VexRiscvSocSoftware/projects/raw/simple/src/crt.S
new file mode 100755
index 0000000..0e7c8f5
--- /dev/null
+++ b/VexRiscvSocSoftware/projects/raw/simple/src/crt.S
@@ -0,0 +1,98 @@
+.global crtStart
+.global main
+.global irqCallback
+
+crtStart:
+  j crtInit
+  nop
+  nop
+  nop
+  nop
+  nop
+  nop
+  nop
+
+.global  trap_entry
+trap_entry:
+  sw x1,  - 1*4(sp)
+  sw x5,  - 2*4(sp)
+  sw x6,  - 3*4(sp)
+  sw x7,  - 4*4(sp)
+  sw x10, - 5*4(sp)
+  sw x11, - 6*4(sp)
+  sw x12, - 7*4(sp)
+  sw x13, - 8*4(sp)
+  sw x14, - 9*4(sp)
+  sw x15, -10*4(sp)
+  sw x16, -11*4(sp)
+  sw x17, -12*4(sp)
+  sw x28, -13*4(sp)
+  sw x29, -14*4(sp)
+  sw x30, -15*4(sp)
+  sw x31, -16*4(sp)
+  addi sp,sp,-16*4
+  call irqCallback
+  lw x1 , 15*4(sp)
+  lw x5,  14*4(sp)
+  lw x6,  13*4(sp)
+  lw x7,  12*4(sp)
+  lw x10, 11*4(sp)
+  lw x11, 10*4(sp)
+  lw x12,  9*4(sp)
+  lw x13,  8*4(sp)
+  lw x14,  7*4(sp)
+  lw x15,  6*4(sp)
+  lw x16,  5*4(sp)
+  lw x17,  4*4(sp)
+  lw x28,  3*4(sp)
+  lw x29,  2*4(sp)
+  lw x30,  1*4(sp)
+  lw x31,  0*4(sp)
+  addi sp,sp,16*4
+  mret
+  .text
+
+
+crtInit:
+ /* .option push
+  .option norelax
+  la gp, __global_pointer$
+  .option pop*/
+  la sp, _stack_start
+
+bss_init:
+  la a0, _bss_start
+  la a1, _bss_end
+bss_loop:
+  beq a0,a1,bss_done
+  sw zero,0(a0)
+  add a0,a0,4
+  j bss_loop
+bss_done:
+
+ctors_init:
+  la a0, _ctors_start
+  addi sp,sp,-4
+ctors_loop:
+  la a1, _ctors_end
+  beq a0,a1,ctors_done
+  lw a3,0(a0)
+  add a0,a0,4
+  sw a0,0(sp)
+  jalr  a3
+  lw a0,0(sp)
+  j ctors_loop
+ctors_done:
+  addi sp,sp,4
+
+
+  li a0, 0x880     //880 enable timer + external interrupts
+  csrw mie,a0
+  li a0, 0x1808     //1808 enable interrupts
+  csrw mstatus,a0
+
+  call main
+infinitLoop:
+  j infinitLoop
+
+
diff --git a/VexRiscvSocSoftware/projects/raw/simple/src/main.c b/VexRiscvSocSoftware/projects/raw/simple/src/main.c
new file mode 100755
index 0000000..dbefb08
--- /dev/null
+++ b/VexRiscvSocSoftware/projects/raw/simple/src/main.c
@@ -0,0 +1,21 @@
+
+#define TEST_COM_BASE ((volatile int*)(0xF00FFF00))
+
+int var1 = 32;
+int var2 = 0;
+int var3 = 0;
+int main() {
+	TEST_COM_BASE[0] = var1 + var2 + var3;
+	var1 += 1;
+}
+
+
+void irqCallback(int irq){
+
+}
+
+int miaou(){
+	return 2;
+}
+
+