diff options
Diffstat (limited to 'pnr')
| -rw-r--r-- | pnr/de1_murax_franz/de1_murax_franz_pins.tcl | 20 | ||||
| -rw-r--r-- | pnr/de1_murax_franz/makefile | 8 | ||||
| -rw-r--r-- | pnr/makefile | 92 |
3 files changed, 120 insertions, 0 deletions
diff --git a/pnr/de1_murax_franz/de1_murax_franz_pins.tcl b/pnr/de1_murax_franz/de1_murax_franz_pins.tcl new file mode 100644 index 0000000..c2fb5fb --- /dev/null +++ b/pnr/de1_murax_franz/de1_murax_franz_pins.tcl @@ -0,0 +1,20 @@ +# assign pin locations to a quartus project + +#---------------------------------------------------------------------- +# Pin Assignments +set_location_assignment PIN_R20 -to LEDR[0] +set_location_assignment PIN_R19 -to LEDR[1] +set_location_assignment PIN_U19 -to LEDR[2] +set_location_assignment PIN_Y19 -to LEDR[3] +set_location_assignment PIN_T18 -to LEDR[4] +set_location_assignment PIN_V19 -to LEDR[5] +set_location_assignment PIN_Y18 -to LEDR[6] +set_location_assignment PIN_U18 -to LEDR[7] +set_location_assignment PIN_L1 -to CLOCK_50 +set_location_assignment PIN_R22 -to KEY0 +set_location_assignment PIN_F14 -to uart_rxd +set_location_assignment PIN_G12 -to uart_txd +set_location_assignment PIN_H13 -to jtag_tck +set_location_assignment PIN_G15 -to jtag_tms +set_location_assignment PIN_E15 -to jtag_tdi +set_location_assignment PIN_G16 -to jtag_tdo diff --git a/pnr/de1_murax_franz/makefile b/pnr/de1_murax_franz/makefile new file mode 100644 index 0000000..f3ebc19 --- /dev/null +++ b/pnr/de1_murax_franz/makefile @@ -0,0 +1,8 @@ +PROJECT = de1_murax_franz + +# Here the VHDL files for synthesis are defined. +include ../../sim/$(PROJECT)/makefile.sources + +SOURCE_FILES = $(SYN_SOURCE_FILES) + +include ../makefile diff --git a/pnr/makefile b/pnr/makefile new file mode 100644 index 0000000..84a3b03 --- /dev/null +++ b/pnr/makefile @@ -0,0 +1,92 @@ +## ---------------------------------------------------------------------------- +## Script : makefile +## ---------------------------------------------------------------------------- +## Author : Johann Faerber, Friedrich Beckmann +## Company : University of Applied Sciences Augsburg +## ---------------------------------------------------------------------------- +## Description: This makefile allows automating design flow with Quartus, +## it is based on a design directory structure shown at +## the end of this file. +## ---------------------------------------------------------------------------- + +################################################################### +# Main Targets +# +################################################################### + +help: + @echo '"make" does intentionally nothing. Type:' + @echo ' "make qproject" to create quartus project only' + @echo ' "make compile" to synthesize the design' + @echo ' "make prog" to configure programmable device' + @echo ' "make quartus" to start quartus graphical user interface' + @echo ' "make clean" to remove all generated files' + +$(PROJECT).sdc: + # create a default timing constraint file assuming CLOCK_50 + echo "create_clock -period 20.000 -name CLOCK_50 CLOCK_50" > $(PROJECT).sdc + echo "set_input_delay -clock CLOCK_50 2 [all_inputs]" >> $(PROJECT).sdc + echo "set_output_delay -clock CLOCK_50 2 [all_outputs]" >> $(PROJECT).sdc + +qproject: $(PROJECT).qpf + +$(PROJECT).qpf: $(SOURCE_FILES) ../../scripts/create_quartus_project_settings.tcl $(PROJECT)_pins.tcl $(PROJECT).sdc + # assign VHDL design files + rm -rf quartus_vhdl_source_files.tcl + for source_file in $(SOURCE_FILES); do \ + echo set_global_assignment -name VHDL_FILE $$source_file >> quartus_vhdl_source_files.tcl; \ + done + # just create a quartus project + quartus_sh -t ../../scripts/create_quartus_project_settings.tcl -projectname $(PROJECT) + +compile: flowsummary.log + +flowsummary.log: $(PROJECT).qpf ../../scripts/quartus_project_flow.tcl + quartus_sh -t ../../scripts/quartus_project_flow.tcl -projectname $(PROJECT) + +prog: flowsummary.log + quartus_pgm -c USB-Blaster --mode jtag --operation="p;$(PROJECT).sof" + +quartus: $(PROJECT).qpf + # start quartus gui + quartus $(PROJECT).qpf & + +clean: + rm -rf *~ *.rpt *.chg *.log quartus_vhdl_source_files.tcl *.htm *.eqn *.pin *.sof *.pof db incremental_db *.qpf *.qsf *.summary $(PROJECT).* + +## ---------------------------------------------------------------------------- +## Description: +## ------------ +## assumes the following design directory structure as prerequisite +## +## DigitaltechnikPraktikum +## | +## +---src +## | and2gate_equation.vhd +## | invgate_equation.vhd +## | mux2to1_structure.vhd +## | or2gate_equation.vhd +## | t_mux2to1.vhd +## | de1_mux2to1_structure.vhd +## | +## +---sim +## | | makefile +## | | +## | \---mux2to1 +## | makefile +## | makefile.sources +## | +## +---pnr +## | | makefile +## | | +## | \---de1_mux2to1 +## | de1_mux2to1_pins.tcl +## | makefile +## | +## \---scripts +## de1_pin_assignments_minimumio.csv +## de1_pin_assignments_minimumio.tcl +## modelsim.ini +## quartus_project_settings.tcl +## ---------------------------------------------------------------------------- + |