1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
|
`timescale 1ns / 1ps
module toplevel(
input CLK,
input BUT1,
input BUT2,
output LED1,
output LED2
);
assign LED1 = io_gpioA_write[0];
assign LED2 = io_gpioA_write[7];
wire [31:0] io_gpioA_read;
wire [31:0] io_gpioA_write;
wire [31:0] io_gpioA_writeEnable;
wire io_mainClk;
// Use PLL to downclock external clock.
toplevel_pll toplevel_pll_inst(.REFERENCECLK(CLK),
.PLLOUTCORE(io_mainClk),
.PLLOUTGLOBAL(),
.RESET(1'b1));
Murax murax (
.io_asyncReset(1'b0),
.io_mainClk (io_mainClk),
.io_jtag_tck(1'b0),
.io_jtag_tdi(1'b0),
.io_jtag_tdo(),
.io_jtag_tms(1'b0),
.io_gpioA_read (io_gpioA_read),
.io_gpioA_write (io_gpioA_write),
.io_gpioA_writeEnable(io_gpioA_writeEnable),
.io_uart_txd(),
.io_uart_rxd(0'b0)
);
endmodule
|
