1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
|
package vexriscv
import java.io.File
import org.scalatest.funsuite.AnyFunSuite
import spinal.core.SpinalVerilog
import vexriscv.demo._
import scala.sys.process._
class DhrystoneBench extends AnyFunSuite {
def doCmd(cmd: String): String = {
val stdOut = new StringBuilder()
class Logger extends ProcessLogger {
override def err(s: => String): Unit = {
if (!s.startsWith("ar: creating ")) println(s)
}
override def out(s: => String): Unit = {
println(s)
stdOut ++= s
}
override def buffer[T](f: => T) = f
}
Process(cmd, new File("src/test/cpp/regression")).!(new Logger)
stdOut.toString()
}
val report = new StringBuilder()
def getDmips(name: String, gen: => Unit, testCmd: String): Unit = {
var genPassed = false
test(name + "_gen") {
gen
genPassed = true
}
test(name + "_test") {
assert(genPassed)
val str = doCmd(testCmd)
assert(!str.contains("FAIL"))
val intFind = "(\\d+\\.?)+".r
val dmips = intFind.findFirstIn("DMIPS per Mhz\\: (\\d+.?)+".r.findAllIn(str).toList.last).get.toDouble
val coremarkTicks = intFind.findFirstIn("Total ticks \\: (\\d+.?)+".r.findAllIn(str).toList.last).get.toDouble
val coremarkIterations = intFind.findFirstIn("Iterations \\: (\\d+.?)+".r.findAllIn(str).toList.last).get.toDouble
val coremarkHzs = intFind.findFirstIn("DCLOCKS_PER_SEC=(\\d+.?)+".r.findAllIn(str).toList.last).get.toDouble
val coremarkPerMhz = 1e6 * coremarkIterations / coremarkTicks
report ++= s"$name -> $dmips DMIPS/Mhz $coremarkPerMhz Coremark/Mhz\n"
}
}
for(withMemoryStage <- List(false, true)){
val stages = if(withMemoryStage) "Three" else "Two"
getDmips(
name = s"Gen${stages}StageArty",
gen = SpinalVerilog(GenTwoThreeStage.cpu(
withMulDiv = false,
bypass = false,
barrielShifter = false,
withMemoryStage = withMemoryStage
)),
testCmd = "make clean run REDO=10 IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no COREMARK=yes"
)
getDmips(
name = s"Gen${stages}StageBarrielArty",
gen = SpinalVerilog(GenTwoThreeStage.cpu(
withMulDiv = false,
bypass = true,
barrielShifter = true,
withMemoryStage = withMemoryStage
)),
testCmd = "make clean run REDO=10 IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no COREMARK=yes"
)
getDmips(
name = s"Gen${stages}StageMDArty",
gen = SpinalVerilog(GenTwoThreeStage.cpu(
withMulDiv = true,
bypass = false,
barrielShifter = false,
withMemoryStage = withMemoryStage
)),
testCmd = "make clean run REDO=10 IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=yes DIV=yes COREMARK=yes"
)
getDmips(
name = s"Gen${stages}StageMDBarrielArty",
gen = SpinalVerilog(GenTwoThreeStage.cpu(
withMulDiv = true,
bypass = true,
barrielShifter = true,
withMemoryStage = withMemoryStage
)),
testCmd = "make clean run REDO=10 IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=yes DIV=yes COREMARK=yes"
)
}
getDmips(
name = "GenSmallestNoCsr",
gen = GenSmallestNoCsr.main(null),
testCmd = "make clean run REDO=10 IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no COREMARK=yes"
)
getDmips(
name = "GenSmallest",
gen = GenSmallest.main(null),
testCmd = "make clean run REDO=10 IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no COREMARK=yes"
)
getDmips(
name = "GenSmallAndProductive",
gen = GenSmallAndProductive.main(null),
testCmd = "make clean run REDO=10 IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no COREMARK=yes"
)
getDmips(
name = "GenSmallAndProductiveWithICache",
gen = GenSmallAndProductiveICache.main(null),
testCmd = "make clean run REDO=10 IBUS=CACHED DBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no COREMARK=yes"
)
getDmips(
name = "GenFullNoMmuNoCache",
gen = GenFullNoMmuNoCache.main(null),
testCmd = "make clean run REDO=10 IBUS=SIMPLE DBUS=SIMPLE CSR=no MMU=no COREMARK=yes"
)
getDmips(
name = "GenNoCacheNoMmuMaxPerf",
gen = GenNoCacheNoMmuMaxPerf.main(null),
testCmd = "make clean run REDO=10 MMU=no CSR=no DBUS=SIMPLE IBUS=SIMPLE COREMARK=yes"
)
getDmips(
name = "GenFullNoMmuMaxPerf",
gen = GenFullNoMmuMaxPerf.main(null),
testCmd = "make clean run REDO=10 MMU=no CSR=no COREMARK=yes"
)
getDmips(
name = "GenFullNoMmu",
gen = GenFullNoMmu.main(null),
testCmd = "make clean run REDO=10 MMU=no CSR=no COREMARK=yes"
)
getDmips(
name = "GenFull",
gen = GenFull.main(null),
testCmd = "make clean run REDO=10 CSR=no MMU=no COREMARK=yes"
)
getDmips(
name = "GenLinuxBalenced",
gen = LinuxGen.main(Array.fill[String](0)("")),
testCmd = "make clean run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD DHRYSTONE=yes SUPERVISOR=yes MMU=no CSR=yes CSR_SKIP_TEST=yes COMPRESSED=no MUL=yes DIV=yes LRSC=yes AMO=yes REDO=10 TRACE=no COREMARK=yes LINUX_REGRESSION=no"
)
test("final_report") {
println(report)
}
}
|
