add txautomat and rxautomatHEADmaster

3 files changed, 42 insertions, 0 deletions

diff --git a/src/rxautomat.vhd b/src/rxautomat.vhd
new file mode 100644
index 0000000..3ce19de
--- /dev/null
+++ b/src/rxautomat.vhd
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity rxautomat is
+  port (
+    clk          : in std_ulogic;
+    rst_n        : in std_ulogic;
+    rxchar       : in std_ulogic_vector(7 downto 0);
+    rxchar_valid : in std_ulogic;
+    led0_o       : out std_ulogic_vector(3 downto 0);
+    led1_o       : out std_ulogic_vector(3 downto 0);
+    led2_o       : out std_ulogic_vector(3 downto 0);
+    led3_o       : out std_ulogic_vector(3 downto 0);
+    send_ok_o    : out std_ulogic);
+end entity;
+
+architecture rtl of rxautomat is
+begin
+
+end architecture rtl; 
+
diff --git a/src/txautomat.vhd b/src/txautomat.vhd
new file mode 100644
index 0000000..7ec2b91
--- /dev/null
+++ b/src/txautomat.vhd
@@ -0,0 +1,18 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity txautomat is
+  port (
+    clk            : in std_ulogic;
+    rst_n          : in std_ulogic;
+    start_ok_i     : in std_ulogic
+    txchar_o       : out std_ulogic_vector(7 downto 0);
+    txchar_valid_o : out std_ulogic);
+end entity;
+
+architecture rtl of txautomat is
+begin
+
+end architecture rtl; 
+
diff --git a/vhdl_ls.toml b/vhdl_ls.toml
index 71576ef..aa70fe3 100644
--- a/vhdl_ls.toml
+++ b/vhdl_ls.toml
@@ -34,6 +34,8 @@ top_uart.files = [
     ,'src/uart_rx_baudcnt.vhd'
     ,'src/uart_rx_bitcnt.vhd'
     ,'src/uart_rx.vhd'
+    ,'src/rxautomat.vhd'
+    ,'src/txautomat.vhd'
     ,'src/top_uart.vhd'
     ,'src/t_top_uart.vhd'
     ]