top_uart solutions

4 files changed, 48 insertions, 8 deletions

diff --git a/sim/top_uart/view_signals.gtkw b/sim/top_uart/view_signals.gtkw
index 272ac13..4dc4a96 100644
--- a/sim/top_uart/view_signals.gtkw
+++ b/sim/top_uart/view_signals.gtkw
@@ -1,17 +1,19 @@
 [*]
 [*] GTKWave Analyzer v3.3.118 (w)1999-2023 BSI
-[*] Tue May 14 14:13:35 2024
+[*] Tue May 14 14:43:08 2024
 [*]
 [dumpfile] "/home/caeuser/projects/dtlab/sim/top_uart/t_top_uart.ghw"
-[dumpfile_mtime] "Tue May 14 14:10:01 2024"
-[dumpfile_size] 2003
+[dumpfile_mtime] "Tue May 14 14:41:32 2024"
+[dumpfile_size] 2702
 [savefile] "/home/caeuser/projects/dtlab/sim/top_uart/view_signals.gtkw"
 [timestart] 0
 [size] 1170 600
-[pos] 38 -78
+[pos] -1 -1
 *-28.012674 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] top.
 [treeopen] top.t_top_uart.
+[treeopen] top.t_top_uart.top_uart_inst.
+[treeopen] top.t_top_uart.top_uart_inst.baudcnt_inst.
 [sst_width] 245
 [signals_width] 169
 [sst_expanded] 1
@@ -23,5 +25,9 @@ top.t_top_uart.sim_rst_n
 #{top.t_top_uart.sim_sw[9:0]} top.t_top_uart.sim_sw[9] top.t_top_uart.sim_sw[8] top.t_top_uart.sim_sw[7] top.t_top_uart.sim_sw[6] top.t_top_uart.sim_sw[5] top.t_top_uart.sim_sw[4] top.t_top_uart.sim_sw[3] top.t_top_uart.sim_sw[2] top.t_top_uart.sim_sw[1] top.t_top_uart.sim_sw[0]
 @28
 top.t_top_uart.sim_x
+top.t_top_uart.top_uart_inst.start
+top.t_top_uart.top_uart_inst.en
+@25
+#{top.t_top_uart.top_uart_inst.baudcnt_inst.cnt[9:0]} top.t_top_uart.top_uart_inst.baudcnt_inst.cnt[9] top.t_top_uart.top_uart_inst.baudcnt_inst.cnt[8] top.t_top_uart.top_uart_inst.baudcnt_inst.cnt[7] top.t_top_uart.top_uart_inst.baudcnt_inst.cnt[6] top.t_top_uart.top_uart_inst.baudcnt_inst.cnt[5] top.t_top_uart.top_uart_inst.baudcnt_inst.cnt[4] top.t_top_uart.top_uart_inst.baudcnt_inst.cnt[3] top.t_top_uart.top_uart_inst.baudcnt_inst.cnt[2] top.t_top_uart.top_uart_inst.baudcnt_inst.cnt[1] top.t_top_uart.top_uart_inst.baudcnt_inst.cnt[0]
 [pattern_trace] 1
 [pattern_trace] 0
diff --git a/src/baudcnt.vhd b/src/baudcnt.vhd
index 4e18aa7..ec46aa5 100644
--- a/src/baudcnt.vhd
+++ b/src/baudcnt.vhd
@@ -1,5 +1,6 @@
 library ieee;
 use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
 
 entity baudcnt is
   port (
@@ -10,7 +11,12 @@ entity baudcnt is
 end entity;
 
 architecture rtl of baudcnt is
+  signal cnt, ncnt : unsigned(9 downto 0);
 begin
-
+  cnt <= (others => '0') when rst_n = '0' else
+         ncnt when rising_edge(clk);
+  ncnt <= to_unsigned(0, cnt'length) when start_i = '1' or cnt = 2 else
+          cnt + 1;
+  en_o <= '1' when cnt = 2 else '0';
 end architecture rtl;
 
diff --git a/src/top_uart.vhd b/src/top_uart.vhd
index 4cc6c01..d53f06d 100644
--- a/src/top_uart.vhd
+++ b/src/top_uart.vhd
@@ -16,13 +16,37 @@ architecture rtl of top_uart is
   signal clk     : std_ulogic;
   signal rst_n   : std_ulogic;
   signal en, txd : std_ulogic;
+  signal start   : std_ulogic;
 begin
   -- Assign the inputs to signals with reasonable names
   clk <= CLOCK_50;
   rst_n <= KEY(0);
 
-  txd <= '0';
-  en <= '0';
+  edge_inst: entity work.edge
+   port map(
+      clk    => clk,
+      rst_n  => rst_n,
+      x_i    => KEY(1),
+      edge_o => start
+  );
+
+  baudcnt_inst: entity work.baudcnt
+   port map(
+      clk     => clk,
+      rst_n   => rst_n,
+      start_i => start,
+      en_o    => en
+  );
+
+  uart_tx_shift_inst: entity work.uart_tx_shift
+   port map(
+      clk     => clk,
+      rst_n   => rst_n,
+      start_i => start,
+      en_i    => en,
+      d_i     => SW(7 downto 0),
+      tx_o    => txd
+  );
 
   -- Set the outputs;
   EXP(7 downto 4) <= "0000";
diff --git a/src/uart_tx_shift.vhd b/src/uart_tx_shift.vhd
index b81fe78..f5724f6 100644
--- a/src/uart_tx_shift.vhd
+++ b/src/uart_tx_shift.vhd
@@ -12,7 +12,11 @@ entity uart_tx_shift is
 end entity;
 
 architecture rtl of uart_tx_shift is
+  signal sr, srn : std_ulogic_vector(8 downto 0);
 begin
-
+  sr <= (others => '1') when rst_n = '0' else srn when rising_edge(clk);
+  srn <= d_i & '0' when start_i = '1' else
+         '1' & sr(8 downto 1) when en_i = '1' else sr;
+  tx_o <= sr(0);
 end architecture rtl;