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2024-05-28uart rx solutionsolutionsFriedrich Beckmann
2024-05-28top_uart solutionsFriedrich Beckmann
2024-05-28add top_count solutionsFriedrich Beckmann
2024-05-28fixed Quartus Problem with indexed assignmentFriedrich Beckmann
2024-05-28add ringcnt to top_shiftFriedrich Beckmann
2024-05-28moved edgedetection to edge module, 6 clock designFriedrich Beckmann
2024-05-28add solution top_hexFriedrich Beckmann
2024-05-28added top_simple solutionsFriedrich Beckmann
2024-05-28add uart_rx_edgeFriedrich Beckmann
2024-05-27uart rxFriedrich Beckmann
2024-05-15sim/makefile: added synth step to simFriedrich Beckmann
2024-05-14add top_uartFriedrich Beckmann
2024-05-14bring back full scripts/de1_pin_assignments_minimumioFriedrich Beckmann
2024-05-10add pwmFriedrich Beckmann
2024-05-10add top_countFriedrich Beckmann
2024-04-28sim: make the output of the make command more verboseFriedrich Beckmann
2024-04-28.gitignore: add ghdl generated files and quartus_vhdl..Friedrich Beckmann
2024-04-28top_shift: add edge.vhd and ringcnt.vhd as empty modulesFriedrich Beckmann
2024-03-11top_hex: add adderFriedrich Beckmann
2024-03-08add top_hexFriedrich Beckmann
2024-03-07top_simple: add LEDG for outputsFriedrich Beckmann
2024-03-07pnr/makefile: fixed bug in rtlview targetFriedrich Beckmann
2024-03-07add top_shift and simulationFriedrich Beckmann
2024-03-06.gitignore: added quartus generated filesFriedrich Beckmann
2024-03-06first commit with top_simple synthesisFriedrich Beckmann
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-04 10:14:26 +0000