add ringcnt to top_shift

3 files changed, 73 insertions, 19 deletions

diff --git a/sim/top_shift/view_signals.gtkw b/sim/top_shift/view_signals.gtkw
index 5a9014a..17d7e6e 100644
--- a/sim/top_shift/view_signals.gtkw
+++ b/sim/top_shift/view_signals.gtkw
@@ -1,33 +1,69 @@
 [*]
 [*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
-[*] Sun Apr 28 09:10:12 2024
+[*] Sun Apr 28 16:14:58 2024
 [*]
 [dumpfile] "/home/caeuser/projects/dtlab/sim/top_shift/t_top_shift.ghw"
-[dumpfile_mtime] "Sun Apr 28 09:07:59 2024"
-[dumpfile_size] 1389
+[dumpfile_mtime] "Sun Apr 28 16:08:26 2024"
+[dumpfile_size] 2655
 [savefile] "/home/caeuser/projects/dtlab/sim/top_shift/view_signals.gtkw"
 [timestart] 0
 [size] 1101 671
-[pos] -210 -116
-*-26.740849 120000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[pos] -1 -1
+*-26.740849 76800000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] top.
 [treeopen] top.t_top_shift.
 [treeopen] top.t_top_shift.dut.
+[treeopen] top.t_top_shift.dut.edge_inst.
 [sst_width] 245
-[signals_width] 173
+[signals_width] 262
 [sst_expanded] 1
-[sst_vpaned_height] 216
+[sst_vpaned_height] 268
 @28
 top.t_top_shift.dut.clk
 top.t_top_shift.dut.rst_n
 top.t_top_shift.dut.x
-@800028
-#{top.t_top_shift.dut.sr[1:0]} top.t_top_shift.dut.sr[1] top.t_top_shift.dut.sr[0]
+@c00022
+#{top.t_top_shift.dut.edge_inst.sr[5:0]} top.t_top_shift.dut.edge_inst.sr[5] top.t_top_shift.dut.edge_inst.sr[4] top.t_top_shift.dut.edge_inst.sr[3] top.t_top_shift.dut.edge_inst.sr[2] top.t_top_shift.dut.edge_inst.sr[1] top.t_top_shift.dut.edge_inst.sr[0]
 @28
-top.t_top_shift.dut.sr[1]
-top.t_top_shift.dut.sr[0]
-@29
+top.t_top_shift.dut.edge_inst.sr[5]
+top.t_top_shift.dut.edge_inst.sr[4]
+top.t_top_shift.dut.edge_inst.sr[3]
+top.t_top_shift.dut.edge_inst.sr[2]
+top.t_top_shift.dut.edge_inst.sr[1]
+top.t_top_shift.dut.edge_inst.sr[0]
+@1401200
+-group_end
+@28
+top.t_top_shift.dut.edge_inst.edge_o
 top.t_top_shift.dut.en
+@c00022
+#{top.t_top_shift.sim_ledr[9:0]} top.t_top_shift.sim_ledr[9] top.t_top_shift.sim_ledr[8] top.t_top_shift.sim_ledr[7] top.t_top_shift.sim_ledr[6] top.t_top_shift.sim_ledr[5] top.t_top_shift.sim_ledr[4] top.t_top_shift.sim_ledr[3] top.t_top_shift.sim_ledr[2] top.t_top_shift.sim_ledr[1] top.t_top_shift.sim_ledr[0]
+@28
+top.t_top_shift.sim_ledr[9]
+top.t_top_shift.sim_ledr[8]
+top.t_top_shift.sim_ledr[7]
+top.t_top_shift.sim_ledr[6]
+top.t_top_shift.sim_ledr[5]
+top.t_top_shift.sim_ledr[4]
+top.t_top_shift.sim_ledr[3]
+top.t_top_shift.sim_ledr[2]
+top.t_top_shift.sim_ledr[1]
+top.t_top_shift.sim_ledr[0]
+@1401200
+-group_end
+@800022
+#{top.t_top_shift.sim_exp[7:0]} top.t_top_shift.sim_exp[7] top.t_top_shift.sim_exp[6] top.t_top_shift.sim_exp[5] top.t_top_shift.sim_exp[4] top.t_top_shift.sim_exp[3] top.t_top_shift.sim_exp[2] top.t_top_shift.sim_exp[1] top.t_top_shift.sim_exp[0]
+@28
+top.t_top_shift.sim_exp[7]
+top.t_top_shift.sim_exp[6]
+@29
+top.t_top_shift.sim_exp[5]
+@28
+top.t_top_shift.sim_exp[4]
+top.t_top_shift.sim_exp[3]
+top.t_top_shift.sim_exp[2]
+top.t_top_shift.sim_exp[1]
+top.t_top_shift.sim_exp[0]
 @1001200
 -group_end
 [pattern_trace] 1
diff --git a/src/ringcnt.vhd b/src/ringcnt.vhd
index 5fc0d60..1c46679 100644
--- a/src/ringcnt.vhd
+++ b/src/ringcnt.vhd
@@ -1,11 +1,18 @@
 library ieee;
 use ieee.std_logic_1164.all;
 
-entity ringcnt is 
+entity ringcnt is
+  port (
+    clk  : in std_ulogic;
+    rst_n : in std_ulogic;
+    en_i  : in std_ulogic;
+    y_o   : out std_ulogic_vector(9 downto 0));
 end entity;
 
 architecture rtl of ringcnt is
+  signal rc, rcn : std_ulogic_vector(9 downto 0);
 begin
-
+  rc <= "1000000000" when rst_n = '0' else rcn when rising_edge(clk);
+  rcn <= rc when en_i = '0' else rc(0) & rc(9 downto 1);
+  y_o <= rc;
 end architecture rtl; 
-
diff --git a/src/top_shift.vhd b/src/top_shift.vhd
index 5b9db02..96691e0 100644
--- a/src/top_shift.vhd
+++ b/src/top_shift.vhd
@@ -15,6 +15,8 @@ architecture rtl of top_shift is
   signal rst_n   : std_ulogic;
   signal x       : std_ulogic;
   signal en      : std_ulogic;
+  signal en_edge : std_ulogic;
+  signal led     : std_ulogic_vector(9 downto 0);
 begin
   -- Assign the inputs to signals with reasonable names
   clk <= CLOCK_50;
@@ -26,15 +28,24 @@ begin
       clk    => clk,
       rst_n  => rst_n,
       x_i    => x,
-      edge_o => en);
+      edge_o => en_edge);
+
+  ringcnt_inst: entity work.ringcnt
+   port map(
+      clk => clk,
+      rst_n => rst_n,
+      en_i => en,
+      y_o => led);
+
+  en <= '1' when SW(0) = '1' else en_edge;
 
   -- Set the outputs;
-  EXP <= (7 downto 4 => '0',
+  EXP <= (7 downto 4 => led(9 downto 6),
           3 => en,
           2 => x,
           1 => rst_n,
           0 => clk);
-  LEDR <= SW;
+  LEDR <= led;
   LEDG <= KEY;
 
-end architecture rtl;
\ No newline at end of file
+end architecture rtl;