moved edgedetection to edge module, 6 clock design

3 files changed, 21 insertions, 21 deletions

diff --git a/src/edge.vhd b/src/edge.vhd
index 23dba70..d510660 100644
--- a/src/edge.vhd
+++ b/src/edge.vhd
@@ -10,7 +10,11 @@ entity edge is
 end entity;
 
 architecture rtl of edge is
+  signal sr, srnext : std_ulogic_vector(5 downto 0);
 begin
-
+  sr <= "000000" when rst_n = '0' else srnext when rising_edge(clk);
+  srnext(5) <= x_i;
+  srnext(4 downto 0) <= sr(5 downto 1);
+  edge_o <= '1' when sr = "111000" or sr = "000111" else '0';
 end architecture rtl;
 
diff --git a/src/t_top_shift.vhd b/src/t_top_shift.vhd
index ddf76a1..e789c85 100644
--- a/src/t_top_shift.vhd
+++ b/src/t_top_shift.vhd
@@ -45,10 +45,17 @@ begin
       wait until falling_edge(sim_clk);
     end loop;
     sim_x <= '1';
-    wait until falling_edge(sim_clk);
-    wait until falling_edge(sim_clk);
+    wait for 100 ns;
     sim_x <= '0';
-    wait for 200 ns;
+    wait for 40 ns;
+    sim_x <= '1';
+    wait for 100 ns;
+    sim_x <= '0';
+    wait for 100 ns;
+    sim_x <= '1';
+    wait for 40 ns;
+    sim_x <= '0';
+    wait for 100 ns;
     simstop <= true;
     wait;
   end process ;
diff --git a/src/top_shift.vhd b/src/top_shift.vhd
index d0c6f44..5b9db02 100644
--- a/src/top_shift.vhd
+++ b/src/top_shift.vhd
@@ -14,7 +14,6 @@ architecture rtl of top_shift is
   signal clk     : std_ulogic;
   signal rst_n   : std_ulogic;
   signal x       : std_ulogic;
-  signal sr, srnext : std_ulogic_vector(1 downto 0);
   signal en      : std_ulogic;
 begin
   -- Assign the inputs to signals with reasonable names
@@ -22,22 +21,12 @@ begin
   rst_n <= KEY(0);
   x <= KEY(1);
 
-  -------------------------
-  -- The edge detector
-  -------------------------
-  -- Designpattern Register
-  -- Create a register with two flipflops with low active
-  -- asynchronous reset.
-  -- D-Input is connected to srnext
-  -- Q Outputs are connected to sr
-  sr <= "00" when rst_n = '0' else srnext when rising_edge(clk);
-
-  -- Implement the shift register function with next state logic
-  srnext(1) <= x;
-  srnext(0) <= sr(1);
-
-  -- Compute the output function from the shift register content
-  en <= sr(1) xor sr(0);
+  edge_inst: entity work.edge
+   port map(
+      clk    => clk,
+      rst_n  => rst_n,
+      x_i    => x,
+      edge_o => en);
 
   -- Set the outputs;
   EXP <= (7 downto 4 => '0',