add top_count solutions

6 files changed, 102 insertions, 28 deletions

diff --git a/sim/top_count/view_signals.gtkw b/sim/top_count/view_signals.gtkw
index 3fa122f..cd25497 100644
--- a/sim/top_count/view_signals.gtkw
+++ b/sim/top_count/view_signals.gtkw
@@ -1,21 +1,21 @@
 [*]
 [*] GTKWave Analyzer v3.3.118 (w)1999-2023 BSI
-[*] Fri May 10 10:14:46 2024
+[*] Fri May 10 14:33:39 2024
 [*]
 [dumpfile] "/home/caeuser/projects/dtlab/sim/top_count/t_top_count.ghw"
-[dumpfile_mtime] "Fri May 10 10:12:17 2024"
-[dumpfile_size] 1487
+[dumpfile_mtime] "Fri May 10 14:30:08 2024"
+[dumpfile_size] 10861
 [savefile] "/home/caeuser/projects/dtlab/sim/top_count/view_signals.gtkw"
 [timestart] 0
-[size] 1101 671
-[pos] -1 -1
-*-26.740849 48700000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[size] 1235 671
+[pos] -105 -11
+*-29.962776 109100000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] top.
 [treeopen] top.t_top_count.
 [treeopen] top.t_top_count.dut.
-[treeopen] top.t_top_count.dut.bin2seg_inst.
+[treeopen] top.t_top_count.dut.pwm_inst.
 [sst_width] 276
-[signals_width] 262
+[signals_width] 155
 [sst_expanded] 1
 [sst_vpaned_height] 216
 @28
@@ -34,5 +34,43 @@ top.t_top_count.sim_exp[1]
 top.t_top_count.sim_exp[0]
 @1001201
 -group_end
+@22
+#{top.t_top_count.dut.pwm_inst.cnt[3:0]} top.t_top_count.dut.pwm_inst.cnt[3] top.t_top_count.dut.pwm_inst.cnt[2] top.t_top_count.dut.pwm_inst.cnt[1] top.t_top_count.dut.pwm_inst.cnt[0]
+@28
+top.t_top_count.dut.pwm
+top.t_top_count.sim_x
+@c00024
+#{top.t_top_count.dut.cnt[3:0]} top.t_top_count.dut.cnt[3] top.t_top_count.dut.cnt[2] top.t_top_count.dut.cnt[1] top.t_top_count.dut.cnt[0]
+@28
+top.t_top_count.dut.cnt[3]
+top.t_top_count.dut.cnt[2]
+top.t_top_count.dut.cnt[1]
+top.t_top_count.dut.cnt[0]
+@1401200
+-group_end
+@c00022
+#{top.t_top_count.sim_ledg[3:0]} top.t_top_count.sim_ledg[3] top.t_top_count.sim_ledg[2] top.t_top_count.sim_ledg[1] top.t_top_count.sim_ledg[0]
+@28
+top.t_top_count.sim_ledg[3]
+top.t_top_count.sim_ledg[2]
+top.t_top_count.sim_ledg[1]
+top.t_top_count.sim_ledg[0]
+@1401200
+-group_end
+@c00022
+#{top.t_top_count.sim_ledr[9:0]} top.t_top_count.sim_ledr[9] top.t_top_count.sim_ledr[8] top.t_top_count.sim_ledr[7] top.t_top_count.sim_ledr[6] top.t_top_count.sim_ledr[5] top.t_top_count.sim_ledr[4] top.t_top_count.sim_ledr[3] top.t_top_count.sim_ledr[2] top.t_top_count.sim_ledr[1] top.t_top_count.sim_ledr[0]
+@28
+top.t_top_count.sim_ledr[9]
+top.t_top_count.sim_ledr[8]
+top.t_top_count.sim_ledr[7]
+top.t_top_count.sim_ledr[6]
+top.t_top_count.sim_ledr[5]
+top.t_top_count.sim_ledr[4]
+top.t_top_count.sim_ledr[3]
+top.t_top_count.sim_ledr[2]
+top.t_top_count.sim_ledr[1]
+top.t_top_count.sim_ledr[0]
+@1401200
+-group_end
 [pattern_trace] 1
 [pattern_trace] 0
diff --git a/src/cnt1sec.vhd b/src/cnt1sec.vhd
index a722ff9..14fad68 100644
--- a/src/cnt1sec.vhd
+++ b/src/cnt1sec.vhd
@@ -10,7 +10,11 @@ entity cnt1sec is
 end entity;
 
 architecture rtl of cnt1sec is
+  signal cnt, ncnt : unsigned(25 downto 0);
 begin
-
+  cnt <= (others => '0') when rst_n = '0' else ncnt when rising_edge(clk);
+  ncnt <= to_unsigned(0,cnt'length) when cnt = 4 else
+          cnt + 1;
+  en_o <= '1' when cnt = 0 else '0';
 end architecture rtl; 
 
diff --git a/src/cntm13.vhd b/src/cntm13.vhd
index 9da61d4..3a8bfa9 100644
--- a/src/cntm13.vhd
+++ b/src/cntm13.vhd
@@ -12,7 +12,13 @@ entity cntm13 is
 end entity;
 
 architecture rtl of cntm13 is
+  signal cnt, ncnt : unsigned(3 downto 0);
 begin
-
+  cnt <= to_unsigned(0,cnt'length) when rst_n = '0' else ncnt when en_i = '1' and rising_edge(clk);
+  ncnt <= to_unsigned(0,cnt'length) when up_i = '1' and cnt = 12 else
+          to_unsigned(12,cnt'length) when up_i = '0' and cnt = 0 else
+          cnt + 1 when up_i = '1' else
+          cnt - 1;
+cnt_o <= std_ulogic_vector(cnt);
 end architecture rtl; 
 
diff --git a/src/pwm.vhd b/src/pwm.vhd
index b23a170..9274bb9 100644
--- a/src/pwm.vhd
+++ b/src/pwm.vhd
@@ -11,7 +11,11 @@ entity pwm is
 end entity;
 
 architecture rtl of pwm is
+  signal cnt, ncnt : unsigned(3 downto 0);
 begin
-
-end architecture rtl; 
+  cnt <= "0000" when rst_n = '0' else ncnt when rising_edge(clk);
+  ncnt <= to_unsigned(0,cnt'length) when cnt = 14 else
+          cnt + 1;
+pwm_o <= '1' when cnt < unsigned(ctrl_i) else '0';
+end architecture rtl;
 
diff --git a/src/t_top_count.vhd b/src/t_top_count.vhd
index 0372a94..ca16d20 100644
--- a/src/t_top_count.vhd
+++ b/src/t_top_count.vhd
@@ -9,7 +9,6 @@ architecture beh of t_top_count is
   signal sim_clk     : std_ulogic;
   signal sim_rst_n   : std_ulogic;
   signal sim_x       : std_ulogic;
-  signal sim_y       : std_ulogic;
 
   signal sim_sw      : std_ulogic_vector(9 downto 0);
   signal sim_key     : std_ulogic_vector(3 downto 0);
@@ -40,16 +39,11 @@ begin
   -- Stimuli key push
   stim_p : process
   begin
-    sim_x <= '0';
-    wait until rising_edge(sim_rst_n);
-    for i in 0 to 5 loop
-      wait until falling_edge(sim_clk);
-    end loop;
     sim_x <= '1';
-    wait until falling_edge(sim_clk);
-    wait until falling_edge(sim_clk);
+    wait until rising_edge(sim_rst_n);
+    wait for 2000 ns;
     sim_x <= '0';
-    wait for 200 ns;
+    wait for 2000 ns;
     simstop <= true;
     wait;
   end process ;
@@ -70,6 +64,6 @@ begin
   sim_key(0) <= sim_rst_n;
   sim_key(1) <= sim_x;
   sim_key(3 downto 2) <= "00";
-  sim_sw <= "1010000001";
+  sim_sw <= "1010000100";
 
 end architecture beh;
\ No newline at end of file
diff --git a/src/top_count.vhd b/src/top_count.vhd
index 0a84349..ff25d1e 100644
--- a/src/top_count.vhd
+++ b/src/top_count.vhd
@@ -24,10 +24,38 @@ begin
   rst_n <= KEY(0);
   x <= KEY(1);
 
-  cnt <= "0000";
-  en <= '0';
-  pwm <= '0';
-  
+  cnt1sec_inst: entity work.cnt1sec
+   port map(
+      clk => clk,
+      rst_n => rst_n,
+      en_o => en
+  );
+
+  ringcnt_inst: entity work.ringcnt
+   port map(
+      clk => clk,
+      rst_n => rst_n,
+      en_i => en,
+      y_o => LEDR
+  );
+
+  cntm13_inst: entity work.cntm13
+   port map(
+      clk => clk,
+      rst_n => rst_n,
+      up_i => x,
+      en_i => en,
+      cnt_o => cnt
+  );
+
+  pwm_inst: entity work.pwm
+   port map(
+      clk => clk,
+      rst_n => rst_n,
+      ctrl_i => SW(3 downto 0),
+      pwm_o => pwm
+  );
+
   bin2seg_inst: entity work.bin2seg
    port map(
       bin_i => cnt,
@@ -40,7 +68,7 @@ begin
           2 => pwm,
           1 => rst_n,
           0 => clk);
-  LEDR <= SW;
-  LEDG <= KEY;
+  LEDG(3) <= pwm;
+  LEDG(2 downto 0) <= KEY(2 downto 0);
 
 end architecture rtl;
\ No newline at end of file