add solution top_hex

1 files changed, 14 insertions, 6 deletions

diff --git a/src/top_hex.vhd b/src/top_hex.vhd
index af0da77..2047e84 100644
--- a/src/top_hex.vhd
+++ b/src/top_hex.vhd
@@ -15,6 +15,7 @@ architecture rtl of top_hex is
   signal sa : signed(4 downto 0);
   signal sb : signed(4 downto 0);
   signal sum : signed(4 downto 0);
+  signal betrag : signed(4 downto 0);
 begin
 
 LEDR <= SW;
@@ -22,20 +23,27 @@ LEDR <= SW;
 sa <= signed(SW(4 downto 0));
 sb <= signed(SW(9 downto 5));
 sum <= sa + sb;
+betrag <= abs(sum);
 
-bin2seg_i1: entity work.bin2seg
+bin2seg_i0: entity work.bin2seg
+ port map(
+    bin_i => std_ulogic_vector(betrag(3 downto 0)),
+    seg_o => HEX0
+);
+
+bin2seg_i3: entity work.bin2seg
  port map(
     bin_i => "000" & std_ulogic(sum(4)),
-    seg_o => HEX1
+    seg_o => HEX3
 );
 
-bin2seg_i0: entity work.bin2seg
+bin2seg_i2: entity work.bin2seg
  port map(
     bin_i => std_ulogic_vector(sum(3 downto 0)),
-    seg_o => HEX0
+    seg_o => HEX2
 );
 
-HEX2 <= "1111111" when sa > -1 else "0000000";
-HEX3 <= "1111111";
+HEX1 <= "0001110" when sum = -16 else
+        "0111111" when sa < 0 else "1111111";
 
 end architecture rtl;