top_shift: add edge.vhd and ringcnt.vhd as empty modules

7 files changed, 64 insertions, 26 deletions

diff --git a/sim/top_shift/makefile.sources b/sim/top_shift/makefile.sources
index 460360c..fdaa601 100644
--- a/sim/top_shift/makefile.sources
+++ b/sim/top_shift/makefile.sources
@@ -1,4 +1,6 @@
 # All files which synthesized
 
 SYN_SOURCE_FILES = \
+../../src/edge.vhd \
+../../src/ringcnt.vhd \
 ../../src/top_shift.vhd
diff --git a/sim/top_shift/view_signals.gtkw b/sim/top_shift/view_signals.gtkw
index 8437be3..5a9014a 100644
--- a/sim/top_shift/view_signals.gtkw
+++ b/sim/top_shift/view_signals.gtkw
@@ -1,34 +1,34 @@
 [*]
 [*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
-[*] Wed Mar  6 22:54:48 2024
+[*] Sun Apr 28 09:10:12 2024
 [*]
 [dumpfile] "/home/caeuser/projects/dtlab/sim/top_shift/t_top_shift.ghw"
-[dumpfile_mtime] "Wed Mar  6 22:52:36 2024"
-[dumpfile_size] 1314
+[dumpfile_mtime] "Sun Apr 28 09:07:59 2024"
+[dumpfile_size] 1389
 [savefile] "/home/caeuser/projects/dtlab/sim/top_shift/view_signals.gtkw"
 [timestart] 0
-[size] 1000 600
-[pos] -1 -1
-*-26.740849 115500000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[size] 1101 671
+[pos] -210 -116
+*-26.740849 120000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] top.
 [treeopen] top.t_top_shift.
 [treeopen] top.t_top_shift.dut.
 [sst_width] 245
 [signals_width] 173
 [sst_expanded] 1
-[sst_vpaned_height] 185
+[sst_vpaned_height] 216
 @28
 top.t_top_shift.dut.clk
 top.t_top_shift.dut.rst_n
 top.t_top_shift.dut.x
 @800028
-#{top.t_top_shift.dut.sr[0:1]} top.t_top_shift.dut.sr[0] top.t_top_shift.dut.sr[1]
+#{top.t_top_shift.dut.sr[1:0]} top.t_top_shift.dut.sr[1] top.t_top_shift.dut.sr[0]
 @28
-top.t_top_shift.dut.sr[0]
 top.t_top_shift.dut.sr[1]
+top.t_top_shift.dut.sr[0]
+@29
+top.t_top_shift.dut.en
 @1001200
 -group_end
-@29
-top.t_top_shift.dut.y
 [pattern_trace] 1
 [pattern_trace] 0
diff --git a/src/edge.vhd b/src/edge.vhd
new file mode 100644
index 0000000..23dba70
--- /dev/null
+++ b/src/edge.vhd
@@ -0,0 +1,16 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity edge is
+  port (
+    clk     : in std_ulogic;
+    rst_n   : in std_ulogic;
+    x_i     : in std_ulogic;
+    edge_o  : out std_ulogic);
+end entity;
+
+architecture rtl of edge is
+begin
+
+end architecture rtl;
+
diff --git a/src/ringcnt.vhd b/src/ringcnt.vhd
new file mode 100644
index 0000000..5fc0d60
--- /dev/null
+++ b/src/ringcnt.vhd
@@ -0,0 +1,11 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ringcnt is 
+end entity;
+
+architecture rtl of ringcnt is
+begin
+
+end architecture rtl; 
+
diff --git a/src/t_top_shift.vhd b/src/t_top_shift.vhd
index 996b6d1..ddf76a1 100644
--- a/src/t_top_shift.vhd
+++ b/src/t_top_shift.vhd
@@ -37,10 +37,21 @@ begin
   sim_rst_n <= '0', '1' after 55 ns;
 
   -- Stimuli key push
-  sim_x <= '0', '1' after 135 ns, '0' after 195 ns;
-
-  -- Simulation stopper
-  simstop <= true after 300 ns;
+  stim_p : process
+  begin
+    sim_x <= '0';
+    wait until rising_edge(sim_rst_n);
+    for i in 0 to 5 loop
+      wait until falling_edge(sim_clk);
+    end loop;
+    sim_x <= '1';
+    wait until falling_edge(sim_clk);
+    wait until falling_edge(sim_clk);
+    sim_x <= '0';
+    wait for 200 ns;
+    simstop <= true;
+    wait;
+  end process ;
 
   -- Device under test instantiation
   dut : entity work.top_shift
@@ -57,7 +68,7 @@ begin
   sim_key(0) <= sim_rst_n;
   sim_key(1) <= sim_x;
   sim_key(3 downto 2) <= "00";
-  sim_sw <= "1010000101";
+  sim_sw <= "1010000001";
 
   -- Check the expansion port y output
   sim_y <= sim_exp(3);
diff --git a/src/top_shift.vhd b/src/top_shift.vhd
index f6036bc..d0c6f44 100644
--- a/src/top_shift.vhd
+++ b/src/top_shift.vhd
@@ -14,8 +14,8 @@ architecture rtl of top_shift is
   signal clk     : std_ulogic;
   signal rst_n   : std_ulogic;
   signal x       : std_ulogic;
-  signal sr, srnext : std_ulogic_vector(0 to 1);
-  signal en       : std_ulogic;
+  signal sr, srnext : std_ulogic_vector(1 downto 0);
+  signal en      : std_ulogic;
 begin
   -- Assign the inputs to signals with reasonable names
   clk <= CLOCK_50;
@@ -33,15 +33,11 @@ begin
   sr <= "00" when rst_n = '0' else srnext when rising_edge(clk);
 
   -- Implement the shift register function with next state logic
-  srnext(0) <= x;
-  srnext(1) <= sr(0);
+  srnext(1) <= x;
+  srnext(0) <= sr(1);
 
   -- Compute the output function from the shift register content
-  en <= sr(0) xor sr(1);
-
-  --------------------------
-  -- New code here
-  --------------------------
+  en <= sr(1) xor sr(0);
 
   -- Set the outputs;
   EXP <= (7 downto 4 => '0',
diff --git a/vhdl_ls.toml b/vhdl_ls.toml
index 4f5842d..ba7cd67 100644
--- a/vhdl_ls.toml
+++ b/vhdl_ls.toml
@@ -4,7 +4,9 @@ top_simple.files = [
     'src/top_simple.vhd'
     ]
 top_shift.files = [
-    'src/top_shift.vhd'
+    'src/edge.vhd'
+    ,'src/ringcnt.vhd'
+    ,'src/top_shift.vhd'
     ,'src/t_top_shift.vhd'
     ]
 top_hex.files = [